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optimized avs_pending_reads in vortex_afu.sv

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This commit is contained in:
Blaise Tine
2020-05-23 19:54:37 -04:00
parent 507622f1a1
commit 9398c07afb
4 changed files with 3507 additions and 25451 deletions
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6
driver/rtlsim/Makefile
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@@ -16,9 +16,9 @@ DBG_PRINT=$(DBG_PRINT_FLAGS)
#MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4 #MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4
#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4 #MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4
MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 #MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
#DEBUG = 1 DEBUG = 1
CFLAGS += -fPIC CFLAGS += -fPIC
@@ -48,7 +48,7 @@ ifdef DEBUG
VL_FLAGS += --trace $(DBG_PRINT) VL_FLAGS += --trace $(DBG_PRINT)
CFLAGS += -DVCD_OUTPUT CFLAGS += -DVCD_OUTPUT
else else
CFLAGS += -DNDEBUG CFLAGS += -DNDEBUG $(DBG_PRINT)
VL_FLAGS += -DNDEBUG VL_FLAGS += -DNDEBUG
endif endif

28922
driver/tests/demo/run.log
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File diff suppressed because it is too large Load Diff

6
hw/Makefile
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@@ -31,7 +31,7 @@ INCLUDE = -I./rtl/ -I./rtl/libs -I./rtl/interfaces -I./rtl/pipe_regs -I./rtl/cac
SRCS += ./simulate/testbench.cpp ./simulate/simulator.cpp SRCS += ./simulate/testbench.cpp ./simulate/simulator.cpp
DBG += --trace DBG += -DVCD_OUTPUT $(DBG_PRINT)
THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
@@ -44,7 +44,7 @@ gen-s: build_config
verilator $(VF) -DNDEBUG -cc Vortex_Socket.v -CFLAGS '$(CF) -DNDEBUG' verilator $(VF) -DNDEBUG -cc Vortex_Socket.v -CFLAGS '$(CF) -DNDEBUG'
gen-sd: build_config gen-sd: build_config
verilator $(VF) -cc Vortex_Socket.v $(DBG_PRINT) -CFLAGS '$(CF) -g -O0 -DVCD_OUTPUT' $(DBG) verilator $(VF) -cc Vortex_Socket.v $(DBG_PRINT) -CFLAGS '$(CF) -g -O0 $(DBG)' --trace $(DBG)
gen-st: build_config gen-st: build_config
verilator $(VF) -DNDEBUG -cc Vortex_Socket.v -CFLAGS '$(CF) -DNDEBUG -O2' --threads $(THREADS) verilator $(VF) -DNDEBUG -cc Vortex_Socket.v -CFLAGS '$(CF) -DNDEBUG -O2' --threads $(THREADS)
@@ -53,7 +53,7 @@ gen-m: build_config
verilator $(VF) -DNDEBUG -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)' verilator $(VF) -DNDEBUG -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)'
gen-md: build_config gen-md: build_config
verilator $(VF) -cc Vortex_Socket.v $(MULTICORE) $(DBG_PRINT) -CFLAGS '$(CF) -g -O0 -DVCD_OUTPUT $(MULTICORE)' $(DBG) verilator $(VF) -cc Vortex_Socket.v $(MULTICORE) $(DBG_PRINT) -CFLAGS '$(CF) -g -O0 $(DBG) $(MULTICORE)' --trace $(DBG)
gen-mt: build_config gen-mt: build_config
verilator $(VF) -DNDEBUG -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(MULTICORE)' --threads $(THREADS) verilator $(VF) -DNDEBUG -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(MULTICORE)' --threads $(THREADS)

24
hw/opae/vortex_afu.sv
View File

@@ -112,7 +112,6 @@ logic avs_rdq_pop;
t_local_mem_data avs_rdq_dout; t_local_mem_data avs_rdq_dout;
logic avs_rdq_empty; logic avs_rdq_empty;
logic avs_rdq_full; logic avs_rdq_full;
logic [`LOG2UP(AVS_RD_QUEUE_SIZE+1)-1:0] avs_rdq_size;
// CSR variables ////////////////////////////////////////////////////////////// // CSR variables //////////////////////////////////////////////////////////////
@@ -318,7 +317,7 @@ logic cci_dram_req_write_fire;
logic vx_dram_req_read_fire; logic vx_dram_req_read_fire;
logic vx_dram_req_write_fire; logic vx_dram_req_write_fire;
logic vx_dram_rsp_fire; logic vx_dram_rsp_fire;
logic [`LOG2UP(AVS_RD_QUEUE_SIZE+1)-1:0] avs_pending_reads, avs_pending_rds_next; logic [`LOG2UP(AVS_RD_QUEUE_SIZE+1)-1:0] avs_pending_reads, avs_pending_reads_next;
t_ccip_clAddr next_avs_address; t_ccip_clAddr next_avs_address;
always_comb always_comb
@@ -333,7 +332,7 @@ begin
&& avs_write_ctr < csr_data_size); && avs_write_ctr < csr_data_size);
cci_dram_req_read_fire = (state == STATE_READ) cci_dram_req_read_fire = (state == STATE_READ)
&& ((avs_pending_reads + avs_rdq_size) < AVS_RD_QUEUE_SIZE) && ((avs_pending_reads < AVS_RD_QUEUE_SIZE)
&& !avs_waitrequest && !avs_waitrequest
&& avs_read_ctr < csr_data_size; && avs_read_ctr < csr_data_size;
@@ -347,14 +346,14 @@ begin
vx_dram_rsp_fire = vx_dram_rsp_valid && vx_dram_rsp_ready; vx_dram_rsp_fire = vx_dram_rsp_valid && vx_dram_rsp_ready;
if ((cci_dram_req_read_fire || vx_dram_req_read_fire) if ((cci_dram_req_read_fire || vx_dram_req_read_fire)
&& ~avs_readdatavalid) begin && ~avs_rdq_pop) begin
avs_pending_rds_next = avs_pending_reads + 1; avs_pending_reads_next = avs_pending_reads + 1;
end else end else
if (~(cci_dram_req_read_fire || vx_dram_req_read_fire) if (~(cci_dram_req_read_fire || vx_dram_req_read_fire)
&& avs_readdatavalid) begin && avs_rdq_pop) begin
avs_pending_rds_next = avs_pending_reads - 1; avs_pending_reads_next = avs_pending_reads - 1;
end else begin end else begin
avs_pending_rds_next = avs_pending_reads; avs_pending_reads_next = avs_pending_reads;
end end
cmd_write_done = (avs_write_ctr >= csr_data_size); cmd_write_done = (avs_write_ctr >= csr_data_size);
@@ -421,11 +420,11 @@ begin
`ifdef DBG_PRINT_OPAE `ifdef DBG_PRINT_OPAE
if (avs_readdatavalid) begin if (avs_readdatavalid) begin
$display("%t: AVS Rd Rsp: pending=%0d", $time, avs_pending_rds_next); $display("%t: AVS Rd Rsp: pending=%0d", $time, avs_pending_reads_next);
end end
`endif `endif
avs_pending_reads <= avs_pending_rds_next; avs_pending_reads <= avs_pending_reads_next;
end end
end end
@@ -435,7 +434,7 @@ always_comb
begin begin
vx_dram_req_ready = vortex_enabled vx_dram_req_ready = vortex_enabled
&& !avs_waitrequest && !avs_waitrequest
&& ((avs_pending_reads + avs_rdq_size) < AVS_RD_QUEUE_SIZE); && (avs_pending_reads < AVS_RD_QUEUE_SIZE);
end end
// Vortex DRAM fill response // Vortex DRAM fill response
@@ -492,8 +491,7 @@ VX_generic_queue #(
.pop (avs_rdq_pop), .pop (avs_rdq_pop),
.data_out (avs_rdq_dout), .data_out (avs_rdq_dout),
.empty (avs_rdq_empty), .empty (avs_rdq_empty),
.full (avs_rdq_full), .full (avs_rdq_full)
.size (avs_rdq_size)
); );
// CCI Read Request /////////////////////////////////////////////////////////// // CCI Read Request ///////////////////////////////////////////////////////////