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Created a testbench and simulated the read/write of the register file

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Lingjun Zhu
2019-10-18 22:55:34 -04:00
parent 4cae140ac1
commit 93531715bb
2 changed files with 88 additions and 0 deletions
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models/memory/cln28hpc/rf2_32x128_wm1/env_vsim Normal file
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source /tools/mentor/modelsim/ms106a/cshrc.modelsim