diff --git a/.travis.yml b/.travis.yml index a9d614d1..e1644a83 100644 --- a/.travis.yml +++ b/.travis.yml @@ -41,11 +41,14 @@ jobs: name: config script: cp -r $PWD ../build4 && cd ../build4 && ./ci/regression.sh -config - stage: test - name: stress - script: cp -r $PWD ../build5 && cd ../build5 && ./ci/regression.sh -stress + name: stress1 + script: cp -r $PWD ../build5 && cd ../build5 && ./ci/regression.sh -stress1 + - stage: test + name: stress2 + script: cp -r $PWD ../build6 && cd ../build6 && ./ci/regression.sh -stress2 - stage: test name: compiler - script: cp -r $PWD ../build6 && cd ../build6 && ./ci/test_compiler.sh + script: cp -r $PWD ../build7 && cd ../build7 && ./ci/test_compiler.sh after_success: # Gather code coverage diff --git a/ci/regression.sh b/ci/regression.sh index 680ae78a..c591070c 100755 --- a/ci/regression.sh +++ b/ci/regression.sh @@ -102,7 +102,16 @@ CONFIGS="-DMEM_LATENCY=100 -DMEM_RQ_SIZE=4 -DMEM_STALLS_MODULO=4" ./ci/blackbox. echo "configuration tests done!" } -stress() +stress1() +{ +echo "begin stress tests..." + +./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=sgemm --args="-n256" + +echo "stress tests done!" +} + +stress2() { echo "begin stress tests..." @@ -113,7 +122,7 @@ echo "stress tests done!" usage() { - echo "usage: regression [-coverage] [-cluster] [-debug] [-config] [-stress] [-all] [-h|--help]" + echo "usage: regression [-coverage] [-cluster] [-debug] [-config] [-stress#n] [-all] [-h|--help]" } while [ "$1" != "" ]; do @@ -126,13 +135,16 @@ while [ "$1" != "" ]; do ;; -config ) config ;; - -stress ) stress + -stress1 ) stress1 + ;; + -stress2 ) stress2 ;; -all ) coverage cluster debug config - stress + stress1 + stress2 ;; -h | --help ) usage exit diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v index 537d759a..1dfaa832 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.v @@ -47,6 +47,8 @@ module VX_icache_stage #( .dout({rsp_PC, rsp_tmask}) ); + `RUNTIME_ASSERT((!ifetch_req_if.valid || ifetch_req_if.PC >= `STARTUP_ADDR), ("invalid PC=%0h", ifetch_req_if.PC)) + // Icache Request assign icache_req_if.valid = ifetch_req_if.valid; assign icache_req_if.addr = ifetch_req_if.PC[31:2];