MSHR Redesign: removed fifo replay constraints and overheads
This commit is contained in:
Blaise Tine
291
hw/rtl/cache/VX_miss_resrv.v
vendored
291
hw/rtl/cache/VX_miss_resrv.v
vendored
@@ -19,7 +19,9 @@ module VX_miss_resrv #(
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parameter MSHR_SIZE = 1,
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parameter ALM_FULL = (MSHR_SIZE-1),
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// core request tag size
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parameter CORE_TAG_WIDTH = 1
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parameter CORE_TAG_WIDTH = 1,
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localparam MSHR_ADDR_WIDTH = $clog2(MSHR_SIZE)
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) (
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input wire clk,
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input wire reset,
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@@ -28,159 +30,147 @@ module VX_miss_resrv #(
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`IGNORE_UNUSED_BEGIN
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input wire[31:0] deq_debug_pc,
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input wire[`NW_BITS-1:0] deq_debug_wid,
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input wire[31:0] enq_debug_pc,
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input wire[`NW_BITS-1:0] enq_debug_wid,
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input wire[31:0] lkp_debug_pc,
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input wire[`NW_BITS-1:0] lkp_debug_wid,
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input wire[31:0] rel_debug_pc,
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input wire[`NW_BITS-1:0] rel_debug_wid,
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`IGNORE_UNUSED_END
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`endif
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// enqueue
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input wire enqueue,
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input wire [`LINE_ADDR_WIDTH-1:0] enqueue_addr,
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input wire [`MSHR_DATA_WIDTH-1:0] enqueue_data,
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input wire enqueue_is_mshr,
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input wire enqueue_as_ready,
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output wire enqueue_full,
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output wire enqueue_almfull,
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// allocate
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input wire allocate_valid,
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input wire [`LINE_ADDR_WIDTH-1:0] allocate_addr,
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input wire [`MSHR_DATA_WIDTH-1:0] allocate_data,
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output wire [MSHR_ADDR_WIDTH-1:0] allocate_id,
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output wire allocate_ready,
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// fill
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input wire fill_start,
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input wire [`LINE_ADDR_WIDTH-1:0] fill_addr,
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input wire fill_valid,
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input wire [MSHR_ADDR_WIDTH-1:0] fill_id,
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// lookup
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input wire lookup_valid,
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input wire lookup_replay,
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input wire [MSHR_ADDR_WIDTH-1:0] lookup_id,
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input wire [`LINE_ADDR_WIDTH-1:0] lookup_addr,
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output wire lookup_match,
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input wire lookup_fill,
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// dequeue
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output wire dequeue_valid,
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output wire [MSHR_ADDR_WIDTH-1:0] dequeue_id,
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output wire [`LINE_ADDR_WIDTH-1:0] dequeue_addr,
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output wire [`MSHR_DATA_WIDTH-1:0] dequeue_data,
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input wire dequeue_ready,
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// schedule
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input wire schedule,
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output wire schedule_valid,
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output wire [`LINE_ADDR_WIDTH-1:0] schedule_addr,
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output wire [`MSHR_DATA_WIDTH-1:0] schedule_data,
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// dequeue
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input wire dequeue
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// release
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input wire release_valid,
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input wire [MSHR_ADDR_WIDTH-1:0] release_id
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);
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`UNUSED_PARAM (CACHE_ID)
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`UNUSED_PARAM (BANK_ID)
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localparam ADDRW = $clog2(MSHR_SIZE);
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reg [MSHR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table;
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reg [MSHR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table, addr_table_n;
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reg [MSHR_SIZE-1:0] valid_table, valid_table_n;
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reg [MSHR_SIZE-1:0] ready_table, ready_table_n;
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reg [ADDRW-1:0] head_ptr, head_ptr_n;
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reg [ADDRW-1:0] tail_ptr, tail_ptr_n;
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reg [ADDRW-1:0] restore_ptr, restore_ptr_n;
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reg [ADDRW-1:0] schedule_ptr, schedule_ptr_n;
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reg [ADDRW-1:0] used_r;
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reg alm_full_r, full_r;
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reg valid_out_r;
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reg allocate_rdy_r, allocate_rdy_n;
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reg [MSHR_ADDR_WIDTH-1:0] allocate_id_r, allocate_id_n;
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reg dequeue_val_r, dequeue_val_n, dequeue_val_x;
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reg [MSHR_ADDR_WIDTH-1:0] dequeue_id_r, dequeue_id_n, dequeue_id_x;
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wire [MSHR_SIZE-1:0] valid_address_match;
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for (genvar i = 0; i < MSHR_SIZE; i++) begin
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assign valid_address_match[i] = valid_table[i] && (addr_table[i] == lookup_addr);
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reg [MSHR_SIZE-1:0] valid_table_x;
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reg [MSHR_SIZE-1:0] ready_table_x;
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wire [MSHR_SIZE-1:0] addr_match;
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wire allocate_fire = allocate_valid && allocate_ready;
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wire dequeue_fire = dequeue_valid && dequeue_ready;
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for (genvar i = 0; i < MSHR_SIZE; ++i) begin
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assign addr_match[i] = (i != lookup_id) && valid_table[i] && (addr_table[i] == lookup_addr);
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end
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always @(*) begin
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valid_table_x = valid_table;
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ready_table_x = ready_table;
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if (dequeue_fire) begin
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valid_table_x[dequeue_id] = 0;
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end
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if (lookup_replay) begin
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ready_table_x |= addr_match;
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end
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end
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wire push_new = enqueue && !enqueue_is_mshr;
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VX_priority_encoder #(
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.N (MSHR_SIZE)
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) dequeue_pe (
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.data_in (valid_table_x & ready_table_x),
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.index (dequeue_id_x),
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.valid_out (dequeue_val_x),
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`UNUSED_PIN (onehot)
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);
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wire restore = enqueue && enqueue_is_mshr;
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VX_priority_encoder #(
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.N (MSHR_SIZE)
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) allocate_pe (
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.data_in (~valid_table_n),
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.index (allocate_id_n),
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.valid_out (allocate_rdy_n),
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`UNUSED_PIN (onehot)
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);
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always @(*) begin
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valid_table_n = valid_table;
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ready_table_n = ready_table;
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head_ptr_n = head_ptr;
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tail_ptr_n = tail_ptr;
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schedule_ptr_n = schedule_ptr;
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restore_ptr_n = restore_ptr;
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valid_table_n = valid_table_x;
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ready_table_n = ready_table_x;
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addr_table_n = addr_table;
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dequeue_val_n = dequeue_val_r;
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dequeue_id_n = dequeue_id_r;
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if (lookup_fill) begin
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// unlock pending requests for scheduling
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ready_table_n |= valid_address_match;
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if (dequeue_fire) begin
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dequeue_val_n = dequeue_val_x;
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dequeue_id_n = dequeue_id_x;
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end
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if (schedule) begin
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// schedule next entry
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schedule_ptr_n = schedule_ptr + 1;
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valid_table_n[schedule_ptr] = 0;
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ready_table_n[schedule_ptr] = 0;
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if (allocate_fire) begin
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valid_table_n[allocate_id] = 1;
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ready_table_n[allocate_id] = 0;
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addr_table_n[allocate_id] = allocate_addr;
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end
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if (fill_start && (fill_addr == addr_table[schedule_ptr])) begin
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ready_table_n[schedule_ptr] = valid_table[schedule_ptr];
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if (fill_valid) begin
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dequeue_val_n = 1;
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dequeue_id_n = fill_id;
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end
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if (push_new) begin
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// push new entry
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valid_table_n[tail_ptr] = 1;
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ready_table_n[tail_ptr] = enqueue_as_ready;
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tail_ptr_n = tail_ptr + 1;
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end else if (restore) begin
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// restore schedule, returning missed mshr entry
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valid_table_n[restore_ptr] = 1;
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ready_table_n[restore_ptr] = enqueue_as_ready;
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restore_ptr_n = restore_ptr + 1;
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schedule_ptr_n = head_ptr;
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end else if (dequeue) begin
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// clear scheduled entry
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head_ptr_n = head_ptr + 1;
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restore_ptr_n = head_ptr_n;
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end
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if (release_valid) begin
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valid_table_n[release_id] = 0;
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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valid_table <= 0;
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ready_table <= 0;
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head_ptr <= 0;
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tail_ptr <= 0;
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schedule_ptr <= 0;
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restore_ptr <= 0;
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used_r <= 0;
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alm_full_r <= 0;
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full_r <= 0;
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valid_out_r <= 0;
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valid_table <= 0;
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allocate_rdy_r <= 0;
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dequeue_val_r <= 0;
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end else begin
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if (schedule) begin
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assert(schedule_valid);
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assert(!fill_start);
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assert(!restore);
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end
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if (push_new) begin
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assert(!full_r);
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end else if (restore) begin
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assert(!schedule);
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end
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if (push_new) begin
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if (!dequeue) begin
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if (used_r == ADDRW'(ALM_FULL-1))
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alm_full_r <= 1;
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if (used_r == ADDRW'(MSHR_SIZE-1))
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full_r <= 1;
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end
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end else if (dequeue) begin
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if (used_r == ADDRW'(ALM_FULL))
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alm_full_r <= 0;
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full_r <= 0;
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end
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used_r <= used_r + ADDRW'($signed(2'(push_new) - 2'(dequeue)));
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valid_table <= valid_table_n;
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ready_table <= ready_table_n;
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head_ptr <= head_ptr_n;
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tail_ptr <= tail_ptr_n;
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schedule_ptr <= schedule_ptr_n;
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restore_ptr <= restore_ptr_n;
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valid_out_r <= ready_table_n[schedule_ptr_n];
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valid_table <= valid_table_n;
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allocate_rdy_r <= allocate_rdy_n;
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dequeue_val_r <= dequeue_val_n;
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end
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ready_table <= ready_table_n;
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addr_table <= addr_table_n;
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dequeue_id_r <= dequeue_id_n;
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allocate_id_r <= allocate_id_n;
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if (push_new) begin
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addr_table[tail_ptr] <= enqueue_addr;
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end
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assert(!allocate_fire || !valid_table[allocate_id_r]);
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assert(!release_valid || valid_table[release_id]);
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end
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`RUNTIME_ASSERT((!fill_valid || valid_table[fill_id]), ("%t: *** cache%0d:%0d invalid fill: addr=%0h, id=%0d", $time, CACHE_ID, BANK_ID,
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`LINE_TO_BYTE_ADDR(addr_table[fill_id], BANK_ID), fill_id))
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VX_dp_ram #(
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.DATAW (`MSHR_DATA_WIDTH),
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.SIZE (MSHR_SIZE),
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@@ -188,43 +178,56 @@ module VX_miss_resrv #(
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.FASTRAM (1)
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) entries (
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.clk (clk),
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.waddr (tail_ptr),
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.raddr (schedule_ptr),
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.wren (push_new),
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.waddr (allocate_id_r),
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.raddr (dequeue_id_r),
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.wren (allocate_valid),
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.byteen (1'b1),
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.rden (1'b1),
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.din (enqueue_data),
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.dout (schedule_data)
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.din (allocate_data),
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.dout (dequeue_data)
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);
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assign lookup_match = (| valid_address_match);
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assign schedule_valid = valid_out_r;
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assign schedule_addr = addr_table[schedule_ptr];
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assign enqueue_almfull = alm_full_r;
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assign enqueue_full = full_r;
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assign allocate_ready = allocate_rdy_r;
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assign allocate_id = allocate_id_r;
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assign dequeue_valid = dequeue_val_r;
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assign dequeue_id = dequeue_id_r;
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assign dequeue_addr = addr_table[dequeue_id_r];
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assign lookup_match = (| addr_match);
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`UNUSED_VAR (lookup_valid)
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`ifdef DBG_PRINT_CACHE_MSHR
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always @(posedge clk) begin
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if (lookup_fill || schedule || enqueue || dequeue) begin
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if (schedule)
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$display("%t: cache%0d:%0d mshr-schedule: addr%0d=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, schedule_ptr, `LINE_TO_BYTE_ADDR(schedule_addr, BANK_ID), deq_debug_wid, deq_debug_pc);
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if (enqueue) begin
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if (enqueue_is_mshr)
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$display("%t: cache%0d:%0d mshr-restore: addr%0d=%0h, ready=%b", $time, CACHE_ID, BANK_ID, restore_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr, BANK_ID), enqueue_as_ready);
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else
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$display("%t: cache%0d:%0d mshr-enqueue: addr%0d=%0h, ready=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, tail_ptr, `LINE_TO_BYTE_ADDR(enqueue_addr, BANK_ID), enqueue_as_ready, enq_debug_wid, enq_debug_pc);
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end
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if (dequeue)
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$display("%t: cache%0d:%0d mshr-dequeue addr%0d, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, head_ptr, enq_debug_wid, enq_debug_pc);
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always @(posedge clk) begin
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if (allocate_fire || fill_valid || dequeue_fire || lookup_replay || lookup_valid || release_valid) begin
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if (allocate_fire)
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$display("%t: cache%0d:%0d mshr-allocate: addr=%0h, id=%0d, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID,
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`LINE_TO_BYTE_ADDR(allocate_addr, BANK_ID), allocate_id, deq_debug_wid, deq_debug_pc);
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if (fill_valid)
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$display("%t: cache%0d:%0d mshr-fill: addr=%0h, id=%0d", $time, CACHE_ID, BANK_ID,
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`LINE_TO_BYTE_ADDR(addr_table[fill_id], BANK_ID), fill_id);
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if (dequeue_fire)
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$display("%t: cache%0d:%0d mshr-dequeue: addr=%0h, id=%0d, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID,
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`LINE_TO_BYTE_ADDR(dequeue_addr, BANK_ID), dequeue_id_r, deq_debug_wid, deq_debug_pc);
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if (lookup_replay)
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$display("%t: cache%0d:%0d mshr-replay: addr=%0h, id=%0d", $time, CACHE_ID, BANK_ID,
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`LINE_TO_BYTE_ADDR(lookup_addr, BANK_ID), lookup_id);
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if (lookup_valid)
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$display("%t: cache%0d:%0d mshr-lookup: addr=%0h, id=%0d, match=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID,
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`LINE_TO_BYTE_ADDR(lookup_addr, BANK_ID), lookup_id, lookup_match, lkp_debug_wid, lkp_debug_pc);
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if (release_valid)
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$display("%t: cache%0d:%0d mshr-release id=%0d, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID,
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release_id, rel_debug_wid, rel_debug_pc);
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$write("%t: cache%0d:%0d mshr-table", $time, CACHE_ID, BANK_ID);
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for (integer j = 0; j < MSHR_SIZE; j++) begin
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if (valid_table[j]) begin
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for (integer i = 0; i < MSHR_SIZE; ++i) begin
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if (valid_table[i]) begin
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$write(" ");
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if (schedule_ptr == $bits(schedule_ptr)'(j)) $write("*");
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if (~ready_table[j]) $write("!");
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$write("addr%0d=%0h", j, `LINE_TO_BYTE_ADDR(addr_table[j], BANK_ID));
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if (ready_table[i])
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$write("*");
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$write("%0d=%0h", i, `LINE_TO_BYTE_ADDR(addr_table[i], BANK_ID));
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end
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end
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end
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$write("\n");
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end
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end
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