simx refactoring, fixed simple.hex, compatibility with rtlsim and vlsim complete, added to regression suite

This commit is contained in:
Blaise Tine
2021-03-08 23:58:33 -08:00
parent 71e9745e68
commit 907e6868cd
19 changed files with 88376 additions and 95959 deletions

View File

@@ -7,18 +7,14 @@
#include "types.h"
namespace vortex {
void *consoleInputThread(void *);
struct BadAddress {};
class MemDevice {
public:
virtual ~MemDevice() {}
virtual Size size() const = 0;
virtual Word read(Addr) = 0;
virtual void write(Addr, Word) = 0;
virtual Byte *base() {
return NULL;
}
virtual void read(Addr addr, void *data, Size size) = 0;
virtual void write(Addr addr, const void *data, Size size) = 0;
};
///////////////////////////////////////////////////////////////////////////////
@@ -29,20 +25,16 @@ public:
RamMemDevice(const char *filename, Size wordSize);
~RamMemDevice() {}
virtual Word read(Addr);
virtual void write(Addr, Word);
void read(Addr addr, void *data, Size size) override;
void write(Addr addr, const void *data, Size size) override;
virtual Size size() const {
return contents_.size();
};
virtual Byte *base() {
return &contents_[0];
}
protected:
Size wordSize_;
std::vector<Byte> contents_;
Size wordSize_;
};
///////////////////////////////////////////////////////////////////////////////
@@ -59,65 +51,14 @@ public:
~RomMemDevice();
virtual void write(Addr, Word);
};
///////////////////////////////////////////////////////////////////////////////
class Core;
class DiskControllerMemDevice : public MemDevice {
public:
DiskControllerMemDevice(Size wordSize, Size blockSize, Core &c);
virtual Word read(Addr);
virtual void write(Addr, Word);
virtual Size size() const {
return uint64_t(wordSize_) * 6;
}
void addDisk(Byte *file, Size n) {
disks_.push_back(Disk(file, n));
}
private:
enum Status {
OK = 0,
INVALID_DISK,
INVALID_BLOCK
};
struct Disk {
Disk(Byte *f, Size n)
: file(f)
, blocks(n)
{}
Byte *file;
Size blocks;
};
Word curDisk_;
Word curBlock_;
Word nBlocks_;
Word physAddr_;
Word command_;
Word status_;
Size wordSize_;
Size blockSize_;
Core &core_;
std::vector<Disk> disks_;
void write(Addr addr, const void *data, Size size) override;
};
///////////////////////////////////////////////////////////////////////////////
class MemoryUnit {
public:
MemoryUnit(Size pageSize, Size addrBytes, bool disableVm = false);
void attach(MemDevice &m, Addr start, Addr end);
struct PageFault {
PageFault(Addr a, bool nf)
: faultAddr(a)
@@ -127,24 +68,27 @@ public:
bool notFound;
};
Word read(Addr, bool sup);
Word fetch(Addr, bool sup);
void write(Addr, Word, bool sup, Size);
MemoryUnit(Size pageSize, Size addrBytes, bool disableVm = false);
void attach(MemDevice &m, Addr start, Addr end);
void read(Addr addr, void *data, Size size, bool sup);
void write(Addr addr, const void *data, Size size, bool sup);
void tlbAdd(Addr virt, Addr phys, Word flags);
void tlbRm(Addr va);
void tlbFlush() {
tlb_.clear();
}
private:
class ADecoder {
public:
ADecoder() {}
Word read(Addr a, bool sup, Size wordSize);
void write(Addr a, Word w, bool sup, Size wordSize);
void read(Addr addr, void *data, Size size);
void write(Addr addr, const void *data, Size size);
void map(Addr start, Addr end, MemDevice &md);
private:
@@ -196,22 +140,8 @@ public:
void clear();
Size size() const override;
void write(Addr addr, Word w) override;
Word read(Addr addr) override;
Byte *base() override;
void read(uint32_t address, uint32_t length, uint8_t *data);
void write(uint32_t address, uint32_t length, uint8_t *data);
void writeWord(uint32_t address, uint32_t *data);
void writeHalf(uint32_t address, uint32_t *data);
void writeByte(uint32_t address, uint32_t *data);
void read(Addr addr, void *data, Size size) override;
void write(Addr addr, const void *data, Size size) override;
void loadHexImage(std::string path);
@@ -219,10 +149,6 @@ private:
uint8_t *get(uint32_t address);
void getBlock(uint32_t address, uint8_t *data);
void getWord(uint32_t address, uint32_t *data);
std::vector<uint8_t*> mem_;
uint32_t page_bits_;
uint32_t size_;