simx refactoring, fixed simple.hex, compatibility with rtlsim and vlsim complete, added to regression suite
This commit is contained in:
Blaise Tine
256
simX/mem.cpp
256
simX/mem.cpp
@@ -28,31 +28,52 @@ RamMemDevice::RamMemDevice(const char *filename, Size wordSize)
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contents_.push_back(input.get());
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} while (input);
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while (contents_.size() % wordSize)
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while (contents_.size() & (wordSize-1))
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contents_.push_back(0x00);
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}
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RamMemDevice::RamMemDevice(Size size, Size wordSize)
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: wordSize_(wordSize)
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, contents_(size)
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: contents_(size)
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, wordSize_(wordSize)
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{}
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void RomMemDevice::write(Addr, Word) {
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std::cout << "Attempt to write to ROM.\n";
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void RamMemDevice::read(Addr addr, void *data, Size size) {
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auto addr_end = addr + size;
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if ((addr & (wordSize_-1))
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|| (addr_end & (wordSize_-1))
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|| (addr_end <= contents_.size())) {
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std::cout << "lookup of 0x" << std::hex << (addr_end-1) << " failed.\n";
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throw BadAddress();
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}
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const Byte *s = contents_.data() + addr;
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for (Byte *d = (Byte*)data, *de = d + size; d != de;) {
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*d++ = *s++;
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}
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}
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void RamMemDevice::write(Addr addr, const void *data, Size size) {
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auto addr_end = addr + size;
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if ((addr & (wordSize_-1))
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|| (addr_end & (wordSize_-1))
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|| (addr_end <= contents_.size())) {
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std::cout << "lookup of 0x" << std::hex << (addr_end-1) << " failed.\n";
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throw BadAddress();
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}
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const Byte *s = (const Byte*)data;
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for (Byte *d = contents_.data() + addr, *de = d + size; d != de;) {
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*d++ = *s++;
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}
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}
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///////////////////////////////////////////////////////////////////////////////
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void RomMemDevice::write(Addr /*addr*/, const void* /*data*/, Size /*size*/) {
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std::cout << "attempt to write to ROM.\n";
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std::abort();
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}
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Word RamMemDevice::read(Addr addr) {
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D(2, "RAM read, addr=0x" << std::hex << addr);
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Word w = readWord(contents_, addr, wordSize_ - addr % wordSize_);
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return w;
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}
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void RamMemDevice::write(Addr addr, Word w) {
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D(2, "RAM write, addr=0x" << std::hex << addr);
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writeWord(contents_, addr, wordSize_ - addr % wordSize_, w);
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}
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///////////////////////////////////////////////////////////////////////////////
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bool MemoryUnit::ADecoder::lookup(Addr a, Size wordSize, mem_accessor_t* ma) {
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@@ -74,32 +95,22 @@ void MemoryUnit::ADecoder::map(Addr a, Addr e, MemDevice &m) {
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entries_.emplace_back(entry);
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}
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Word MemoryUnit::ADecoder::read(Addr a, bool /*sup*/, Size wordSize) {
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void MemoryUnit::ADecoder::read(Addr addr, void *data, Size size) {
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mem_accessor_t ma;
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if (!this->lookup(a, wordSize, &ma)) {
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std::cout << "lookup of 0x" << std::hex << a << " failed.\n";
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if (!this->lookup(addr, size, &ma)) {
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std::cout << "lookup of 0x" << std::hex << addr << " failed.\n";
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throw BadAddress();
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}
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return ma.md->read(ma.addr);
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ma.md->read(ma.addr, data, size);
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}
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void MemoryUnit::ADecoder::write(Addr a, Word w, bool /*sup*/, Size wordSize) {
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void MemoryUnit::ADecoder::write(Addr addr, const void *data, Size size) {
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mem_accessor_t ma;
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if (!this->lookup(a, wordSize, &ma)) {
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std::cout << "lookup of 0x" << std::hex << a << " failed.\n";
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if (!this->lookup(addr, size, &ma)) {
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std::cout << "lookup of 0x" << std::hex << addr << " failed.\n";
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throw BadAddress();
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}
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RAM *ram = (RAM *)ma.md;
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switch (wordSize) {
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case 1:
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ram->writeByte(ma.addr, &w);
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break;
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case 2:
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ram->writeHalf(ma.addr, &w);
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break;
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default:
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ram->writeWord(ma.addr, &w);
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}
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ma.md->write(ma.addr, data, size);
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}
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///////////////////////////////////////////////////////////////////////////////
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@@ -132,44 +143,28 @@ MemoryUnit::TLBEntry MemoryUnit::tlbLookup(Addr vAddr, Word flagMask) {
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}
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}
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Word MemoryUnit::read(Addr vAddr, bool sup) {
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void MemoryUnit::read(Addr addr, void *data, Size size, bool sup) {
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Addr pAddr;
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if (disableVm_) {
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pAddr = vAddr;
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pAddr = addr;
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} else {
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Word flagMask = sup ? 8 : 1;
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TLBEntry t = this->tlbLookup(vAddr, flagMask);
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pAddr = t.pfn * pageSize_ + vAddr % pageSize_;
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TLBEntry t = this->tlbLookup(addr, flagMask);
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pAddr = t.pfn * pageSize_ + addr % pageSize_;
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}
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return decoder_.read(pAddr, sup, addrBytes_);
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return decoder_.read(pAddr, data, size);
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}
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Word MemoryUnit::fetch(Addr vAddr, bool sup) {
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void MemoryUnit::write(Addr addr, const void *data, Size size, bool sup) {
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Addr pAddr;
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if (disableVm_) {
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pAddr = vAddr;
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} else {
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Word flagMask = sup ? 32 : 4;
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TLBEntry t = this->tlbLookup(vAddr, flagMask);
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pAddr = t.pfn * pageSize_ + vAddr % pageSize_;
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}
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Word instruction = decoder_.read(pAddr, sup, addrBytes_);
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return instruction;
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}
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void MemoryUnit::write(Addr vAddr, Word w, bool sup, Size bytes) {
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Addr pAddr;
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if (disableVm_) {
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pAddr = vAddr;
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pAddr = addr;
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} else {
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Word flagMask = sup ? 16 : 2;
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TLBEntry t = tlbLookup(vAddr, flagMask);
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pAddr = t.pfn * pageSize_ + vAddr % pageSize_;
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TLBEntry t = tlbLookup(addr, flagMask);
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pAddr = t.pfn * pageSize_ + addr % pageSize_;
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}
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decoder_.write(pAddr, w, sup, bytes);
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decoder_.write(pAddr, data, size);
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}
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void MemoryUnit::tlbAdd(Addr virt, Addr phys, Word flags) {
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@@ -182,70 +177,6 @@ void MemoryUnit::tlbRm(Addr va) {
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tlb_.erase(tlb_.find(va / pageSize_));
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}
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void *vortex::consoleInputThread(void * /*arg_vp*/) {
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//--
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return nullptr;
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}
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///////////////////////////////////////////////////////////////////////////////
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DiskControllerMemDevice::DiskControllerMemDevice(Size wordSize, Size blockSize, Core &c)
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: wordSize_(wordSize)
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, blockSize_(blockSize)
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, core_(c)
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{}
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Word DiskControllerMemDevice::read(Addr a) {
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switch (a / 8) {
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case 0:
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return curDisk_;
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case 1:
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return curBlock_;
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case 2:
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return disks_[curDisk_].blocks * blockSize_;
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case 3:
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return physAddr_;
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case 4:
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return command_;
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case 5:
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return status_;
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default:
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std::cout << "Attempt to read invalid disk controller register.\n";
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std::abort();
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}
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}
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void DiskControllerMemDevice::write(Addr a, Word w) {
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switch (a / 8) {
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case 0:
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if (w <= disks_.size()) {
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curDisk_ = w;
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status_ = OK;
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} else {
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status_ = INVALID_DISK;
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}
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break;
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case 1:
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if (w < disks_[curDisk_].blocks) {
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curBlock_ = w;
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} else {
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status_ = INVALID_BLOCK;
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}
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break;
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case 2:
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nBlocks_ = w >= disks_[curDisk_].blocks ? disks_[curDisk_].blocks - 1 : w;
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status_ = OK;
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break;
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case 3:
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physAddr_ = w;
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status_ = OK;
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break;
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case 4:
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std::cout << "TODO: Implement disk read and write!\n";
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break;
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}
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}
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///////////////////////////////////////////////////////////////////////////////
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RAM::RAM(uint32_t num_pages, uint32_t page_size)
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@@ -290,81 +221,20 @@ uint8_t *RAM::get(uint32_t address) {
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return page + byte_offset;
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}
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void RAM::read(uint32_t address, uint32_t length, uint8_t *data) {
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for (unsigned i = 0; i < length; i++) {
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data[i] = *this->get(address + i);
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void RAM::read(Addr addr, void *data, Size size) {
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Byte* d = (Byte*)data;
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for (unsigned i = 0; i < size; i++) {
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d[i] = *this->get(addr + i);
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}
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}
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void RAM::write(uint32_t address, uint32_t length, uint8_t *data) {
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for (unsigned i = 0; i < length; i++) {
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*this->get(address + i) = data[i];
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void RAM::write(Addr addr, const void *data, Size size) {
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const Byte* s = (const Byte*)data;
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for (unsigned i = 0; i < size; i++) {
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*this->get(addr + i) = s[i];
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}
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}
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Byte *RAM::base() {
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return (Byte *)this->get(0);
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}
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void RAM::getBlock(uint32_t address, uint8_t *data) {
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uint32_t block_number = address & 0xffffff00; // To zero out block offset
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uint32_t bytes_num = 256;
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this->read(block_number, bytes_num, data);
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}
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void RAM::getWord(uint32_t address, uint32_t *data) {
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data[0] = 0;
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uint8_t first = *get(address + 0);
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uint8_t second = *get(address + 1);
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uint8_t third = *get(address + 2);
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uint8_t fourth = *get(address + 3);
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data[0] = (data[0] << 0) | fourth;
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data[0] = (data[0] << 8) | third;
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data[0] = (data[0] << 8) | second;
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data[0] = (data[0] << 8) | first;
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}
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void RAM::writeWord(uint32_t address, uint32_t *data) {
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uint32_t data_to_write = *data;
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uint32_t byte_mask = 0xFF;
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for (int i = 0; i < 4; i++) {
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*this->get(address + i) = data_to_write & byte_mask;
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data_to_write = data_to_write >> 8;
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}
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}
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void RAM::writeHalf(uint32_t address, uint32_t *data) {
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uint32_t data_to_write = *data;
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uint32_t byte_mask = 0xFF;
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for (int i = 0; i < 2; i++) {
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*this->get(address + i) = data_to_write & byte_mask;
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data_to_write = data_to_write >> 8;
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}
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}
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void RAM::writeByte(uint32_t address, uint32_t *data) {
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uint32_t data_to_write = *data;
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uint32_t byte_mask = 0xFF;
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*this->get(address) = data_to_write & byte_mask;
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data_to_write = data_to_write >> 8;
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}
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void RAM::write(Addr addr, Word w) {
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uint32_t word = (uint32_t)w;
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writeWord(addr, &word);
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}
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Word RAM::read(Addr addr) {
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uint32_t w;
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getWord(addr, &w);
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return (Word)w;
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}
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static uint32_t hti_old(char c) {
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if (c >= 'A' && c <= 'F')
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return c - 'A' + 10;
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