simX floating-point fixes and refactoring
This commit is contained in:
Blaise Tine
505
simX/decode.cpp
505
simX/decode.cpp
@@ -11,47 +11,215 @@
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#include "decode.h"
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#include "archdef.h"
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#include "instr.h"
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#include "trace.h"
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using namespace vortex;
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struct InstTableEntry_t {
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const char *opString;
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bool controlFlow;
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InstType iType;
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};
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static const std::unordered_map<int, struct InstTableEntry_t> sc_instTable = {
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{Opcode::NOP, {"nop" , false, InstType::N_TYPE}},
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{Opcode::R_INST, {"r_type", false, InstType::R_TYPE}},
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{Opcode::L_INST, {"load" , false, InstType::I_TYPE}},
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{Opcode::I_INST, {"i_type", false, InstType::I_TYPE}},
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{Opcode::S_INST, {"store" , false, InstType::S_TYPE}},
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{Opcode::B_INST, {"branch", true , InstType::B_TYPE}},
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{Opcode::LUI_INST, {"lui" , false, InstType::U_TYPE}},
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{Opcode::AUIPC_INST, {"auipc" , false, InstType::U_TYPE}},
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{Opcode::JAL_INST, {"jal" , true , InstType::J_TYPE}},
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{Opcode::JALR_INST, {"jalr" , true , InstType::I_TYPE}},
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{Opcode::SYS_INST, {"SYS" , true , InstType::I_TYPE}},
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{Opcode::FENCE, {"fence" , true , InstType::I_TYPE}},
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{Opcode::PJ_INST, {"pred j", true , InstType::R_TYPE}},
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{Opcode::GPGPU, {"gpgpu" , false, InstType::R_TYPE}},
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{Opcode::VSET_ARITH, {"vsetvl", false, InstType::V_TYPE}},
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{Opcode::VL, {"vl" , false, InstType::V_TYPE}},
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{Opcode::VS, {"vs" , false, InstType::V_TYPE}},
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{Opcode::FL, {"fl" , false, InstType::I_TYPE }},
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{Opcode::FS, {"fs" , false, InstType::S_TYPE }},
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{Opcode::FCI, {"fci" , false, InstType::R_TYPE }},
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{Opcode::FMADD, {"fma" , false, InstType::R4_TYPE }},
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{Opcode::FMSUB, {"fms" , false, InstType::R4_TYPE }},
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{Opcode::FMNMADD, {"fmnma" , false, InstType::R4_TYPE }},
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{Opcode::FMNMSUB, {"fmnms" , false, InstType::R4_TYPE }}
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{Opcode::NOP, {false, InstType::N_TYPE}},
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{Opcode::R_INST, {false, InstType::R_TYPE}},
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{Opcode::L_INST, {false, InstType::I_TYPE}},
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{Opcode::I_INST, {false, InstType::I_TYPE}},
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{Opcode::S_INST, {false, InstType::S_TYPE}},
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{Opcode::B_INST, {true , InstType::B_TYPE}},
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{Opcode::LUI_INST, {false, InstType::U_TYPE}},
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{Opcode::AUIPC_INST, {false, InstType::U_TYPE}},
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{Opcode::JAL_INST, {true , InstType::J_TYPE}},
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{Opcode::JALR_INST, {true , InstType::I_TYPE}},
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{Opcode::SYS_INST, {true , InstType::I_TYPE}},
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{Opcode::FENCE, {true , InstType::I_TYPE}},
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{Opcode::FL, {false, InstType::I_TYPE}},
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{Opcode::FS, {false, InstType::S_TYPE}},
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{Opcode::FCI, {false, InstType::R_TYPE}},
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{Opcode::FMADD, {false, InstType::R4_TYPE}},
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{Opcode::FMSUB, {false, InstType::R4_TYPE}},
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{Opcode::FMNMADD, {false, InstType::R4_TYPE}},
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{Opcode::FMNMSUB, {false, InstType::R4_TYPE}},
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{Opcode::VSET, {false, InstType::V_TYPE}},
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{Opcode::GPGPU, {false, InstType::R_TYPE}},
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};
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std::ostream &vortex::operator<<(std::ostream &os, Instr &instr) {
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os << std::dec << sc_instTable.at(instr.opcode_).opString;
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static const char* op_string(const Instr &instr) {
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Word func3 = instr.getFunc3();
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Word func7 = instr.getFunc7();
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Word rs2 = instr.getRSrc(1);
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Word imm = instr.getImm();
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switch (instr.getOpcode()) {
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case Opcode::NOP: return "NOP";
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case Opcode::LUI_INST: return "LUI";
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case Opcode::AUIPC_INST: return "AUIPC";
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case Opcode::R_INST:
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if (func7 & 0x1) {
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switch (func3) {
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case 0: return "MUL";
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case 1: return "MULH";
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case 2: return "MULHSU";
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case 3: return "MULHU";
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case 4: return "DIV";
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case 5: return "DIVU";
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case 6: return "REM";
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case 7: return "REMU";
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}
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} else {
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switch (func3) {
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case 0: return func7 ? "SUB" : "ADD";
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case 1: return "SLL";
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case 2: return "SLT";
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case 3: return "SLTU";
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case 4: return "XOR";
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case 5: return func7 ? "SRA" : "SRL";
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case 6: return "OR";
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case 7: return "AND";
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}
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}
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case Opcode::I_INST:
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switch (func3) {
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case 0: return func7 ? "SUBI" : "ADDI";
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case 1: return "SLLI";
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case 2: return "SLTI";
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case 3: return "SLTIU";
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case 4: return "XORI";
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case 5: return func7 ? "SRAI" : "SRLI";
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case 6: return "ORI";
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case 7: return "ANDI";
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}
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case Opcode::B_INST:
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switch (func3) {
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case 0: return "BEQ";
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case 1: return "BNE";
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case 4: return "BLT";
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case 5: return "BGE";
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case 6: return "BLTU";
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case 7: return "BGEU";
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default:
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std::abort();
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}
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case Opcode::JAL_INST: return "JAL";
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case Opcode::JALR_INST: return "JALR";
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case Opcode::L_INST:
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switch (func3) {
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case 0: return "LBI";
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case 1: return "LHI";
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case 2: return "LW";
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case 4: return "LBU";
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case 5: return "LHU";
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default:
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std::abort();
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}
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case Opcode::S_INST:
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switch (func3) {
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case 0: return "SB";
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case 1: return "SH";
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case 2: return "SW";
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default:
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std::abort();
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}
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case Opcode::SYS_INST:
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switch (func3) {
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case 0: return imm ? "EBREAK" : "ECALL";
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case 1: return "CSRRW";
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case 2: return "CSRRS";
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case 3: return "CSRRC";
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case 5: return "CSRRWI";
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case 6: return "CSRRSI";
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case 7: return "CSRRCI";
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default:
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std::abort();
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}
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case Opcode::FENCE: return "FENCE";
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case Opcode::FL: return (func3 == 0x2) ? "FL" : "VL";
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case Opcode::FS: return (func3 == 0x2) ? "FS" : "VS";
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case Opcode::FCI:
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switch (func7) {
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case 0x00: return "FADD";
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case 0x04: return "FSUB";
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case 0x08: return "FMUL";
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case 0x0c: return "FDIV";
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case 0x2c: return "FSQRT";
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case 0x10:
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switch (func3) {
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case 0: return "FSGNJ";
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case 1: return "FSGNJN";
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case 2: return "FSGNJX";
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default:
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std::abort();
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}
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case 0x14:
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switch (func3) {
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case 0: return "FMIM";
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case 1: return "FMAX";
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default:
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std::abort();
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}
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case 0x50:
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switch (func3) {
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case 0: return "FLE";
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case 1: return "FLT";
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case 2: return "FEQ";
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default:
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std::abort();
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}
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case 0x60: return rs2 ? "FCVT.WU" : "FCVT.W";
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case 0x68: return rs2 ? "FCVT.S" : "FCVT.S";
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case 0x70: return func3 ? "FLASS" : "FMV.X.W";
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case 0x78: return "FMV.W";
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default:
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std::abort();
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}
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case Opcode::FMADD: return "FMADD";
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case Opcode::FMSUB: return "FMSUB";
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case Opcode::FMNMADD: return "FMNMADD";
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case Opcode::FMNMSUB: return "FMNMSUB";
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case Opcode::VSET: return "VSET";
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case Opcode::GPGPU:
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switch (func3) {
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case 0: return "TMC";
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case 1: return "WSPAWN";
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case 2: return "SPLIT";
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case 3: return "JOIN";
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case 4: return "BAR";
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default:
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std::abort();
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}
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default:
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std::abort();
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}
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}
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namespace vortex {
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std::ostream &operator<<(std::ostream &os, const Instr &instr) {
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os << op_string(instr) << ": ";
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int rdt = instr.getRDType();
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int rd = instr.getRDest();
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switch (rdt) {
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case 1: os << "r" << std::dec << rd << " <- "; break;
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case 2: os << "fr" << std::dec << rd << " <- "; break;
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case 3: os << "vr" << std::dec << rd << " <- "; break;
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default: break;
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}
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int i = 0;
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for (; i < instr.getNRSrc(); ++i) {
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int rst = instr.getRSType(i);
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int rs = instr.getRSrc(i);
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if (i) os << ", ";
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switch (rst) {
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case 1: os << "r" << std::dec << rs; break;
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case 2: os << "fr" << std::dec << rs; break;
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case 3: os << "vr" << std::dec << rs; break;
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default: break;
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}
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}
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if (instr.hasImm()) {
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if (i) os << ", ";
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os << "imm=0x" << std::hex << instr.getImm();
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}
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return os;
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}
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}
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Decoder::Decoder(const ArchDef &arch) {
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inst_s_ = arch.wsize() * 8;
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@@ -63,22 +231,16 @@ Decoder::Decoder(const ArchDef &arch) {
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vmask_s_ = 1;
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shift_opcode_ = 0;
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shift_rd_ = opcode_s_;
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shift_func3_ = opcode_s_ + reg_s_;
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shift_rs1_ = opcode_s_ + reg_s_ + func3_s_;
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shift_rs2_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_;
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shift_func7_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_ + reg_s_;
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shift_func2_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_ + reg_s_;
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shift_rs3_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_ + reg_s_ + func2_s_;
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shift_j_u_immed_ = opcode_s_ + reg_s_;
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shift_s_b_immed_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_ + reg_s_;
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shift_i_immed_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_;
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shift_vset_immed_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_;
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shift_vmask_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_ + reg_s_;
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shift_vmop_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_ + reg_s_ + vmask_s_;
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shift_vnf_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_ + reg_s_ + vmask_s_ + mop_s_;
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shift_func6_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_ + reg_s_ + 1;
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shift_vset_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_ + reg_s_ + 6;
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shift_rd_ = opcode_s_;
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shift_func3_ = shift_rd_ + reg_s_;
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shift_rs1_ = shift_func3_ + func3_s_;
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shift_rs2_ = shift_rs1_ + reg_s_;
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shift_func7_ = shift_rs2_ + reg_s_;
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shift_rs3_ = shift_func7_ + func2_s_;
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shift_vmop_ = shift_func7_ + vmask_s_;
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shift_vnf_ = shift_vmop_ + mop_s_;
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shift_func6_ = shift_func7_ + 1;
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shift_vset_ = shift_func7_ + 6;
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reg_mask_ = 0x1f;
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func2_mask_ = 0x2;
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@@ -94,223 +256,174 @@ Decoder::Decoder(const ArchDef &arch) {
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v_imm_mask_ = 0x7ff;
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}
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std::shared_ptr<Instr> Decoder::decode(
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const std::vector<Byte> &v,
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Size &idx,
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trace_inst_t *trace_inst)
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{
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Word code(readWord(v, idx, inst_s_ / 8));
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// std::cout << "code: " << (int) code << " v: " << v << " indx: " << idx << "\n";
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std::shared_ptr<Instr> Decoder::decode(Word code) {
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auto instr = std::make_shared<Instr>();
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Opcode op = (Opcode)((code >> shift_opcode_) & opcode_mask_);
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// std::cout << "opcode: " << op << "\n";
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instr->setOpcode(op);
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Word imeed, dest_bits, imm_bits, bit_11, bits_4_1, bit_10_5,
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bit_12, bits_19_12, bits_10_1, bit_20, unordered, func3;
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Word func3 = (code >> shift_func3_) & func3_mask_;
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Word func6 = (code >> shift_func6_) & func6_mask_;
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Word func7 = (code >> shift_func7_) & func7_mask_;
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InstType curInstType = sc_instTable.at(op).iType;
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int rd = (code >> shift_rd_) & reg_mask_;
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int rs1 = (code >> shift_rs1_) & reg_mask_;
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int rs2 = (code >> shift_rs2_) & reg_mask_;
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int rs3 = (code >> shift_rs3_) & reg_mask_;
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auto iType = sc_instTable.at(op).iType;
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if (op == Opcode::FL || op == Opcode::FS) {
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// need to find out whether it is vector or floating point inst
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Word width_bits = (code >> shift_func3_) & func3_mask_;
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if ((width_bits == 0x1) || (width_bits == 0x2)
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|| (width_bits == 0x3) || (width_bits == 0x4)) {
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curInstType = (op == Opcode::FL) ? InstType::I_TYPE : InstType::S_TYPE;
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if (func3 != 0x2) {
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iType = InstType::V_TYPE;
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}
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}
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switch (curInstType) {
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switch (iType) {
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case InstType::N_TYPE:
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break;
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case InstType::R_TYPE:
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if (op == Opcode::FCI) {
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instr->setDestFReg((code >> shift_rd_) & reg_mask_);
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instr->setSrcFReg((code >> shift_rs1_) & reg_mask_);
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instr->setSrcFReg((code >> shift_rs2_) & reg_mask_);
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if (op == Opcode::FCI) {
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instr->setSrcFReg(rs1);
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instr->setSrcFReg(rs2);
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switch (func7) {
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case 0x50: // FLE, FLT, FEQ
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case 0x60: // FCVT.WU, FCVT.W
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case 0x70: // FLASS, FMV.X.W
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instr->setDestReg(rd);
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break;
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default:
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instr->setDestFReg(rd);
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}
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} else {
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instr->setDestReg((code >> shift_rd_) & reg_mask_);
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instr->setSrcReg((code >> shift_rs1_) & reg_mask_);
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instr->setSrcReg((code >> shift_rs2_) & reg_mask_);
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instr->setDestReg(rd);
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instr->setSrcReg(rs1);
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instr->setSrcReg(rs2);
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}
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instr->setFunc3((code >> shift_func3_) & func3_mask_);
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instr->setFunc7((code >> shift_func7_) & func7_mask_);
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break;
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case InstType::I_TYPE:
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if (op == Opcode::FCI || op == Opcode::FL) {
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instr->setDestFReg((code >> shift_rd_) & reg_mask_);
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instr->setSrcFReg((code >> shift_rs1_) & reg_mask_);
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} else {
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instr->setDestReg((code >> shift_rd_) & reg_mask_);
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instr->setSrcReg((code >> shift_rs1_) & reg_mask_);
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}
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instr->setFunc7((code >> shift_func7_) & func7_mask_);
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func3 = (code >> shift_func3_) & func3_mask_;
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instr->setFunc3(func3);
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instr->setFunc7(func7);
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break;
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case InstType::I_TYPE: {
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if (op == Opcode::FCI || op == Opcode::FL) {
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instr->setDestFReg(rd);
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instr->setSrcFReg(rs1);
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} else {
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instr->setDestReg(rd);
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instr->setSrcReg(rs1);
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}
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instr->setFunc3(func3);
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instr->setFunc7(func7);
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if ((func3 == 5) && (op != L_INST) && (op != Opcode::FL)) {
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instr->setSrcImm(signExt(((code >> shift_rs2_) & reg_mask_), 5, reg_mask_));
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instr->setImm(signExt(rs2, 5, reg_mask_));
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} else {
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instr->setSrcImm(signExt(code >> shift_i_immed_, 12, i_imm_mask_));
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instr->setImm(signExt(code >> shift_rs2_, 12, i_imm_mask_));
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}
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break;
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} break;
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case InstType::S_TYPE:
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case InstType::S_TYPE: {
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if (op == Opcode::FS) {
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instr->setSrcFReg((code >> shift_rs1_) & reg_mask_);
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instr->setSrcFReg((code >> shift_rs2_) & reg_mask_);
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instr->setSrcFReg(rs1);
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instr->setSrcFReg(rs2);
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} else {
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instr->setSrcReg((code >> shift_rs1_) & reg_mask_);
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instr->setSrcReg((code >> shift_rs2_) & reg_mask_);
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instr->setSrcReg(rs1);
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instr->setSrcReg(rs2);
|
||||
}
|
||||
instr->setFunc3((code >> shift_func3_) & func3_mask_);
|
||||
dest_bits = (code >> shift_rd_) & reg_mask_;
|
||||
imm_bits = (code >> shift_s_b_immed_ & func7_mask_);
|
||||
imeed = (imm_bits << reg_s_) | dest_bits;
|
||||
instr->setSrcImm(signExt(imeed, 12, s_imm_mask_));
|
||||
break;
|
||||
instr->setFunc3(func3);
|
||||
Word imeed = (func7 << reg_s_) | rd;
|
||||
instr->setImm(signExt(imeed, 12, s_imm_mask_));
|
||||
} break;
|
||||
|
||||
case InstType::B_TYPE:
|
||||
instr->setSrcReg((code >> shift_rs1_) & reg_mask_);
|
||||
instr->setSrcReg((code >> shift_rs2_) & reg_mask_);
|
||||
instr->setFunc3((code >> shift_func3_) & func3_mask_);
|
||||
|
||||
dest_bits = (code >> shift_rd_) & reg_mask_;
|
||||
imm_bits = (code >> shift_s_b_immed_ & func7_mask_);
|
||||
|
||||
bit_11 = dest_bits & 0x1;
|
||||
bits_4_1 = dest_bits >> 1;
|
||||
bit_10_5 = imm_bits & 0x3f;
|
||||
bit_12 = imm_bits >> 6;
|
||||
|
||||
imeed = 0 | (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
|
||||
instr->setSrcImm(signExt(imeed, 13, b_imm_mask_));
|
||||
break;
|
||||
case InstType::B_TYPE: {
|
||||
instr->setSrcReg(rs1);
|
||||
instr->setSrcReg(rs2);
|
||||
instr->setFunc3(func3);
|
||||
Word bit_11 = rd & 0x1;
|
||||
Word bits_4_1 = rd >> 1;
|
||||
Word bit_10_5 = func7 & 0x3f;
|
||||
Word bit_12 = func7 >> 6;
|
||||
Word imeed = (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
|
||||
instr->setImm(signExt(imeed, 13, b_imm_mask_));
|
||||
} break;
|
||||
|
||||
case InstType::U_TYPE:
|
||||
instr->setDestReg((code >> shift_rd_) & reg_mask_);
|
||||
instr->setSrcImm(signExt(code >> shift_j_u_immed_, 20, u_imm_mask_));
|
||||
instr->setDestReg(rd);
|
||||
instr->setImm(signExt(code >> shift_func3_, 20, u_imm_mask_));
|
||||
break;
|
||||
|
||||
case InstType::J_TYPE:
|
||||
instr->setDestReg((code >> shift_rd_) & reg_mask_);
|
||||
unordered = code >> shift_j_u_immed_;
|
||||
bits_19_12 = unordered & 0xff;
|
||||
bit_11 = (unordered >> 8) & 0x1;
|
||||
bits_10_1 = (unordered >> 9) & 0x3ff;
|
||||
bit_20 = (unordered >> 19) & 0x1;
|
||||
imeed = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
|
||||
case InstType::J_TYPE: {
|
||||
instr->setDestReg(rd);
|
||||
Word unordered = code >> shift_func3_;
|
||||
Word bits_19_12 = unordered & 0xff;
|
||||
Word bit_11 = (unordered >> 8) & 0x1;
|
||||
Word bits_10_1 = (unordered >> 9) & 0x3ff;
|
||||
Word bit_20 = (unordered >> 19) & 0x1;
|
||||
Word imeed = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
|
||||
if (bit_20) {
|
||||
imeed |= ~j_imm_mask_;
|
||||
}
|
||||
instr->setSrcImm(imeed);
|
||||
break;
|
||||
instr->setImm(imeed);
|
||||
} break;
|
||||
|
||||
case InstType::V_TYPE:
|
||||
D(3, "Entered here: instr type = vector" << op);
|
||||
switch (op) {
|
||||
case Opcode::VSET_ARITH: //TODO: arithmetic ops
|
||||
instr->setDestVReg((code >> shift_rd_) & reg_mask_);
|
||||
instr->setSrcVReg((code >> shift_rs1_) & reg_mask_);
|
||||
func3 = (code >> shift_func3_) & func3_mask_;
|
||||
case Opcode::VSET: {
|
||||
instr->setDestVReg(rd);
|
||||
instr->setSrcVReg(rs1);
|
||||
instr->setFunc3(func3);
|
||||
D(3, "Entered here: instr type = vector");
|
||||
|
||||
if (func3 == 7) {
|
||||
D(3, "Entered here: imm instr");
|
||||
instr->setVsetImm(!(code >> shift_vset_));
|
||||
if (instr->getVsetImm()) {
|
||||
instr->setImm(!(code >> shift_vset_));
|
||||
if (instr->getImm()) {
|
||||
Word immed = (code >> shift_rs2_) & v_imm_mask_;
|
||||
D(3, "immed" << immed);
|
||||
instr->setSrcImm(immed); //TODO
|
||||
instr->setImm(immed);
|
||||
instr->setVlmul(immed & 0x3);
|
||||
D(3, "lmul " << (immed & 0x3));
|
||||
instr->setVediv((immed >> 4) & 0x3);
|
||||
D(3, "ediv " << ((immed >> 4) & 0x3));
|
||||
instr->setVsew((immed >> 2) & 0x3);
|
||||
D(3, "sew " << ((immed >> 2) & 0x3));
|
||||
} else {
|
||||
instr->setSrcVReg((code >> shift_rs2_) & reg_mask_);
|
||||
instr->setSrcVReg(rs2);
|
||||
}
|
||||
} else {
|
||||
instr->setSrcVReg((code >> shift_rs2_) & reg_mask_);
|
||||
instr->setVmask((code >> shift_vmask_) & 0x1);
|
||||
instr->setFunc6((code >> shift_func6_) & func6_mask_);
|
||||
instr->setSrcVReg(rs2);
|
||||
instr->setVmask((code >> shift_func7_) & 0x1);
|
||||
instr->setFunc6(func6);
|
||||
}
|
||||
break;
|
||||
} break;
|
||||
|
||||
case Opcode::VL:
|
||||
D(3, "vector load instr");
|
||||
instr->setDestVReg((code >> shift_rd_) & reg_mask_);
|
||||
instr->setSrcVReg((code >> shift_rs1_) & reg_mask_);
|
||||
instr->setVlsWidth((code >> shift_func3_) & func3_mask_);
|
||||
instr->setSrcVReg((code >> shift_rs2_) & reg_mask_);
|
||||
instr->setVmask((code >> shift_vmask_));
|
||||
instr->setDestVReg(rd);
|
||||
instr->setSrcVReg(rs1);
|
||||
instr->setVlsWidth(func3);
|
||||
instr->setSrcVReg(rs2);
|
||||
instr->setVmask(code >> shift_func7_);
|
||||
instr->setVmop((code >> shift_vmop_) & func3_mask_);
|
||||
instr->setVnf((code >> shift_vnf_) & func3_mask_);
|
||||
break;
|
||||
|
||||
case Opcode::VS:
|
||||
instr->setVs3((code >> shift_rd_) & reg_mask_);
|
||||
instr->setSrcVReg((code >> shift_rs1_) & reg_mask_);
|
||||
instr->setVlsWidth((code >> shift_func3_) & func3_mask_);
|
||||
instr->setSrcVReg((code >> shift_rs2_) & reg_mask_);
|
||||
instr->setVmask((code >> shift_vmask_));
|
||||
instr->setVs3(rd);
|
||||
instr->setSrcVReg(rs1);
|
||||
instr->setVlsWidth(func3);
|
||||
instr->setSrcVReg(rs2);
|
||||
instr->setVmask(code >> shift_func7_);
|
||||
instr->setVmop((code >> shift_vmop_) & func3_mask_);
|
||||
instr->setVnf((code >> shift_vnf_) & func3_mask_);
|
||||
break;
|
||||
|
||||
default:
|
||||
std::cout << "Inavlid opcode.\n";
|
||||
std::abort();
|
||||
}
|
||||
break;
|
||||
case R4_TYPE:
|
||||
// RT: add R4_TYPE decoder
|
||||
instr->setDestFReg((code >> shift_rd_) & reg_mask_);
|
||||
instr->setSrcFReg((code >> shift_rs1_) & reg_mask_);
|
||||
instr->setSrcFReg((code >> shift_rs2_) & reg_mask_);
|
||||
instr->setSrcFReg((code >> shift_rs3_) & reg_mask_);
|
||||
instr->setFunc3((code >> shift_func3_) & func3_mask_);
|
||||
instr->setDestFReg(rd);
|
||||
instr->setSrcFReg(rs1);
|
||||
instr->setSrcFReg(rs2);
|
||||
instr->setSrcFReg(rs3);
|
||||
instr->setFunc3(func3);
|
||||
break;
|
||||
default:
|
||||
std::cout << "Unrecognized argument class in word decoder.\n";
|
||||
std::abort();
|
||||
}
|
||||
|
||||
if (curInstType != InstType::N_TYPE) {
|
||||
trace_inst->valid = true;
|
||||
if (instr->hasRDest()) {
|
||||
if (instr->is_FpDest()) {
|
||||
trace_inst->frd = instr->getRDest();
|
||||
} else if (instr->is_VDest()) {
|
||||
trace_inst->vrd = instr->getRDest();
|
||||
} else {
|
||||
trace_inst->ird = instr->getRDest();
|
||||
}
|
||||
}
|
||||
|
||||
for (int i = 0; i < instr->getNRSrc(); ++i) {
|
||||
if (instr->is_FpSrc(i)) {
|
||||
if (i == 0) trace_inst->frs1 = instr->getRSrc(i);
|
||||
else if (i == 1) trace_inst->frs2 = instr->getRSrc(i);
|
||||
else if (i == 2) trace_inst->frs3 = instr->getRSrc(i);
|
||||
else std::abort();
|
||||
} else if (instr->is_VSrc(i)) {
|
||||
if (i == 0) trace_inst->vrs1 = instr->getRSrc(i);
|
||||
else if (i == 1) trace_inst->vrs2 = instr->getRSrc(i);
|
||||
else std::abort();
|
||||
} else {
|
||||
if (i == 0) trace_inst->irs1 = instr->getRSrc(i);
|
||||
else if (i == 1) trace_inst->irs2 = instr->getRSrc(i);
|
||||
else std::abort();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
D(2, "Decoded instr 0x" << std::hex << code << " into: " << *instr << std::flush);
|
||||
D(2, "Instr 0x" << std::hex << code << ": " << *instr << std::flush);
|
||||
|
||||
return instr;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user