diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 32513d94..2047ac7c 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -125,9 +125,9 @@ module VX_bank #( .clk (clk), .reset (reset), .push (snp_req_valid), - .data_i (snp_req_addr), + .data_in (snp_req_addr), .pop (snrq_pop), - .data_o (snrq_addr_st0), + .data_out(snrq_addr_st0), .empty (snrq_empty), .full (snp_req_full) ); @@ -147,9 +147,9 @@ module VX_bank #( .clk (clk), .reset (reset), .push (dram_fill_rsp_valid), - .data_i ({dram_fill_rsp_addr, dram_fill_rsp_data}), + .data_in ({dram_fill_rsp_addr, dram_fill_rsp_data}), .pop (dfpq_pop), - .data_o({dfpq_addr_st0, dfpq_filldata_st0}), + .data_out({dfpq_addr_st0, dfpq_filldata_st0}), .empty (dfpq_empty), .full (dfpq_full) ); @@ -538,10 +538,10 @@ module VX_bank #( .reset (reset), .push (cwbq_push), - .data_i ({cwbq_tid, cwbq_rd, cwbq_wb, cwbq_warp_num, cwbq_data, cwbq_pc, addr_st2}), + .data_in ({cwbq_tid, cwbq_rd, cwbq_wb, cwbq_warp_num, cwbq_data, cwbq_pc, addr_st2}), .pop (core_rsp_pop), - .data_o({core_rsp_tid, core_rsp_rd, core_rsp_wb, core_rsp_warp_num, core_rsp_data, core_rsp_pc, core_rsp_addr}), + .data_out({core_rsp_tid, core_rsp_rd, core_rsp_wb, core_rsp_warp_num, core_rsp_data, core_rsp_pc, core_rsp_addr}), .empty (cwbq_empty), .full (cwbq_full) ); @@ -606,10 +606,10 @@ module VX_bank #( .reset (reset), .push (dwbq_push), - .data_i ({dwbq_req_addr, dwbq_req_data}), + .data_in ({dwbq_req_addr, dwbq_req_data}), .pop (dram_wb_req_pop), - .data_o({dram_wb_req_addr, dram_wb_req_data}), + .data_out({dram_wb_req_addr, dram_wb_req_data}), .empty (dwbq_empty), .full (dwbq_full) ); @@ -627,9 +627,9 @@ module VX_bank #( .clk (clk), .reset (reset), .push (snp_fwd_push), - .data_i ({addr_st2}), + .data_in ({addr_st2}), .pop (snp_fwd_pop), - .data_o({snp_fwd_addr}), + .data_out({snp_fwd_addr}), .empty (ffsq_empty), .full (ffsq_full) ); diff --git a/hw/rtl/cache/VX_cache_dfq_queue.v b/hw/rtl/cache/VX_cache_dfq_queue.v index 767ab570..b8bb2002 100644 --- a/hw/rtl/cache/VX_cache_dfq_queue.v +++ b/hw/rtl/cache/VX_cache_dfq_queue.v @@ -79,9 +79,9 @@ module VX_cache_dfq_queue #( .clk (clk), .reset (reset), .push (push_qual), - .data_i ({per_bank_dram_fill_req_valid, per_bank_dram_fill_req_addr}), + .data_in ({per_bank_dram_fill_req_valid, per_bank_dram_fill_req_addr}), .pop (pop_qual), - .data_o({out_per_bank_dram_fill_req, out_per_bank_dram_fill_req_addr}), + .data_out({out_per_bank_dram_fill_req, out_per_bank_dram_fill_req_addr}), .empty (o_empty), .full (dfqq_full) ); diff --git a/hw/rtl/cache/VX_cache_req_queue.v b/hw/rtl/cache/VX_cache_req_queue.v index 7aa90497..c78b200f 100644 --- a/hw/rtl/cache/VX_cache_req_queue.v +++ b/hw/rtl/cache/VX_cache_req_queue.v @@ -122,9 +122,9 @@ module VX_cache_req_queue #( .clk (clk), .reset (reset), .push (push_qual), - .data_i ({bank_valids , bank_addr , bank_writedata , bank_rd , bank_wb , bank_warp_num , bank_mem_read , bank_mem_write , bank_pc}), + .data_in ({bank_valids , bank_addr , bank_writedata , bank_rd , bank_wb , bank_warp_num , bank_mem_read , bank_mem_write , bank_pc}), .pop (pop_qual), - .data_o ({out_per_valids, out_per_addr, out_per_writedata, out_per_rd, out_per_wb, out_per_warp_num, out_per_mem_read, out_per_mem_write, out_per_pc}), + .data_out ({out_per_valids, out_per_addr, out_per_writedata, out_per_rd, out_per_wb, out_per_warp_num, out_per_mem_read, out_per_mem_write, out_per_pc}), .empty (o_empty), .full (reqq_full) ); diff --git a/hw/rtl/cache/VX_prefetcher.v b/hw/rtl/cache/VX_prefetcher.v index 9e599eae..db63feeb 100644 --- a/hw/rtl/cache/VX_prefetcher.v +++ b/hw/rtl/cache/VX_prefetcher.v @@ -40,10 +40,10 @@ module VX_prefetcher #( .reset (reset), .push (dram_req && !current_full && !pref_pop), - .data_i (dram_req_addr & `BASE_ADDR_MASK), + .data_in (dram_req_addr & `BASE_ADDR_MASK), .pop (update_use), - .data_o(current_addr), + .data_out(current_addr), .empty (current_empty), .full (current_full) diff --git a/hw/rtl/libs/VX_generic_queue.v b/hw/rtl/libs/VX_generic_queue.v index 02f44ff4..f8391c3d 100644 --- a/hw/rtl/libs/VX_generic_queue.v +++ b/hw/rtl/libs/VX_generic_queue.v @@ -10,13 +10,13 @@ module VX_generic_queue #( output wire empty, output wire full, `IGNORE_WARNINGS_END - input wire [DATAW-1:0] data_i, - output wire [DATAW-1:0] data_o + input wire [DATAW-1:0] data_in, + output wire [DATAW-1:0] data_out ); if (SIZE == 0) begin assign empty = 1; - assign data_o = data_i; + assign data_out = data_in; assign full = 0; end else begin // (SIZE > 0) @@ -49,12 +49,12 @@ module VX_generic_queue #( end if (writing) begin - head_r <= data_i; + head_r <= data_in; end end end - assign data_o = head_r; + assign data_out = head_r; assign empty = (size_r == 0); assign full = (size_r != 0) && !pop; @@ -99,7 +99,7 @@ module VX_generic_queue #( always @(posedge clk) begin if (writing) begin - data[wr_ctr_r] <= data_i; + data[wr_ctr_r] <= data_in; end end @@ -121,12 +121,12 @@ module VX_generic_queue #( end bypass_r <= writing && (empty_r || (1 == size_r) && reading); - curr_r <= data_i; + curr_r <= data_in; head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r]; end end - assign data_o = bypass_r ? curr_r : head_r; + assign data_out = bypass_r ? curr_r : head_r; assign empty = empty_r; assign full = full_r; end diff --git a/hw/rtl/libs/VX_generic_stack.v b/hw/rtl/libs/VX_generic_stack.v index 1ecf6409..fca12d1d 100644 --- a/hw/rtl/libs/VX_generic_stack.v +++ b/hw/rtl/libs/VX_generic_stack.v @@ -1,10 +1,8 @@ -module VX_generic_stack - #( - parameter WIDTH = 40, - parameter DEPTH = 2 - ) - ( +module VX_generic_stack #( + parameter WIDTH = 40, + parameter DEPTH = 2 +) ( input wire clk, input wire reset, input wire push, @@ -12,8 +10,7 @@ module VX_generic_stack input reg [WIDTH - 1:0] q1, input reg [WIDTH - 1:0] q2, output wire[WIDTH - 1:0] d - ); - +); reg [DEPTH - 1:0] ptr; reg [WIDTH - 1:0] stack [0:(1 << DEPTH) - 1]; @@ -30,10 +27,8 @@ module VX_generic_stack end else if (pop) begin ptr <= ptr - 1; end - end - assign d = stack[ptr - 1]; endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_priority_encoder.v b/hw/rtl/libs/VX_priority_encoder.v index 753814a8..b6e04433 100644 --- a/hw/rtl/libs/VX_priority_encoder.v +++ b/hw/rtl/libs/VX_priority_encoder.v @@ -2,9 +2,9 @@ module VX_priority_encoder ( input wire[`NUM_WARPS-1:0] valids, - output reg[`NW_BITS-1:0] index, - output reg found - ); + output reg[`NW_BITS-1:0] index, + output reg found +); integer i; always @(*) begin diff --git a/hw/rtl/libs/VX_priority_encoder_w_mask.v b/hw/rtl/libs/VX_priority_encoder_w_mask.v index ee60d11a..d6a2405c 100644 --- a/hw/rtl/libs/VX_priority_encoder_w_mask.v +++ b/hw/rtl/libs/VX_priority_encoder_w_mask.v @@ -1,16 +1,14 @@ `include "VX_define.vh" -module VX_priority_encoder_w_mask - #( - parameter N = 10 - ) - ( - input wire[N-1:0] valids, - output reg [N-1:0] mask, +module VX_priority_encoder_w_mask #( + parameter N = 10 +) ( + input wire[N-1:0] valids, + output reg [N-1:0] mask, //output reg[$clog2(N)-1:0] index, - output reg[(`LOG2UP(N))-1:0] index, + output reg[(`LOG2UP(N))-1:0] index, //output reg[`LOG2UP(N):0] index, // eh - output reg found - ); + output reg found +); integer i; always @(valids) begin diff --git a/hw/rtl/pipe_regs/VX_f_d_reg.v b/hw/rtl/pipe_regs/VX_f_d_reg.v index d130f71e..1b8d8170 100644 --- a/hw/rtl/pipe_regs/VX_f_d_reg.v +++ b/hw/rtl/pipe_regs/VX_f_d_reg.v @@ -1,19 +1,21 @@ `include "../VX_define.vh" module VX_f_d_reg ( - input wire clk, - input wire reset, - input wire freeze_i, + input wire clk, + input wire reset, + input wire freeze_i, - VX_inst_meta_if fe_inst_meta_fd, - VX_inst_meta_if fd_inst_meta_de + VX_inst_meta_if fe_inst_meta_fd, + VX_inst_meta_if fd_inst_meta_de ); wire flush = 1'b0; wire stall = freeze_i == 1'b1; - VX_generic_register #( .N(64+`NW_BITS-1+1+`NUM_THREADS) ) f_d_reg ( + VX_generic_register #( + .N(64+`NW_BITS-1+1+`NUM_THREADS) + ) f_d_reg ( .clk (clk), .reset(reset), .stall(stall), diff --git a/hw/rtl/pipe_regs/VX_i_d_reg.v b/hw/rtl/pipe_regs/VX_i_d_reg.v index e7da02eb..e0cfb2b6 100644 --- a/hw/rtl/pipe_regs/VX_i_d_reg.v +++ b/hw/rtl/pipe_regs/VX_i_d_reg.v @@ -14,7 +14,9 @@ module VX_i_d_reg ( wire stall = freeze_i == 1'b1; - VX_generic_register #( .N( 64 + `NW_BITS-1 + 1 + `NUM_THREADS ) ) i_d_reg ( + VX_generic_register #( + .N(64 + `NW_BITS-1 + 1 + `NUM_THREADS) + ) i_d_reg ( .clk (clk), .reset(reset), .stall(stall), diff --git a/hw/rtl/shared_memory/VX_bank_valids.v b/hw/rtl/shared_memory/VX_bank_valids.v deleted file mode 100644 index af5a9f24..00000000 --- a/hw/rtl/shared_memory/VX_bank_valids.v +++ /dev/null @@ -1,36 +0,0 @@ -`include "../VX_define.vh" - -// Converts in_valids to bank_valids -module VX_bank_valids - #( - parameter NB = 4, - parameter BITS_PER_BANK = 3 - ) - ( - input wire[`NUM_THREADS-1:0] in_valids, - input wire[`NUM_THREADS-1:0][31:0] in_addr, - output reg[NB:0][`NUM_THREADS-1:0] bank_valids - ); - - - integer i, j; - always@(*) begin - for(j = 0; j <= NB; j = j+1 ) begin - for(i = 0; i < `NUM_THREADS; i = i+1) begin - if(in_valids[i]) begin - if(in_addr[i][(2+BITS_PER_BANK-1):2] == j[BITS_PER_BANK-1:0]) begin - bank_valids[j][i] = 1'b1; - end - else begin - bank_valids[j][i] = 1'b0; - end - - end - else begin - bank_valids[j][i] = 1'b0; - end - end - end - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/shared_memory/VX_priority_encoder_sm.v b/hw/rtl/shared_memory/VX_priority_encoder_sm.v deleted file mode 100644 index 75720aaa..00000000 --- a/hw/rtl/shared_memory/VX_priority_encoder_sm.v +++ /dev/null @@ -1,116 +0,0 @@ -`include "../VX_define.vh" - -module VX_priority_encoder_sm - #( - parameter NB = 4, - parameter BITS_PER_BANK = 3, - parameter NUM_REQ = 3 - ) - ( - //INPUTS - input wire clk, - input wire reset, - input wire[`NUM_THREADS-1:0] in_valid, - input wire[`NUM_THREADS-1:0][31:0] in_address, - input wire[`NUM_THREADS-1:0][31:0] in_data, - // OUTPUTS - // To SM Module - output reg[NB:0] out_valid, - output reg[NB:0][31:0] out_address, - output reg[NB:0][31:0] out_data, - - // To Processor - output wire[NB:0][`LOG2UP(NUM_REQ) - 1:0] req_num, - output reg stall, - output wire send_data // Finished all of the requests -); - - reg[`NUM_THREADS-1:0] left_requests; - reg[`NUM_THREADS-1:0] serviced; - - wire[`NUM_THREADS-1:0] use_valid; - - wire requests_left = (|left_requests); - - assign use_valid = (requests_left) ? left_requests : in_valid; - - wire[NB:0][`NUM_THREADS-1:0] bank_valids; - - VX_bank_valids #( - .NB(NB), - .BITS_PER_BANK(BITS_PER_BANK) - ) bank_valid ( - .valids_i(use_valid), - .addr_i(in_address), - .bank_valids(bank_valids) - ); - - wire[NB:0] more_than_one_valid; - - genvar curr_bank; - generate - for (curr_bank = 0; curr_bank <= NB; curr_bank = curr_bank + 1) begin : countones_blocks - wire[`LOG2UP(`NUM_THREADS):0] num_valids; - - VX_countones #(.N(`NUM_THREADS)) valids_counter ( - .valids(bank_valids[curr_bank]), - .count (num_valids) - ); - assign more_than_one_valid[curr_bank] = num_valids > 1; - // assign more_than_one_valid[curr_bank] = $countones(bank_valids[curr_bank]) > 1; - end - endgenerate - - - assign stall = (|more_than_one_valid); - assign send_data = (!stall) && (|in_valid); // change - - wire[NB:0][(`LOG2UP(NUM_REQ)) - 1:0] internal_req_num; - wire[NB:0] internal_out_valid; - - - // There's one or less valid per bank - genvar curr_bank_o; - generate - for (curr_bank_o = 0; curr_bank_o <= NB; curr_bank_o = curr_bank_o + 1) begin : encoders - - VX_generic_priority_encoder #( - .N(NUM_REQ) - ) priority_encoder ( - .valids(bank_valids[curr_bank_o]), - .index(internal_req_num[curr_bank_o]), - .found(internal_out_valid[curr_bank_o]) - ); - assign out_address[curr_bank_o] = internal_out_valid[curr_bank_o] ? in_address[internal_req_num[curr_bank_o]] : 0; - assign out_data[curr_bank_o] = internal_out_valid[curr_bank_o] ? in_data[internal_req_num[curr_bank_o]] : 0; - end - endgenerate - - integer curr_b; - always @(*) begin - serviced = 0; - for (curr_b = 0; curr_b <= NB; curr_b=curr_b+1) begin - serviced[internal_req_num[curr_b]] = 1; - end - end - - assign req_num = internal_req_num; - assign out_valid = internal_out_valid; - - wire[`NUM_THREADS-1:0] serviced_qual = in_valid & (serviced); - - wire[`NUM_THREADS-1:0] new_left_requests = (left_requests == 0) ? (in_valid & ~serviced_qual) : (left_requests & ~ serviced_qual); - - // wire[`NUM_THREADS-1:0] new_left_requests = left_requests & ~(serviced_qual); - - always @(posedge clk) begin - if (reset) begin - left_requests <= 0; - // serviced = 0; - end else begin - if (!stall) left_requests <= 0; - else left_requests <= new_left_requests; - end - end - -endmodule \ No newline at end of file diff --git a/hw/rtl/shared_memory/VX_shared_memory.v b/hw/rtl/shared_memory/VX_shared_memory.v deleted file mode 100644 index 3e8cec75..00000000 --- a/hw/rtl/shared_memory/VX_shared_memory.v +++ /dev/null @@ -1,171 +0,0 @@ -`include "../VX_define.vh" - -module VX_shared_memory #( - parameter SM_SIZE = 4096, // Bytes - parameter SM_BANKS = 4, - parameter SM_BYTES_PER_READ = 16, - parameter SM_WORDS_PER_READ = 4, - parameter SM_LOG_WORDS_PER_READ = 2, - parameter SM_HEIGHT = 128, // Bytes - parameter SM_BANK_OFFSET_START = 2, - parameter SM_BANK_OFFSET_END = 4, - parameter SM_BLOCK_OFFSET_START = 5, - parameter SM_BLOCK_OFFSET_END = 6, - parameter SM_INDEX_START = 7, - parameter SM_INDEX_END = 13, - parameter NUM_REQ = 4, - parameter BITS_PER_BANK = 3 -) ( - //INPUTS - input wire clk, - input wire reset, - input wire[`NUM_THREADS-1:0] in_valid, - input wire[`NUM_THREADS-1:0][31:0] in_address, - input wire[`NUM_THREADS-1:0][31:0] in_data, - input wire[2:0] mem_read, - input wire[2:0] mem_write, - //OUTPUTS - output wire[`NUM_THREADS-1:0] out_valid, - output wire[`NUM_THREADS-1:0][31:0] out_data, - output wire stall -); - - //reg [NB:0][31:0] temp_address; - //reg [NB:0][31:0] temp_in_data; - //reg [NB:0] temp_in_valid; - reg [SM_BANKS - 1:0][31:0] temp_address; - reg [SM_BANKS - 1:0][31:0] temp_in_data; - reg [SM_BANKS - 1:0] temp_in_valid; - - reg [`NUM_THREADS-1:0] temp_out_valid; - reg [`NUM_THREADS-1:0][31:0] temp_out_data; - - //reg [NB:0][6:0] block_addr; - //reg [NB:0][3:0][31:0] block_wdata; - //reg [NB:0][3:0][31:0] block_rdata; - //reg [NB:0][1:0] block_we; - reg [SM_BANKS - 1:0][$clog2(SM_HEIGHT) - 1:0] block_addr; - reg [SM_BANKS - 1:0][SM_WORDS_PER_READ-1:0][31:0] block_wdata; - reg [SM_BANKS - 1:0][SM_WORDS_PER_READ-1:0][31:0] block_rdata; - reg [SM_BANKS - 1:0][SM_LOG_WORDS_PER_READ-1:0] block_we; - - wire send_data; - - //reg [NB:0][1:0] req_num; - reg [SM_BANKS - 1:0][`LOG2UP(NUM_REQ) - 1:0] req_num; // not positive about this - - wire [`NUM_THREADS-1:0] orig_in_valid; - - genvar f; - generate - for(f = 0; f < `NUM_THREADS; f = f+1) begin : orig_in_valid_setup - assign orig_in_valid[f] = in_valid[f]; - end - - assign out_valid = send_data ? temp_out_valid : 0; - assign out_data = send_data ? temp_out_data : 0; - endgenerate - - VX_priority_encoder_sm #( - .NB(SM_BANKS - 1), - .BITS_PER_BANK(BITS_PER_BANK), - .NUM_REQ(NUM_REQ) - ) priority_encoder_sm ( - .clk(clk), - .reset(reset), - .valid_i(orig_in_valid), - .address_i(in_address), - .data_i(in_data), - - .valid_o(temp_in_valid), - .address_o(temp_address), - .data_o(temp_in_data), - - .req_num(req_num), - .stall(stall), - .send_data(send_data) - ); - - genvar j; - integer i; - generate - for (j=0; j<= SM_BANKS - 1; j=j+1) begin : shared_mem_blocks - - wire shm_write = (mem_write != `NO_MEM_WRITE) && temp_in_valid[j]; - - VX_shared_memory_block #( - .SMB_HEIGHT(SM_HEIGHT), - .SMB_WORDS_PER_READ(SM_WORDS_PER_READ), - .SMB_LOG_WORDS_PER_READ(SM_LOG_WORDS_PER_READ) - ) shared_memory_block ( - .clk (clk), - .reset (reset), - .addr (block_addr[j]), - .wdata (block_wdata[j]), - .we (block_we[j]), - .shm_write(shm_write), - .data_out (block_rdata[j]) - ); - end - - always @(*) begin - block_addr = 0; - block_we = 0; - block_wdata = 0; - //for(i = 0; i <= NB; i = i+1) begin - for (i = 0; i <= SM_BANKS - 1; i = i+1) begin - if (temp_in_valid[i] == 1'b1) begin - //1. Check if the request is actually to the shared memory - if ((temp_address[i][31:24]) == 8'hFF) begin - // STORES - if (mem_write != `NO_MEM_WRITE) begin - if (mem_write == `SB_MEM_WRITE) begin - //TODO - end - else if (mem_write == `SH_MEM_WRITE) begin - //TODO - end - else if (mem_write == `SW_MEM_WRITE) begin - //block_addr[i] = temp_address[i][13:7]; - //block_we[i] = temp_address[i][6:5]; - //block_wdata[i][temp_address[i][6:5]] = temp_in_data[i]; - block_addr[i] = temp_address[i][SM_INDEX_END:SM_INDEX_START]; - block_we[i] = temp_address[i][SM_BLOCK_OFFSET_END:SM_BLOCK_OFFSET_START]; - block_wdata[i][temp_address[i][SM_BLOCK_OFFSET_END:SM_BLOCK_OFFSET_START]] = temp_in_data[i]; - end - end - //LOADS - else if(mem_read != `NO_MEM_READ) begin - if(mem_read == `LB_MEM_READ) begin - //TODO - end - else if (mem_read == `LH_MEM_READ) - begin - //TODO - end - else if (mem_read == `LW_MEM_READ) - begin - //block_addr[i] = temp_address[i][13:7]; - //temp_out_data[req_num[i]] = block_rdata[i][temp_address[i][6:5]]; - //temp_out_valid[req_num[i]] = 1'b1; - block_addr[i] = temp_address[i][SM_INDEX_END:SM_INDEX_START]; - temp_out_data[req_num[i]] = block_rdata[i][temp_address[i][SM_BLOCK_OFFSET_END:SM_BLOCK_OFFSET_START]]; - temp_out_valid[req_num[i]] = 1'b1; - end - else if (mem_read == `LBU_MEM_READ) - begin - //TODO - end - else if (mem_read == `LHU_MEM_READ) - begin - //TODO - end - end - end - end - end - end - - endgenerate - -endmodule diff --git a/hw/rtl/shared_memory/VX_shared_memory_block.v b/hw/rtl/shared_memory/VX_shared_memory_block.v deleted file mode 100644 index 8410c6b2..00000000 --- a/hw/rtl/shared_memory/VX_shared_memory_block.v +++ /dev/null @@ -1,105 +0,0 @@ -module VX_shared_memory_block -#( - parameter SMB_SIZE = 4096, // Bytes - parameter SMB_BYTES_PER_READ = 16, - parameter SMB_WORDS_PER_READ = 4, - parameter SMB_LOG_WORDS_PER_READ = 2, - parameter SMB_HEIGHT = 128, // Bytes - parameter BITS_PER_BANK = 3 -) -( - input wire clk, // Clock - input wire reset, - //input wire[6:0] addr, - //input wire[3:0][31:0] wdata, - //input wire[1:0] we, - //input wire shm_write, - - //output wire[3:0][31:0] data_out - input wire[$clog2(SMB_HEIGHT) - 1:0] addr, - input wire[SMB_WORDS_PER_READ-1:0][31:0] wdata, - input wire[SMB_LOG_WORDS_PER_READ-1:0] we, - input wire shm_write, - - output wire[SMB_WORDS_PER_READ-1:0][31:0] data_out -); - `ifndef SYN - - reg [SMB_WORDS_PER_READ-1:0][3:0][7:0] shared_memory[SMB_HEIGHT-1:0]; - wire [$clog2(SMB_HEIGHT) - 1:0] reg_addr; - - always @(posedge clk) begin - if (reset) begin - //-- - end else if (shm_write) begin - if (we == 2'b00) shared_memory[reg_addr][0] <= wdata[0]; - if (we == 2'b01) shared_memory[reg_addr][1] <= wdata[1]; - if (we == 2'b10) shared_memory[reg_addr][2] <= wdata[2]; - if (we == 2'b11) shared_memory[reg_addr][3] <= wdata[3]; - end - end - - assign reg_addr = addr; - assign data_out = shm_write ? 0 : shared_memory[reg_addr]; - - `else - - wire cena = 0; - wire cenb = !shm_write; - - wire[3:0][31:0] write_bit_mask; - - //assign write_bit_mask[0] = (we == 2'b00) ? {32{1'b1}} : {32{1'b0}}; - //assign write_bit_mask[1] = (we == 2'b01) ? {32{1'b1}} : {32{1'b0}}; - //assign write_bit_mask[2] = (we == 2'b10) ? {32{1'b1}} : {32{1'b0}}; - //assign write_bit_mask[3] = (we == 2'b11) ? {32{1'b1}} : {32{1'b0}}; - - genvar curr_word; - for (curr_word = 0; curr_word < SMB_WORDS_PER_READ; curr_word = curr_word + 1) - begin - assign write_bit_mask[curr_word] = (we == curr_word) ? 1 : {32{1'b0}}; - end - - // Using ASIC MEM - `IGNORE_WARNINGS_BEGIN - rf2_128x128_wm1 first_ram ( - .CENYA(), - .AYA(), - .CENYB(), - .WENYB(), - .AYB(), - .QA(data_out), - .SOA(), - .SOB(), - .CLKA(clk), - .CENA(cena), - .AA(addr), - .CLKB(clk), - .CENB(cenb), - .WENB(write_bit_mask), - .AB(addr), - .DB(wdata), - .EMAA(3'b011), - .EMASA(1'b0), - .EMAB(3'b011), - .TENA(1'b1), - .TCENA(1'b0), - .TAA(7'b0), - .TENB(1'b1), - .TCENB(1'b0), - .TWENB(128'b0), - .TAB(7'b0), - .TDB(128'b0), - .RET1N(1'b1), - .SIA(2'b0), - .SEA(1'b0), - .DFTRAMBYP(1'b0), - .SIB(2'b0), - .SEB(1'b0), - .COLLDISN(1'b1) - ); - `IGNORE_WARNINGS_END - - `endif - -endmodule diff --git a/hw/unit_tests/generic_queue/testbench.v b/hw/unit_tests/generic_queue/testbench.v index f315df33..885edaeb 100644 --- a/hw/unit_tests/generic_queue/testbench.v +++ b/hw/unit_tests/generic_queue/testbench.v @@ -17,10 +17,10 @@ module testbench(); VX_generic_queue #(.DATAW(4), .SIZE(4)) dut ( .clk(clk), .reset(reset), - .data_i(in_data), + .data_in(in_data), .push(push), .pop(pop), - .data_o(out_data), + .data_out(out_data), .empty(empty), .full(full));