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Quartus + GPR evaluation

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This commit is contained in:
felsabbagh3
2019-09-10 20:23:01 -04:00
parent 4e8da1811a
commit 8d143d7739
68 changed files with 5345 additions and 3066 deletions
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104
rtl/VX_gpr_wrapper.v
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@@ -12,50 +12,29 @@ module VX_gpr_wrapper (
output wire[`NT_M1:0][31:0] out_a_reg_data,
output wire[`NT_M1:0][31:0] out_b_reg_data,
output wire out_clone_stall
output wire out_gpr_stall
);
wire[`NT_M1:0][31:0] temp_a_reg_data;
wire[`NT_M1:0][31:0] temp_b_reg_data;
// wire[`NW-1:0][`NT_M1:0][31:0] temp_a_reg_data;
// wire[`NW-1:0][`NT_M1:0][31:0] temp_b_reg_data;
wire[`NT_M1:0][31:0] jal_data;
genvar index;
for (index = 0; index <= `NT_M1; index = index + 1) assign jal_data[index] = VX_gpr_jal.curr_PC;
// wire[`NT_M1:0][31:0] jal_data;
// genvar index;
// for (index = 0; index <= `NT_M1; index = index + 1) assign jal_data[index] = VX_gpr_jal.curr_PC;
assign out_a_reg_data = (VX_gpr_jal.is_jal ? jal_data : (VX_fwd_rsp.src1_fwd ? VX_fwd_rsp.src1_fwd_data : temp_a_reg_data));
assign out_b_reg_data = (VX_fwd_rsp.src2_fwd ? VX_fwd_rsp.src2_fwd_data : temp_b_reg_data);
wire[`NW-1:0] temp_clone_stall = 0;
assign out_clone_stall = (|temp_clone_stall);
genvar warp_index;
generate
for (warp_index = 0; warp_index < `NW; warp_index = warp_index + 1) begin
wire valid_write_request = warp_index == VX_writeback_inter.wb_warp_num;
wire valid_read_request = warp_index == VX_gpr_read.warp_num;
VX_gpr vx_gpr(
.clk (clk),
.valid_write_request(valid_write_request),
.valid_read_request (valid_read_request),
.VX_gpr_read (VX_gpr_read),
.VX_writeback_inter (VX_writeback_inter),
.out_a_reg_data (temp_a_reg_data),
.out_b_reg_data (temp_b_reg_data)
);
end
endgenerate
// assign out_a_reg_data = VX_gpr_jal.is_jal ? jal_data : temp_a_reg_data[VX_gpr_read.warp_num];
// assign out_b_reg_data = temp_b_reg_data[VX_gpr_read.warp_num];
// wire[31:0][31:0] w0_t0_registers;
// wire[`NW-1:0] temp_clone_stall;
// assign out_gpr_stall = (|temp_clone_stall);
// wire curr_warp_zero = VX_gpr_read.warp_num == 0;
// wire context_zero_valid = (VX_writeback_inter.wb_warp_num == 0);
// wire real_zero_isclone = VX_gpr_clone.is_clone && (VX_gpr_clone.warp_num == 0);
@@ -114,4 +93,59 @@ module VX_gpr_wrapper (
// end
// endgenerate
endmodule
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
wire[`NW-1:0][`NT_M1:0][31:0] temp_a_reg_data;
wire[`NW-1:0][`NT_M1:0][31:0] temp_b_reg_data;
wire[`NT_M1:0][31:0] jal_data;
genvar index;
for (index = 0; index <= `NT_M1; index = index + 1) assign jal_data[index] = VX_gpr_jal.curr_PC;
assign out_a_reg_data = (VX_gpr_jal.is_jal ? jal_data : (VX_fwd_rsp.src1_fwd ? VX_fwd_rsp.src1_fwd_data : temp_a_reg_data[VX_gpr_read.warp_num]));
assign out_b_reg_data = (VX_fwd_rsp.src2_fwd ? VX_fwd_rsp.src2_fwd_data : temp_b_reg_data[VX_gpr_read.warp_num]);
genvar warp_index;
generate
for (warp_index = 0; warp_index < `NW; warp_index = warp_index + 1) begin
wire valid_write_request = warp_index == VX_writeback_inter.wb_warp_num;
VX_gpr vx_gpr(
.clk (clk),
.valid_write_request(valid_write_request),
.VX_gpr_read (VX_gpr_read),
.VX_writeback_inter (VX_writeback_inter),
.out_a_reg_data (temp_a_reg_data[warp_index]),
.out_b_reg_data (temp_b_reg_data[warp_index])
);
end
endgenerate
assign out_gpr_stall = 0;
// // WSPAWN FSM
// reg[3:0] wspawn_state;
// VX_gpr_read_inter VX_wspawn_gpr_read();
// VX_wb_inter VX_wspawn_wb_inter();
// VX_wspawn_gpr_read.rs1
// always @(posedge clk) begin
// if ((in_wspawn) && wspawn_state == 0) begin
// wspawn_state <= 10;
// end else if (wspawn_state == 1) begin
// wspawn_state <= 0;
// end else if (wspawn_state > 0) begin
// wspawn_state <= wspawn_state - 1;
// end
// end
// assign out_gpr_stall = ((wspawn_state == 0) && VX_gpr_wspawn.is_wspawn) || (VX_gpr_wspawn.is_wspawn > 1);;
endmodule