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Connected cache to bank

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This commit is contained in:
felsabbagh3
2020-03-02 23:24:17 -08:00
parent f6cc05eaa2
commit 8c6284f627
4 changed files with 132 additions and 97 deletions
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122
rtl/VX_cache/VX_cache.v
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@@ -41,23 +41,23 @@ module VX_cache (
);
wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_valids;
wire [`NUMBER_BANKS-1:0] per_bank_wb_pop;
wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_wb_tid;
wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd;
wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb;
wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num;
wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data;
wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_valids;
wire [`NUMBER_BANKS-1:0] per_bank_wb_pop;
wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_wb_tid;
wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd;
wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb;
wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num;
wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data;
wire dfqq_full;
wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req;
wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr;
wire dfqq_full;
wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req;
wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr;
wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop;
wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req;
wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr;
wire[`NUMBER_BANKS-1]:0[`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data;
wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop;
wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req;
wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr;
wire[`NUMBER_BANKS-1]:0[`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data;
VX_cache_dram_req_arb VX_cache_dram_req_arb(
.clk (clk),
@@ -103,34 +103,34 @@ module VX_cache (
generate
integer curr_bank;
for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank=curr_bank+1) begin
wire [`NUMBER_REQUESTS-1:0] curr_bank_valids;
wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_addr;
wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_writedata;
wire [4:0] curr_bank_rd;
wire [1:0] curr_bank_wb;
wire [`NW_M1:0] curr_bank_warp_num;
wire [2:0] curr_bank_mem_read;
wire [2:0] curr_bank_mem_write;
wire [`NUMBER_REQUESTS-1:0] curr_bank_valids;
wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_addr;
wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_writedata;
wire [4:0] curr_bank_rd;
wire [1:0] curr_bank_wb;
wire [`NW_M1:0] curr_bank_warp_num;
wire [2:0] curr_bank_mem_read;
wire [2:0] curr_bank_mem_write;
wire curr_bank_wb_pop;
wire [`NUMBER_REQUESTS-1:0] curr_bank_wb_tid;
wire [4:0] curr_bank_wb_rd;
wire [1:0] curr_bank_wb_wb;
wire [`NW_M1:0] curr_bank_wb_warp_num;
wire [31:0] curr_bank_wb_data;
wire curr_bank_wb_pop;
wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] curr_bank_wb_tid;
wire [4:0] curr_bank_wb_rd;
wire [1:0] curr_bank_wb_wb;
wire [`NW_M1:0] curr_bank_wb_warp_num;
wire [31:0] curr_bank_wb_data;
wire curr_bank_dram_fill_rsp;
wire [31:0] curr_bank_dram_fill_rsp_addr;
wire [`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_fill_rsp_data;
wire curr_bank_dram_fill_rsp;
wire [31:0] curr_bank_dram_fill_rsp_addr;
wire [`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_fill_rsp_data;
wire curr_bank_dfqq_full;
wire curr_bank_dram_fill_req;
wire[31:0] curr_bank_dram_fill_req_addr;
wire curr_bank_dfqq_full;
wire curr_bank_dram_fill_req;
wire[31:0] curr_bank_dram_fill_req_addr;
wire curr_bank_dram_wb_queue_pop;
wire curr_bank_dram_wb_req;
wire[31:0] curr_bank_dram_wb_req_addr;
wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_wb_req_data;
wire curr_bank_dram_wb_queue_pop;
wire curr_bank_dram_wb_req;
wire[31:0] curr_bank_dram_wb_req_addr;
wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_wb_req_data;
// Core Req
assign curr_bank_valids = per_bank_valids[curr_bank];
@@ -150,16 +150,16 @@ module VX_cache (
assign per_bank_wb_warp_num[curr_bank] = curr_bank_wb_warp_num;
assign per_bank_wb_data [curr_bank] = curr_bank_wb_data;
// Dram fill response
assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_addr[`BANK_SELECT_ADDR_RNG] == curr_bank);
assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr;
assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data;
// Dram fill request
assign curr_bank_dfqq_full = dfqq_full;
assign per_bank_dram_fill_req[curr_bank] = curr_bank_dram_fill_req;
assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr;
// Dram fill response
assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_addr[`BANK_SELECT_ADDR_RNG] == curr_bank);
assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr;
assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data;
// Dram writeback request
assign curr_bank_dram_wb_queue_pop = per_bank_dram_wb_queue_pop[curr_bank];
assign per_bank_dram_wb_req[curr_bank] = curr_bank_dram_wb_req;
@@ -167,8 +167,42 @@ module VX_cache (
assign per_bank_dram_wb_req_data[curr_bank] = curr_bank_dram_wb_req_data;
VX_cache_bank bank (
VX_bank bank (
.clk (clk),
.reset (reset),
// Core req
.bank_valids (curr_bank_valids),
.bank_addr (curr_bank_addr),
.bank_writedata (curr_bank_writedata),
.bank_rd (curr_bank_rd),
.bank_wb (curr_bank_wb),
.bank_warp_num (curr_bank_warp_num),
.bank_mem_read (curr_bank_mem_read),
.bank_mem_write (curr_bank_mem_write),
// Output core wb
.bank_wb_pop (curr_bank_wb_pop),
.bank_wb_tid (curr_bank_wb_tid),
.bank_wb_rd (curr_bank_wb_rd),
.bank_wb_wb (curr_bank_wb_wb),
.bank_wb_warp_num (curr_bank_wb_warp_num),
.bank_wb_data (curr_bank_wb_data),
// Dram fill req
.dram_fill_req (curr_bank_dram_fill_req),
.dram_fill_req_addr (curr_bank_dram_fill_req_addr),
.dram_fill_req_queue_full(curr_bank_dfqq_full),
// Dram fill rsp
.dram_fill_rsp (curr_bank_dram_fill_rsp),
.dram_fill_addr (curr_bank_dram_fill_rsp_addr),
.dram_fill_rsp_data (curr_bank_dram_fill_rsp_data),
// Dram writeback
.dram_wb_queue_pop (curr_bank_dram_wb_queue_pop),
.dram_wb_req (curr_bank_dram_wb_req),
.dram_wb_req_addr (curr_bank_dram_wb_req_addr),
.dram_wb_req_data (curr_bank_dram_wb_req_data)
);
end