wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'graphics' of https://github.com/vortexgpgpu/vortex-dev into graphics

Browse Source
This commit is contained in:
Blaise Tine
2021-03-20 19:22:11 -04:00
parent 5747d12530 3c8469008f
commit 8c0c4e2b6e
4 changed files with 533 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
hw/rtl/tex_unit/VX_tex_define.vh
View File

@@ -23,4 +23,16 @@
`define TEX_WRAP_CLAMP 1
`define TEX_WRAP_MIRROR 2
`define MAX_COLOR_WIDTH 8
`define NUM_COLOR_CHANNEL 4
`define R5G6B5 `TEX_FORMAT_BITS'h1
`define R8G8B8 `TEX_FORMAT_BITS'h2
`define R8G8B8A8 `TEX_FORMAT_BITS'h3
`define RBEGIN 24
`define GBEGIN 16
`define BBEGIN 8
`define ABEGIN 0
`endif

55
hw/rtl/tex_unit/VX_tex_format.v
View File

@@ -3,10 +3,59 @@
module VX_tex_format #(
parameter CORE_ID = 0
) (
// TODO
input wire [31:0] texel_data,
input wire [`TEX_FORMAT_BITS-1:0] format,
output wire [`NUM_COLOR_CHANNEL-1:0] color_enable,
output wire [`MAX_COLOR_BITS-1:0] R,
output wire [`MAX_COLOR_BITS-1:0] G,
output wire [`MAX_COLOR_BITS-1:0] B,
output wire [`MAX_COLOR_BITS-1:0] A
);
`UNUSED_PARAM (CORE_ID)
// TODO
reg [`NUM_COLOR_CHANNEL-1:0] color_enable_r;
reg [`MAX_COLOR_BITS-1:0] R_r;
reg [`MAX_COLOR_BITS-1:0] G_r;
reg [`MAX_COLOR_BITS-1:0] B_r;
reg [`MAX_COLOR_BITS-1:0] A_r;
always @(*) begin
case (format)
`R5G6B5:
R_r = `MAX_COLOR_BITS'(texel_data[15:11]);
G_r = `MAX_COLOR_BITS'(texel_data[10:5]);
B_r = `MAX_COLOR_BITS'(texel_data[4:0]);
A_r = {`MAX_COLOR_BITS{1'b0}};
color_enable_r = 4'b1110;
`R8G8B8:
R_r = `MAX_COLOR_BITS'(texel_data[23:16]);
G_r = `MAX_COLOR_BITS'(texel_data[15:8]);
B_r = `MAX_COLOR_BITS'(texel_data[7:0]);
A_r = {`MAX_COLOR_BITS{1'b0}};
color_enable_r = 4'b1110;
`R8G8B8A8:
R_r = `MAX_COLOR_BITS'(texel_data[31:24]);
G_r = `MAX_COLOR_BITS'(texel_data[23:16]);
B_r = `MAX_COLOR_BITS'(texel_data[15:8]);
A_r = `MAX_COLOR_BITS'(texel_data[7:0]);
color_enable_r = 4'b1111;
default:
R_r = `MAX_COLOR_BITS'(texel_data[23:16]);
G_r = `MAX_COLOR_BITS'(texel_data[15:8]);
B_r = `MAX_COLOR_BITS'(texel_data[7:0]);
A_r = {`MAX_COLOR_BITS{1'b0}};
color_enable_r = 4'b1110;
endcase
end
assign color_enable = color_enable_r;
assign R = R_r;
assign G = G_r;
assign B = B_r;
assign A = A_r;
endmodule

65
hw/rtl/tex_unit/VX_tex_sampler.v
View File

@@ -15,6 +15,8 @@ module VX_tex_sampler #(
input wire req_wb,
input wire [`TEX_FILTER_BITS-1:0] req_filter,
input wire [`TEX_FORMAT_BITS-1:0] req_format,
input wire [3:0][`FIXED_FRAC-1:0] req_ufrac,
input wire [3:0][`FIXED_FRAC-1:0] req_vfrac,
input wire [`NUM_THREADS-1:0][3:0][31:0] req_texels,
output wire req_ready,
@@ -30,41 +32,48 @@ module VX_tex_sampler #(
);
`UNUSED_PARAM (CORE_ID)
if (req_filter == 0) begin // point sampling
/*
assign tex_req_if.ready = (& pt_addr_ready);
wire [31:0] req_data [`NUM_THREADS-1:0];
assign lsu_req_if.valid = (& pt_addr_valid);
for (genvar i = 0; i<`NUM_THREADS ;i++ ) begin
VX_tex_format #(
.CORE_ID (CORE_ID)
) tex_format_point (
.texel_data (req_texels[i]),
.format (req_format),
assign lsu_req_if.wid = tex_req_if.wid;
assign lsu_req_if.tmask = tex_req_if.tmask;
assign lsu_req_if.PC = tex_req_if.PC;
assign lsu_req_if.rd = tex_req_if.rd;
assign lsu_req_if.wb = tex_req_if.wb;
assign lsu_req_if.offset = 32'h0000;
assign lsu_req_if.op_type = `OP_BITS'({1'b0, 3'b000}); //func3 for word load??
assign lsu_req_if.store_data = {`NUM_THREADS{32'h0000}};
.color_enable (),
.R(req_data[i][`RBEGIN +: 8]),
.G(req_data[i][`GBEGIN +: 8]),
.B(req_data[i][`BBEGIN +: 8]),
.A(req_data[i][`ABEGIN +: 8])
);
// wait buffer for fragments / replace with cache/state fragment fifo for bilerp
// no filtering for point sampling -> directly from dcache to output response
end
VX_pipe_register #(
.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)),
.RESETW (1)
) pipe_reg (
.clk (clk),
.reset (reset),
.enable (~stall_out),
.data_in ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data}),
.data_out ({tex_rsp_if.valid, tex_rsp_if.wid, tex_rsp_if.tmask, tex_rsp_if.PC, tex_rsp_if.rd, tex_rsp_if.wb, tex_rsp_if.data})
);
VX_pipe_register #(
.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)),
.RESETW (1)
) pipe_reg (
.clk (clk),
.reset (reset),
.enable (~stall_out),
.data_in ({req_valid, req_wid, req_tmask, req_PC, req_rd, req_wb, req_data}),
.data_out ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data})
);
// output
assign stall_out = ~tex_rsp_if.ready && tex_rsp_if.valid;
// output
assign stall_out = ~rsp_ready;
assign req_ready = rsp_ready;
end else begin // bilinear sampling
// TO DO
end
// can accept new request?
assign stall_in = stall_out;
assign ld_commit_if.ready = ~stall_in;*/
endmodule