Need to link SystemC for sc_time_stamp()
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11
rtl/VX_gpr.v
11
rtl/VX_gpr.v
@@ -55,7 +55,11 @@ module VX_gpr (
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// .q1 (out_b_reg_data)
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// );
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wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}};
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// Port A is a read port, Port B is a write port
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/* verilator lint_off PINCONNECTEMPTY */
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rf2_32x128_wm1 first_ram (
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.CENYA(),
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.AYA(),
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@@ -70,7 +74,7 @@ module VX_gpr (
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.AA(VX_gpr_read.rs1),
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.CLKB(clk),
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.CENB(1'b0),
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.WENB({32{~(VX_writeback_inter.wb_valid[3])}, 32{~(VX_writeback_inter.wb_valid[2])}, 32{~(VX_writeback_inter.wb_valid[1])}, 32{~(VX_writeback_inter.wb_valid[0])}}),
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.WENB(write_bit_mask),
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.AB(VX_writeback_inter.rd),
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.DB(VX_writeback_inter.write_data),
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.EMAA(3'b011),
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@@ -92,7 +96,9 @@ module VX_gpr (
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.SEB(1'b0),
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.COLLDISN(1'b1)
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);
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/* verilator lint_on PINCONNECTEMPTY */
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/* verilator lint_off PINCONNECTEMPTY */
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rf2_32x128_wm1 second_ram (
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.CENYA(),
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.AYA(),
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@@ -107,7 +113,7 @@ module VX_gpr (
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.AA(VX_gpr_read.rs2),
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.CLKB(clk),
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.CENB(1'b0),
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.WENB({32{~(VX_writeback_inter.wb_valid[3])}, 32{~(VX_writeback_inter.wb_valid[2])}, 32{~(VX_writeback_inter.wb_valid[1])}, 32{~(VX_writeback_inter.wb_valid[0])}}),
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.WENB(write_bit_mask),
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.AB(VX_writeback_inter.rd),
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.DB(VX_writeback_inter.write_data),
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.EMAA(3'b011),
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@@ -129,6 +135,7 @@ module VX_gpr (
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.SEB(1'b0),
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.COLLDISN(1'b1)
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);
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/* verilator lint_on PINCONNECTEMPTY */
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// >>>>>>> 5680b997b599ce2900997cab976681fe3881e880
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