disabling fetch's deadlock check when L1 caches are present

hw/rtl/core/VX_fetch.sv

@@ -32,7 +32,6 @@ module VX_fetch import VX_gpu_pkg::*; #(
 );
     `UNUSED_PARAM (CORE_ID)
     `UNUSED_VAR (reset)
-    localparam ISW_WIDTH  = `LOG2UP(`ISSUE_WIDTH);
 
     wire icache_req_valid;
     wire [ICACHE_ADDR_WIDTH-1:0] icache_req_addr;
@@ -44,8 +43,6 @@ module VX_fetch import VX_gpu_pkg::*; #(
 
     wire icache_req_fire = icache_req_valid && icache_req_ready;
 
-    wire [ISW_WIDTH-1:0] schedule_isw = wid_to_isw(schedule_if.data.wid);
-    
     assign req_tag = schedule_if.data.wid;
     
     assign {rsp_uuid, rsp_tag} = icache_bus_if.rsp_data.tag;
@@ -68,9 +65,12 @@ module VX_fetch import VX_gpu_pkg::*; #(
         .rdata ({rsp_PC, rsp_tmask})
     );
 
+`ifndef L1_ENABLE
     // Ensure that the ibuffer doesn't fill up.
     // This resolves potential deadlock if ibuffer fills and the LSU stalls the execute stage due to pending dcache request.
     // This issue is particularly prevalent when the icache and dcache is disabled and both requests share the same bus.
+    wire [ISSUE_ISW-1:0] schedule_isw = wid_to_isw(schedule_if.data.wid);
+
     wire [`ISSUE_WIDTH-1:0] pending_ibuf_full;
     for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
         VX_pending_size #( 
@@ -85,13 +85,16 @@ module VX_fetch import VX_gpu_pkg::*; #(
             `UNUSED_PIN (empty)
         );
     end
+    wire ibuf_ready = ~pending_ibuf_full[schedule_isw];
+`else
+    wire ibuf_ready = 1'b1;
+`endif
 
     `RUNTIME_ASSERT((!schedule_if.valid || schedule_if.data.PC != 0), 
         ("%t: *** invalid PC=0x%0h, wid=%0d, tmask=%b (#%0d)", $time, schedule_if.data.PC, schedule_if.data.wid, schedule_if.data.tmask, schedule_if.data.uuid))
 
     // Icache Request
     
-    wire ibuf_ready = ~pending_ibuf_full[schedule_isw];
     assign icache_req_valid = schedule_if.valid && ibuf_ready;
     assign icache_req_addr  = schedule_if.data.PC[`MEM_ADDR_WIDTH-1:2];
     assign icache_req_tag   = {schedule_if.data.uuid, req_tag};