diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 38fe3d60..c1503a94 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -21,7 +21,7 @@ DBG_FLAGS += -DDBG_CORE_REQ_INFO #CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DEBUG=1 +#DEBUG=1 #AFU=1 CFLAGS += -fPIC @@ -35,11 +35,13 @@ TOP = Vortex SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp -RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/cache +FPU_INCLUDE = -I../../hw/rtl/fp_cores/fpnew/src/common_cells/include -I../../hw/rtl/fp_cores/fpnew/src/common_cells/src -I../../hw/rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I../../hw/rtl/fp_cores/fpnew/src +RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/cache $(FPU_INCLUDE) VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS) VL_FLAGS += -Wno-DECLFILENAME VL_FLAGS += --x-initial unique --x-assign unique +VL_FLAGS += verilator.vlt # Enable Verilator multithreaded simulation #THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') diff --git a/driver/rtlsim/simulator.cpp b/driver/rtlsim/simulator.cpp deleted file mode 100644 index 6ff72603..00000000 --- a/driver/rtlsim/simulator.cpp +++ /dev/null @@ -1,71 +0,0 @@ -#include "simulator.h" -#include -#include -#include - -uint64_t timestamp = 0; - -double sc_time_stamp() { - return timestamp; -} - -Simulator::Simulator() { - // force random values for unitialized signals - const char* args[] = {"", "+verilator+rand+reset+2", "+verilator+seed+50"}; - Verilated::commandArgs(3, args); - - vortex_ = new Vvortex_afu_sim(); - -#ifdef VCD_OUTPUT - Verilated::traceEverOn(true); - trace_ = new VerilatedVcdC; - trace_->set_time_unit("1ns"); - vortex_->trace(trace_, 99); - trace_->open("trace.vcd"); -#endif -} - -Simulator::~Simulator() { -#ifdef VCD_OUTPUT - trace_->close(); -#endif - delete vortex_; -} - -void Simulator::reset() { -#ifndef NDEBUG - std::cout << timestamp << ": [sim] reset()" << std::endl; -#endif - vortex_->reset = 1; - this->step(); - vortex_->reset = 0; - - dram_rsp_vec_.clear(); -} - -void Simulator::step() { - vortex_->clk = 0; - this->eval(); - - vortex_->clk = 1; - this->eval(); - - avs_driver(); - ccip_driver(); -} - -void Simulator::eval() { - vortex_->eval(); -#ifdef VCD_OUTPUT - trace_->dump(timestamp); -#endif - ++timestamp; -} - -void Simulator::avs_driver() { - //-- -} - - void Simulator::ccip_driver() { - //-- - } \ No newline at end of file diff --git a/driver/rtlsim/simulator.h b/driver/rtlsim/simulator.h deleted file mode 100644 index 50d666d3..00000000 --- a/driver/rtlsim/simulator.h +++ /dev/null @@ -1,59 +0,0 @@ -#pragma once - -#include "Vvortex_afu_sim.h" -#include "Vvortex_afu_sim__Syms.h" -#include "verilated.h" - -#ifdef VCD_OUTPUT -#include -#endif - -#include -#include "ram.h" - -#include -#include - -#define ENABLE_DRAM_STALLS -#define DRAM_LATENCY 100 -#define DRAM_RQ_SIZE 16 -#define DRAM_STALLS_MODULO 16 - -typedef struct { - int cycles_left; - uint8_t *data; - unsigned tag; -} dram_req_t; - -class Simulator { -public: - - Simulator(); - virtual ~Simulator(); - - void reset(); - - void step(); - - int mmio_read(uint64_t addr, uint64_t* value); - - int mmio_write(uint64_t addr, uint64_t value); - -private: - - void eval(); - - void avs_driver(); - - void ccip_driver(); - - std::vector dram_rsp_vec_; - - RAM ram_; - Vvortex_afu_sim *vortex_; - - -#ifdef VCD_OUTPUT - VerilatedVcdC *trace_; -#endif -}; \ No newline at end of file diff --git a/driver/rtlsim/verilator.vlt b/driver/rtlsim/verilator.vlt new file mode 100644 index 00000000..c0cd70d7 --- /dev/null +++ b/driver/rtlsim/verilator.vlt @@ -0,0 +1,9 @@ +`verilator_config + +lint_off -rule BLKANDNBLK -file "../../hw/rtl/fp_cores/fpnew/*" +lint_off -rule UNOPTFLAT -file "../../hw/rtl/fp_cores/fpnew/*" +lint_off -rule WIDTH -file "../../hw/rtl/fp_cores/fpnew/*" +lint_off -rule UNUSED -file "../../hw/rtl/fp_cores/fpnew/*" +lint_off -rule LITENDIAN -file "../../hw/rtl/fp_cores/fpnew/*" +lint_off -rule IMPORTSTAR -file "../../hw/rtl/fp_cores/fpnew/*" +lint_off -rule PINCONNECTEMPTY -file "../../hw/rtl/fp_cores/fpnew/*" \ No newline at end of file diff --git a/hw/rtl/VX_alu_unit.v b/hw/rtl/VX_alu_unit.v index 13e7b2a1..61867ac2 100644 --- a/hw/rtl/VX_alu_unit.v +++ b/hw/rtl/VX_alu_unit.v @@ -11,7 +11,7 @@ module VX_alu_unit #( // Outputs VX_branch_ctl_if branch_ctl_if, - VX_commit_if alu_commit_if + VX_exu_to_cmt_if alu_commit_if ); reg [`NUM_THREADS-1:0][31:0] alu_result; wire [`NUM_THREADS-1:0][32:0] sub_result; diff --git a/hw/rtl/VX_commit.v b/hw/rtl/VX_commit.v index 5e0767bc..2ebe6b06 100644 --- a/hw/rtl/VX_commit.v +++ b/hw/rtl/VX_commit.v @@ -3,16 +3,16 @@ module VX_commit #( parameter CORE_ID = 0 ) ( - input wire clk, - input wire reset, + input wire clk, + input wire reset, // inputs - VX_commit_if alu_commit_if, - VX_commit_if lsu_commit_if, - VX_commit_if mul_commit_if, - VX_commit_if csr_commit_if, + VX_exu_to_cmt_if alu_commit_if, + VX_exu_to_cmt_if lsu_commit_if, + VX_exu_to_cmt_if mul_commit_if, + VX_exu_to_cmt_if csr_commit_if, VX_fpu_to_cmt_if fpu_commit_if, - VX_commit_if gpu_commit_if, + VX_exu_to_cmt_if gpu_commit_if, // outputs VX_cmt_to_issue_if cmt_to_issue_if, @@ -31,7 +31,7 @@ module VX_commit #( wire [`NE_BITS:0] num_commits; - VX_countones #( + VX_countones #( .N(`NUM_EXS) ) valids_counter ( .valids(commited_mask), diff --git a/hw/rtl/VX_csr_arb.v b/hw/rtl/VX_csr_arb.v index 3feb03cc..ed7e7f24 100644 --- a/hw/rtl/VX_csr_arb.v +++ b/hw/rtl/VX_csr_arb.v @@ -12,10 +12,10 @@ module VX_csr_arb ( VX_csr_req_if csr_req_if, // input - VX_commit_if csr_rsp_if, + VX_exu_to_cmt_if csr_rsp_if, // outputs - VX_commit_if csr_commit_if, + VX_exu_to_cmt_if csr_commit_if, VX_csr_io_rsp_if csr_io_rsp_if, input wire select_io_req, diff --git a/hw/rtl/VX_csr_unit.v b/hw/rtl/VX_csr_unit.v index 422aa8c3..8e4baf8b 100644 --- a/hw/rtl/VX_csr_unit.v +++ b/hw/rtl/VX_csr_unit.v @@ -13,10 +13,10 @@ module VX_csr_unit #( VX_csr_io_rsp_if csr_io_rsp_if, VX_csr_req_if csr_req_if, - VX_commit_if csr_commit_if + VX_exu_to_cmt_if csr_commit_if ); VX_csr_req_if csr_pipe_req_if(); - VX_commit_if csr_pipe_commit_if(); + VX_exu_to_cmt_if csr_pipe_commit_if(); wire select_io_req = csr_io_req_if.valid; wire select_io_rsp; diff --git a/hw/rtl/VX_execute.v b/hw/rtl/VX_execute.v index d622d38f..18947d19 100644 --- a/hw/rtl/VX_execute.v +++ b/hw/rtl/VX_execute.v @@ -31,12 +31,12 @@ module VX_execute #( // outputs VX_branch_ctl_if branch_ctl_if, VX_warp_ctl_if warp_ctl_if, - VX_commit_if alu_commit_if, - VX_commit_if lsu_commit_if, - VX_commit_if csr_commit_if, - VX_commit_if mul_commit_if, + VX_exu_to_cmt_if alu_commit_if, + VX_exu_to_cmt_if lsu_commit_if, + VX_exu_to_cmt_if csr_commit_if, + VX_exu_to_cmt_if mul_commit_if, VX_fpu_to_cmt_if fpu_commit_if, - VX_commit_if gpu_commit_if, + VX_exu_to_cmt_if gpu_commit_if, output wire ebreak ); diff --git a/hw/rtl/VX_fpu_unit.v b/hw/rtl/VX_fpu_unit.v index ed83f57c..f01cbf19 100644 --- a/hw/rtl/VX_fpu_unit.v +++ b/hw/rtl/VX_fpu_unit.v @@ -111,6 +111,8 @@ module VX_fpu_unit #( endcase end +`DISABLE_TRACING + fpnew_top #( .Features (FPU_FEATURES), .Implementation (FPU_IMPLEMENTATION), @@ -138,6 +140,8 @@ module VX_fpu_unit #( `UNUSED_PIN (busy_o) ); +`ENABLE_TRACING + reg [`NUM_THREADS-1:0][31:0] fpu_result_qual; always @(8) begin @@ -168,6 +172,7 @@ module VX_fpu_unit #( assign fpu_in_valid = fpu_req_if.valid; assign fpu_in_tag = fpu_req_if.issue_tag; + // can accept new request? assign fpu_req_if.ready = fpu_in_ready; assign fpu_commit_if.valid = fpu_out_valid; diff --git a/hw/rtl/VX_gpu_unit.v b/hw/rtl/VX_gpu_unit.v index 208193d6..23439d7d 100644 --- a/hw/rtl/VX_gpu_unit.v +++ b/hw/rtl/VX_gpu_unit.v @@ -4,11 +4,11 @@ module VX_gpu_unit #( parameter CORE_ID = 0 ) ( // Input - VX_gpu_req_if gpu_req_if, + VX_gpu_req_if gpu_req_if, // Output - VX_warp_ctl_if warp_ctl_if, - VX_commit_if gpu_commit_if + VX_warp_ctl_if warp_ctl_if, + VX_exu_to_cmt_if gpu_commit_if ); wire is_wspawn = (gpu_req_if.gpu_op == `GPU_WSPAWN); diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index 7198f97a..3cbfb512 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -9,14 +9,14 @@ module VX_lsu_unit #( input wire reset, // Dcache interface - VX_cache_core_req_if dcache_req_if, - VX_cache_core_rsp_if dcache_rsp_if, + VX_cache_core_req_if dcache_req_if, + VX_cache_core_rsp_if dcache_rsp_if, // inputs - VX_lsu_req_if lsu_req_if, + VX_lsu_req_if lsu_req_if, // outputs - VX_commit_if lsu_commit_if + VX_exu_to_cmt_if lsu_commit_if ); wire use_valid; @@ -61,8 +61,7 @@ module VX_lsu_unit #( assign mem_req_data[i] = lsu_req_if.store_data[i] << {mem_req_offset[i], 3'b0}; end - wire store_stalled; - wire stall_in = store_stalled || ~dcache_req_if.ready; + wire stall_in = ~dcache_req_if.ready; // Can accept new request? assign lsu_req_if.ready = ~stall_in; @@ -124,7 +123,7 @@ module VX_lsu_unit #( end // Core Request - assign dcache_req_if.valid = {`NUM_THREADS{use_valid && ~store_stalled}} & use_thread_mask; + assign dcache_req_if.valid = {`NUM_THREADS{use_valid}} & use_thread_mask; assign dcache_req_if.rw = {`NUM_THREADS{use_req_rw}}; assign dcache_req_if.byteen = use_req_byteen; assign dcache_req_if.addr = use_req_addr; @@ -151,17 +150,14 @@ module VX_lsu_unit #( end wire is_store_rsp = dcache_req_fire && use_req_rw; - wire is_load_rsp = (| dcache_rsp_if.valid) && (0 == mem_rsp_mask_n); - - assign store_stalled = use_req_rw && (~lsu_commit_if.ready - || is_load_rsp); // arbitration prioritizes LOAD + wire is_load_rsp = (| dcache_rsp_if.valid) && (0 == mem_rsp_mask_n); assign lsu_commit_if.valid = is_load_rsp || is_store_rsp; - assign lsu_commit_if.issue_tag = is_load_rsp ? rsp_issue_tag : use_issue_tag; + assign lsu_commit_if.issue_tag = is_store_rsp ? use_issue_tag : rsp_issue_tag; assign lsu_commit_if.data = mem_rsp_data | mem_rsp_data_all; - // Can accept new cache response - assign dcache_rsp_if.ready = lsu_commit_if.ready; + // Can accept new cache response? + assign dcache_rsp_if.ready = lsu_commit_if.ready && ~is_store_rsp; // STORE has priority // scope registration `SCOPE_ASSIGN(scope_dcache_req_valid, dcache_req_if.valid); @@ -187,8 +183,8 @@ module VX_lsu_unit #( `ifdef DBG_PRINT_CORE_DCACHE always @(posedge clk) begin if ((| dcache_req_if.valid) && dcache_req_if.ready) begin - $display("%t: D$%0d req: valid=%b, warp=%0d, PC=%0h, addr=%0h, tag=%0h, rd=%0d, rw=%0b, byteen=%0h, data=%0h", - $time, CORE_ID, dcache_req_if.valid, use_warp_num, use_pc, use_address, dcache_req_if.tag, use_rd, dcache_req_if.rw, dcache_req_if.byteen, dcache_req_if.data); + $display("%t: D$%0d req: warp=%0d, PC=%0h, tmask=%b, addr=%0h, tag=%0h, rd=%0d, rw=%0b, byteen=%0h, data=%0h", + $time, CORE_ID, use_warp_num, use_pc, dcache_req_if.valid, use_address, dcache_req_if.tag, use_rd, dcache_req_if.rw, dcache_req_if.byteen, dcache_req_if.data); end if ((| dcache_rsp_if.valid) && dcache_rsp_if.ready) begin $display("%t: D$%0d rsp: valid=%b, warp=%0d, PC=%0h, tag=%0h, rd=%0d, data=%0h", diff --git a/hw/rtl/VX_mul_unit.v b/hw/rtl/VX_mul_unit.v index 34744bd0..691f30ae 100644 --- a/hw/rtl/VX_mul_unit.v +++ b/hw/rtl/VX_mul_unit.v @@ -7,10 +7,10 @@ module VX_mul_unit #( input wire reset, // Inputs - VX_mul_req_if alu_req_if, + VX_mul_req_if alu_req_if, // Outputs - VX_commit_if alu_commit_if + VX_exu_to_cmt_if alu_commit_if ); wire [`MUL_BITS-1:0] alu_op = alu_req_if.mul_op; diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.v index 5e1e46f7..79219a1a 100644 --- a/hw/rtl/VX_pipeline.v +++ b/hw/rtl/VX_pipeline.v @@ -116,12 +116,12 @@ module VX_pipeline #( VX_cmt_to_issue_if cmt_to_issue_if(); VX_wstall_if wstall_if(); VX_join_if join_if(); - VX_commit_if alu_commit_if(); - VX_commit_if lsu_commit_if(); - VX_commit_if csr_commit_if(); - VX_commit_if mul_commit_if(); + VX_exu_to_cmt_if alu_commit_if(); + VX_exu_to_cmt_if lsu_commit_if(); + VX_exu_to_cmt_if csr_commit_if(); + VX_exu_to_cmt_if mul_commit_if(); VX_fpu_to_cmt_if fpu_commit_if(); - VX_commit_if gpu_commit_if(); + VX_exu_to_cmt_if gpu_commit_if(); VX_fetch #( .CORE_ID(CORE_ID) diff --git a/hw/rtl/VX_writeback.v b/hw/rtl/VX_writeback.v index 830898a9..578391d5 100644 --- a/hw/rtl/VX_writeback.v +++ b/hw/rtl/VX_writeback.v @@ -3,19 +3,19 @@ module VX_writeback #( parameter CORE_ID = 0 ) ( - input wire clk, - input wire reset, + input wire clk, + input wire reset, // inputs - VX_commit_if alu_commit_if, - VX_commit_if lsu_commit_if, - VX_commit_if mul_commit_if, - VX_fpu_to_cmt_if fpu_commit_if, - VX_commit_if csr_commit_if, - VX_cmt_to_issue_if cmt_to_issue_if, + VX_exu_to_cmt_if alu_commit_if, + VX_exu_to_cmt_if lsu_commit_if, + VX_exu_to_cmt_if mul_commit_if, + VX_fpu_to_cmt_if fpu_commit_if, + VX_exu_to_cmt_if csr_commit_if, + VX_cmt_to_issue_if cmt_to_issue_if, // outputs - VX_wb_if writeback_if + VX_wb_if writeback_if ); wire alu_valid = alu_commit_if.valid && cmt_to_issue_if.alu_data.wb; diff --git a/hw/rtl/interfaces/VX_commit_if.v b/hw/rtl/interfaces/VX_exu_to_cmt_if.v similarity index 74% rename from hw/rtl/interfaces/VX_commit_if.v rename to hw/rtl/interfaces/VX_exu_to_cmt_if.v index c0c60df8..df5d3c14 100644 --- a/hw/rtl/interfaces/VX_commit_if.v +++ b/hw/rtl/interfaces/VX_exu_to_cmt_if.v @@ -1,9 +1,9 @@ -`ifndef VX_COMMIT_IF -`define VX_COMMIT_IF +`ifndef VX_EXU_TO_CMT_IF +`define VX_EXU_TO_CMT_IF `include "VX_define.vh" -interface VX_commit_if (); +interface VX_exu_to_cmt_if (); wire valid; wire [`ISTAG_BITS-1:0] issue_tag; diff --git a/hw/simulate/Makefile b/hw/simulate/Makefile index 327d5aa4..7aec5eeb 100644 --- a/hw/simulate/Makefile +++ b/hw/simulate/Makefile @@ -17,9 +17,8 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE DBG_FLAGS += $(DBG_PRINT_FLAGS) #DBG_FLAGS += -DDBG_CORE_REQ_INFO -INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/cache -I../rtl/fp_cores -I../rtl/simulate - -INCLUDE += -I../rtl/fp_cores/fpnew/src/common_cells/include -I../rtl/fp_cores/fpnew/src/common_cells/src -I../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I../rtl/fp_cores/fpnew/src +FPU_INCLUDE = -I../rtl/fp_cores/fpnew/src/common_cells/include -I../rtl/fp_cores/fpnew/src/common_cells/src -I../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I../rtl/fp_cores/fpnew/src +INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/cache -I../rtl/fp_cores -I../rtl/simulate $(FPU_INCLUDE) SRCS = simulator.cpp testbench.cpp diff --git a/hw/simulate/testbench.cpp b/hw/simulate/testbench.cpp index 080a845f..0ba41176 100644 --- a/hw/simulate/testbench.cpp +++ b/hw/simulate/testbench.cpp @@ -137,7 +137,7 @@ int main(int argc, char **argv) simulator.load_ihex(test); simulator.run(); - bool status = (1 == simulator.get_last_wb_value(28)); + bool status = (1 == simulator.get_last_wb_value(3)); if (status) std::cerr << GREEN << "Test Passed: " << test << std::endl; if (!status) std::cerr << RED << "Test Failed: " << test << std::endl; diff --git a/hw/simulate/verilator.vlt b/hw/simulate/verilator.vlt index 7e8fdd49..5598b43e 100644 --- a/hw/simulate/verilator.vlt +++ b/hw/simulate/verilator.vlt @@ -6,6 +6,4 @@ lint_off -rule WIDTH -file "../rtl/fp_cores/fpnew/*" lint_off -rule UNUSED -file "../rtl/fp_cores/fpnew/*" lint_off -rule LITENDIAN -file "../rtl/fp_cores/fpnew/*" lint_off -rule IMPORTSTAR -file "../rtl/fp_cores/fpnew/*" -lint_off -rule PINCONNECTEMPTY -file "../rtl/fp_cores/fpnew/*" - -//lint_off -rule CASEINCOMPLETE -file "../rtl/fp_cores/fpnew/*" +lint_off -rule PINCONNECTEMPTY -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file diff --git a/hw/syn/yosys/synth.ys b/hw/syn/yosys/synth.ys new file mode 100644 index 00000000..958f0353 --- /dev/null +++ b/hw/syn/yosys/synth.ys @@ -0,0 +1,136 @@ +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_countones.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_divide.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_encoder_onehot.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_fair_arbiter.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_fixed_arbiter.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_generic_queue.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_generic_register.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_generic_stack.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_indexable_queue.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_matrix_arbiter.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_mult.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_priority_encoder.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_rr_arbiter.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_scope.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_bank.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_bank_core_req_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_core_req_bank_sel.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_core_rsp_merge.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_dram_fill_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_dram_req_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_miss_resrv.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_prefetcher.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_snp_forwarder.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_snp_rsp_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_tag_data_access.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_tag_data_structure.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_backend_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_branch_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_core_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_core_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_dram_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_dram_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_snp_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_snp_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_io_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_io_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_exec_unit_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_gpr_read_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_gpu_inst_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_inst_meta_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_jal_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_join_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_lsu_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_warp_ctl_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_wb_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_wstall_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_alu_unit.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_back_end.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_cluster.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_core.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_csr_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_csr_data.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_csr_io_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_csr_pipe.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_d_e_reg.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_dcache_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_decode.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_exec_unit.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_f_d_reg.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_fetch.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_front_end.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_gpr_ram.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_gpr_stage.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_gpr_wrapper.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_gpu_inst.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_i_d_reg.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_icache_stage.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_inst_multiplex.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_lsu_unit.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_mem_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_mem_unit.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_pipeline.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_scheduler.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_user_config.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_warp.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_warp_sched.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/VX_writeback.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/Vortex.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_bank.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_bank_core_req_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_core_req_bank_sel.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_core_rsp_merge.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_dram_fill_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_dram_req_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_cache_miss_resrv.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_prefetcher.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_snp_forwarder.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_snp_rsp_arb.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_tag_data_access.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/cache/VX_tag_data_structure.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_backend_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_branch_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_core_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_core_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_dram_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_dram_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_snp_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_cache_snp_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_io_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_io_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_csr_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_exec_unit_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_gpr_read_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_gpu_inst_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_inst_meta_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_jal_rsp_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_join_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_lsu_req_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_warp_ctl_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_wb_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/interfaces/VX_wstall_if.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_countones.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_divide.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_encoder_onehot.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_fair_arbiter.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_fixed_arbiter.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_generic_queue.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_generic_register.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_generic_stack.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_indexable_queue.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_matrix_arbiter.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_mult.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_priority_encoder.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_rr_arbiter.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/libs/VX_scope.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/tex_unit/VX_tex_mgr.v +read_verilog -sv -I../../rtl/libs -I../../rtl/cache -I../../rtl/interfaces -I../../rtl ../../rtl/tex_unit/VX_tex_unit.v +hierarchy -check -top Vortex +add -global_input reset 1 +proc -global_arst reset +synth -run coarse; opt -fine +tee -o brams.log memory_bram -rules scripts/brams.txt;; +write_verilog -noexpr -noattr synth.v