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adding DEBUG MACROS

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This commit is contained in:
Blaise Tine
2020-04-19 04:59:52 -04:00
parent 9b476f1e17
commit 885869df4a
32 changed files with 84 additions and 2397 deletions
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8
hw/rtl/generic_cache/VX_bank.v
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@@ -304,9 +304,9 @@ module VX_bank #(
wire valid_st1 [STAGE_1_CYCLES-1:0];
wire is_fill_st1 [STAGE_1_CYCLES-1:0];
/* verilator lint_off UNUSED */
`DEBUG_BEGIN
wire going_to_write_st1[STAGE_1_CYCLES-1:0];
/* verilator lint_on UNUSED */
`DEBUG_END
wire [31:0] addr_st1 [STAGE_1_CYCLES-1:0];
integer p_stage;
@@ -417,12 +417,12 @@ module VX_bank #(
wire miss_st1e;
wire dirty_st1e;
wire[31:0] pc_st1e;
/* verilator lint_off UNUSED */
`DEBUG_BEGIN
wire [4:0] rd_st1e;
wire [1:0] wb_st1e;
wire [`NW_BITS-1:0] warp_num_st1e;
wire [`LOG2UP(NUM_REQUESTS)-1:0] tid_st1e;
/* verilator lint_on UNUSED */
`DEBUG_END
wire [2:0] mem_read_st1e;
wire [2:0] mem_write_st1e;
wire fill_saw_dirty_st1e;

4
hw/rtl/generic_cache/VX_cache.v
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@@ -115,9 +115,9 @@ module VX_cache #(
wire dfqq_full;
wire [NUM_BANKS-1:0] per_bank_dram_fill_req_valid;
wire [NUM_BANKS-1:0][31:0] per_bank_dram_fill_req_addr;
/* verilator lint_off UNUSED */
`DEBUG_BEGIN
wire [NUM_BANKS-1:0] per_bank_dram_fill_req_is_snp;
/* verilator lint_on UNUSED */
`DEBUG_END
wire [NUM_BANKS-1:0] per_bank_dram_rsp_ready;
wire [NUM_BANKS-1:0] per_bank_dram_wb_queue_pop;

6
hw/rtl/generic_cache/VX_cache_dram_req_arb.v
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@@ -94,9 +94,11 @@ module VX_cache_dram_req_arb #(
);
wire[31:0] dfqq_req_addr;
/* verilator lint_off UNUSED */
`DEBUG_BEGIN
wire dfqq_empty;
/* verilator lint_on UNUSED */
`DEBUG_END
wire dfqq_pop = !dwb_valid && dfqq_req && !dram_req_full; // If no dwb, and dfqq has valids, then pop
wire dfqq_push = (|per_bank_dram_fill_req_valid);

4
hw/rtl/generic_cache/VX_cache_miss_resrv.v
View File

@@ -61,10 +61,10 @@ module VX_cache_miss_resrv #(
// Broadcast Fill
input wire is_fill_st1,
/* verilator lint_off UNUSED */
`IGNORE_WARNINGS_BEGIN
// TODO: should fix this
input wire[31:0] fill_addr_st1,
/* verilator lint_on UNUSED */
`IGNORE_WARNINGS_END
// Miss dequeue
input wire miss_resrv_pop,

4
hw/rtl/generic_cache/VX_cache_req_queue.v
View File

@@ -103,9 +103,9 @@ module VX_cache_req_queue #(
wire [NUM_REQUESTS-1:0][2:0] qual_mem_write;
wire [31:0] qual_pc;
/* verilator lint_off UNUSED */
`DEBUG_BEGIN
reg [NUM_REQUESTS-1:0] updated_valids;
/* verilator lint_on UNUSED */
`DEBUG_END
wire o_empty;

20
hw/rtl/generic_cache/VX_tag_data_access.v
View File

@@ -48,17 +48,13 @@ module VX_tag_data_access #(
input wire is_snp_st1e,
input wire stall_bank_pipe,
// Initial Reading
/* verilator lint_off UNUSED */
// TODO:
`IGNORE_WARNINGS_BEGIN
// TODO: should fix this
input wire[31:0] readaddr_st10,
/* verilator lint_on UNUSED */
// Write/Read Logic
input wire[31:0] writeaddr_st1e,
`IGNORE_WARNINGS_END
input wire valid_req_st1e,
input wire writefill_st1e,
/* verilator lint_off UNUSED */
// TODO:
input wire[31:0] writeaddr_st1e,
/* verilator lint_on UNUSED */
input wire[`WORD_SIZE_RNG] writeword_st1e,
input wire[`DBANK_LINE_WORDS-1:0][31:0] writedata_st1e,
input wire[2:0] mem_write_st1e,
@@ -176,7 +172,7 @@ module VX_tag_data_access #(
wire[`OFFSET_SIZE_RNG] byte_select = writeaddr_st1e[`OFFSET_ADDR_RNG];
wire[`WORD_SELECT_SIZE_RNG] block_offset = writeaddr_st1e[`WORD_SELECT_ADDR_RNG];
/* verilator lint_off UNUSED */
`IGNORE_WARNINGS_BEGIN
wire lw = valid_req_st1e && (mem_read_st1e == `LW_MEM_READ);
wire lb = valid_req_st1e && (mem_read_st1e == `LB_MEM_READ);
wire lh = valid_req_st1e && (mem_read_st1e == `LH_MEM_READ);
@@ -187,14 +183,14 @@ module VX_tag_data_access #(
wire b1 = (byte_select == 1);
wire b2 = (byte_select == 2);
wire b3 = (byte_select == 3);
/* verilator lint_on UNUSED */
`IGNORE_WARNINGS_END
/* verilator lint_off UNUSED */
`DEBUG_BEGIN
wire[31:0] w0 = read_data_st1c[STAGE_1_CYCLES-1][0][31:0];
wire[31:0] w1 = read_data_st1c[STAGE_1_CYCLES-1][1][31:0];
wire[31:0] w2 = read_data_st1c[STAGE_1_CYCLES-1][2][31:0];
wire[31:0] w3 = read_data_st1c[STAGE_1_CYCLES-1][3][31:0];
/* verilator lint_on UNUSED */
`DEBUG_END
/////////////////////// STORE LOGIC ///////////////////