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lkg build rollout with 16cores optimization on arria10

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This commit is contained in:
Blaise Tine
2021-01-24 16:49:22 -08:00
parent 74a687e395
commit 8775f63ec4
55 changed files with 1021 additions and 868 deletions
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100
hw/rtl/libs/VX_skid_buffer.v
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@@ -3,7 +3,9 @@
module VX_skid_buffer #(
parameter DATAW = 1,
parameter PASSTHRU = 0,
parameter NOBACKPRESSURE = 0
parameter NOBACKPRESSURE = 0,
parameter BUFFERED = 0,
parameter FASTRAM = 1
) (
input wire clk,
input wire reset,
@@ -49,44 +51,76 @@ module VX_skid_buffer #(
end else begin
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] buffer;
reg valid_out_r;
reg use_buffer;
wire push = valid_in && ready_in;
always @(posedge clk) begin
if (reset) begin
valid_out_r <= 0;
use_buffer <= 0;
end else begin
if (ready_out) begin
use_buffer <= 0;
if (BUFFERED) begin
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] buffer;
reg valid_out_r;
reg use_buffer;
wire push = valid_in && ready_in;
always @(posedge clk) begin
if (reset) begin
valid_out_r <= 0;
use_buffer <= 0;
end else begin
if (ready_out) begin
use_buffer <= 0;
end
if (push && valid_out_r && !ready_out) begin
assert(!use_buffer);
use_buffer <= 1;
end
if (!valid_out_r || ready_out) begin
valid_out_r <= valid_in || use_buffer;
end
end
if (push && valid_out_r && !ready_out) begin
assert(!use_buffer);
use_buffer <= 1;
end
always @(posedge clk) begin
if (push) begin
buffer <= data_in;
end
if (!valid_out_r || ready_out) begin
valid_out_r <= valid_in || use_buffer;
data_out_r <= use_buffer ? buffer : data_in;
end
end
assign ready_in = !use_buffer;
assign valid_out = valid_out_r;
assign data_out = data_out_r;
end else begin
wire q_push = valid_in && ready_in;
wire q_pop = valid_out && ready_out;
wire q_empty, q_full;
VX_fifo_queue #(
.DATAW (DATAW),
.SIZE (2),
.BUFFERED (BUFFERED),
.FASTRAM (FASTRAM)
) fifo (
.clk (clk),
.reset (reset),
.push (q_push),
.pop (q_pop),
.data_in (data_in),
.data_out (data_out),
.empty (q_empty),
.alm_full (q_full),
`UNUSED_PIN (full),
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (size)
);
assign ready_in = !q_full;
assign valid_out = !q_empty;
end
always @(posedge clk) begin
if (push) begin
buffer <= data_in;
end
if (!valid_out_r || ready_out) begin
data_out_r <= use_buffer ? buffer : data_in;
end
end
assign ready_in = !use_buffer;
assign valid_out = valid_out_r;
assign data_out = data_out_r;
end
endmodule