From 842a202d1968bdb48ca81f51154e50d4142af492 Mon Sep 17 00:00:00 2001 From: "Lyons, Ethan Tyler" Date: Fri, 22 Nov 2019 09:20:20 -0500 Subject: [PATCH] Fixed GPR Stage to be Generic when ASIC is defined --- rtl/VX_gpr_stage.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/rtl/VX_gpr_stage.v b/rtl/VX_gpr_stage.v index 89316cbb..3d556a83 100644 --- a/rtl/VX_gpr_stage.v +++ b/rtl/VX_gpr_stage.v @@ -116,7 +116,7 @@ module VX_gpr_stage ( wire store_curr_real = !delayed_lsu_last_cycle && stall_lsu; - VX_generic_register #(.N(256)) lsu_data( + VX_generic_register #(.N(`NT*32*2)) lsu_data( .clk (clk), .reset(reset), .stall(!store_curr_real), @@ -133,7 +133,7 @@ module VX_gpr_stage ( assign VX_lsu_req.base_address = (delayed_lsu_last_cycle) ? temp_base_address : real_base_address; - VX_generic_register #(.N(77 + `NW_M1 + 65*(1 + `NT))) lsu_reg( + VX_generic_register #(.N(77 + `NW_M1 + 1 + (`NT))) lsu_reg( .clk (clk), .reset(reset), .stall(stall_lsu), @@ -142,7 +142,7 @@ module VX_gpr_stage ( .out ({VX_lsu_req.valid , VX_lsu_req.lsu_pc ,VX_lsu_req.warp_num , VX_lsu_req.offset , VX_lsu_req.mem_read , VX_lsu_req.mem_write , VX_lsu_req.rd , VX_lsu_req.wb }) ); - VX_generic_register #(.N(224 + `NW_M1 + 1 + 65*(`NT))) exec_unit_reg( + VX_generic_register #(.N(224 + `NW_M1 + 1 + (`NT))) exec_unit_reg( .clk (clk), .reset(reset), .stall(stall_rest), @@ -154,7 +154,7 @@ module VX_gpr_stage ( assign VX_exec_unit_req.a_reg_data = real_base_address; assign VX_exec_unit_req.b_reg_data = real_store_data; - VX_generic_register #(.N(68 + `NW_M1 + 1 + 33*(`NT))) gpu_inst_reg( + VX_generic_register #(.N(36 + `NW_M1 + 1 + (`NT))) gpu_inst_reg( .clk (clk), .reset(reset), .stall(stall_rest),