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code refactoring: DRAM => MEM renaming

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Blaise Tine
2021-04-26 00:58:48 -07:00
parent d808aa2735
commit 8410c49f53
38 changed files with 1161 additions and 1161 deletions
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8
hw/rtl/interfaces/VX_perf_memsys_if.v
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@@ -23,10 +23,10 @@ interface VX_perf_memsys_if ();
wire [`PERF_CTR_BITS-1:0] smem_writes;
wire [`PERF_CTR_BITS-1:0] smem_bank_stalls;
wire [`PERF_CTR_BITS-1:0] dram_reads;
wire [`PERF_CTR_BITS-1:0] dram_writes;
wire [`PERF_CTR_BITS-1:0] dram_stalls;
wire [`PERF_CTR_BITS-1:0] dram_latency;
wire [`PERF_CTR_BITS-1:0] mem_reads;
wire [`PERF_CTR_BITS-1:0] mem_writes;
wire [`PERF_CTR_BITS-1:0] mem_stalls;
wire [`PERF_CTR_BITS-1:0] mem_latency;
endinterface