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code refactoring: DRAM => MEM renaming

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This commit is contained in:
Blaise Tine
2021-04-26 00:58:48 -07:00
parent d808aa2735
commit 8410c49f53
38 changed files with 1161 additions and 1161 deletions
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68
hw/rtl/VX_define.vh
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@@ -263,11 +263,11 @@
// Core request tag bits
`define ICORE_TAG_WIDTH (`DBG_CACHE_REQ_MDATAW + `ICORE_TAG_ID_BITS)
// DRAM request data bits
`define IDRAM_LINE_WIDTH (`ICACHE_LINE_SIZE * 8)
// Memory request data bits
`define IMEM_LINE_WIDTH (`ICACHE_LINE_SIZE * 8)
// DRAM byte enable bits
`define IDRAM_BYTEEN_WIDTH `ICACHE_LINE_SIZE
// Memory byte enable bits
`define IMEM_BYTEEN_WIDTH `ICACHE_LINE_SIZE
////////////////////////// Dcache Configurable Knobs //////////////////////////
@@ -275,7 +275,7 @@
`define DCACHE_ID (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 1)
// Block size in bytes
`define DCACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `GLOBAL_BLOCK_SIZE)
`define DCACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `GLOBAL_BLOCK_SIZE)
// Word size in bytes
`define DWORD_SIZE 4
@@ -286,17 +286,17 @@
// Core request tag bits
`define DCORE_TAG_WIDTH (`DBG_CACHE_REQ_MDATAW + `DCORE_TAG_ID_BITS)
// DRAM request data bits
`define DDRAM_LINE_WIDTH (`DCACHE_LINE_SIZE * 8)
// Memory request data bits
`define DMEM_LINE_WIDTH (`DCACHE_LINE_SIZE * 8)
// DRAM request address bits
`define DDRAM_ADDR_WIDTH (32 - `CLOG2(`DCACHE_LINE_SIZE))
// Memory request address bits
`define DMEM_ADDR_WIDTH (32 - `CLOG2(`DCACHE_LINE_SIZE))
// DRAM byte enable bits
`define DDRAM_BYTEEN_WIDTH `DCACHE_LINE_SIZE
// Memory byte enable bits
`define DMEM_BYTEEN_WIDTH `DCACHE_LINE_SIZE
// DRAM request tag bits
`define DDRAM_TAG_WIDTH `DDRAM_ADDR_WIDTH
// Memory request tag bits
`define DMEM_TAG_WIDTH `DMEM_ADDR_WIDTH
// Core request size
`define DNUM_REQUESTS `NUM_THREADS
@@ -332,17 +332,17 @@
// Core request tag bits
`define L2CORE_TAG_WIDTH (`DCORE_TAG_WIDTH + `CLOG2(`NUM_CORES))
// DRAM request data bits
`define L2DRAM_LINE_WIDTH (`L2CACHE_LINE_SIZE * 8)
// Memory request data bits
`define L2MEM_LINE_WIDTH (`L2CACHE_LINE_SIZE * 8)
// DRAM request address bits
`define L2DRAM_ADDR_WIDTH (32 - `CLOG2(`L2CACHE_LINE_SIZE))
// Memory request address bits
`define L2MEM_ADDR_WIDTH (32 - `CLOG2(`L2CACHE_LINE_SIZE))
// DRAM byte enable bits
`define L2DRAM_BYTEEN_WIDTH `L2CACHE_LINE_SIZE
// Memory byte enable bits
`define L2MEM_BYTEEN_WIDTH `L2CACHE_LINE_SIZE
// DRAM request tag bits
`define L2DRAM_TAG_WIDTH (`L2_ENABLE ? `L2DRAM_ADDR_WIDTH : (`XDRAM_TAG_WIDTH+`CLOG2(`NUM_CORES)))
// Memory request tag bits
`define L2MEM_TAG_WIDTH (`L2_ENABLE ? `L2MEM_ADDR_WIDTH : (`XMEM_TAG_WIDTH+`CLOG2(`NUM_CORES)))
////////////////////////// L3cache Configurable Knobs /////////////////////////
@@ -358,30 +358,30 @@
// Core request tag bits
`define L3CORE_TAG_WIDTH (`L2CORE_TAG_WIDTH + `CLOG2(`NUM_CLUSTERS))
// DRAM request data bits
`define L3DRAM_LINE_WIDTH (`L3CACHE_LINE_SIZE * 8)
// Memory request data bits
`define L3MEM_LINE_WIDTH (`L3CACHE_LINE_SIZE * 8)
// DRAM request address bits
`define L3DRAM_ADDR_WIDTH (32 - `CLOG2(`L3CACHE_LINE_SIZE))
// Memory request address bits
`define L3MEM_ADDR_WIDTH (32 - `CLOG2(`L3CACHE_LINE_SIZE))
// DRAM byte enable bits
`define L3DRAM_BYTEEN_WIDTH `L3CACHE_LINE_SIZE
// Memory byte enable bits
`define L3MEM_BYTEEN_WIDTH `L3CACHE_LINE_SIZE
// DRAM request tag bits
`define L3DRAM_TAG_WIDTH (`L3_ENABLE ? `L3DRAM_ADDR_WIDTH : (`L2DRAM_TAG_WIDTH+`CLOG2(`NUM_CLUSTERS)))
// Memory request tag bits
`define L3MEM_TAG_WIDTH (`L3_ENABLE ? `L3MEM_ADDR_WIDTH : (`L2MEM_TAG_WIDTH+`CLOG2(`NUM_CLUSTERS)))
///////////////////////////////////////////////////////////////////////////////
`define VX_DRAM_BYTEEN_WIDTH `L3DRAM_BYTEEN_WIDTH
`define VX_DRAM_ADDR_WIDTH `L3DRAM_ADDR_WIDTH
`define VX_DRAM_LINE_WIDTH `L3DRAM_LINE_WIDTH
`define VX_DRAM_TAG_WIDTH `L3DRAM_TAG_WIDTH
`define VX_MEM_BYTEEN_WIDTH `L3MEM_BYTEEN_WIDTH
`define VX_MEM_ADDR_WIDTH `L3MEM_ADDR_WIDTH
`define VX_MEM_LINE_WIDTH `L3MEM_LINE_WIDTH
`define VX_MEM_TAG_WIDTH `L3MEM_TAG_WIDTH
`define VX_CORE_TAG_WIDTH `L3CORE_TAG_WIDTH
`define VX_CSR_ID_WIDTH `LOG2UP(`NUM_CLUSTERS * `NUM_CORES)
`define TO_FULL_ADDR(x) {x, (32-$bits(x))'(0)}
`define XDRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH+`CLOG2(2))
`define XMEM_TAG_WIDTH (`DMEM_TAG_WIDTH+`CLOG2(2))
`include "VX_types.vh"