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Merge branch 'master' of https://github.gatech.edu/casl/Vortex

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This commit is contained in:
Blaise Tine
2021-09-14 05:11:28 -04:00
parent 7a0b4d7895 4e8293c3e3
commit 83d80c061f
16 changed files with 194 additions and 253 deletions
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26
hw/rtl/libs/VX_dp_ram.v
View File

@@ -5,10 +5,10 @@ module VX_dp_ram #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter OUT_REG = 0,
parameter OUT_REG = 0,
parameter NO_RWCHECK = 0,
parameter ADDRW = $clog2(SIZE),
parameter LUTRAM = 0,
parameter ADDRW = $clog2(SIZE),
parameter INIT_ENABLE = 0,
parameter INIT_FILE = "",
parameter [DATAW-1:0] INIT_VALUE = 0
@@ -17,7 +17,6 @@ module VX_dp_ram #(
input wire [BYTEENW-1:0] wren,
input wire [ADDRW-1:0] waddr,
input wire [DATAW-1:0] wdata,
input wire rden,
input wire [ADDRW-1:0] raddr,
output wire [DATAW-1:0] rdata
);
@@ -47,8 +46,7 @@ module VX_dp_ram #(
if (wren[i])
ram[waddr][i] <= wdata[i * 8 +: 8];
end
if (rden)
rdata_r <= ram[raddr];
rdata_r <= ram[raddr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
@@ -58,13 +56,11 @@ module VX_dp_ram #(
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
if (rden)
rdata_r <= ram[raddr];
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
@@ -103,8 +99,7 @@ module VX_dp_ram #(
if (wren[i])
ram[waddr][i] <= wdata[i * 8 +: 8];
end
if (rden)
rdata_r <= ram[raddr];
rdata_r <= ram[raddr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
@@ -114,13 +109,11 @@ module VX_dp_ram #(
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
if (rden)
rdata_r <= ram[raddr];
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (NO_RWCHECK) begin
if (BYTEENW > 1) begin
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
@@ -185,8 +178,7 @@ module VX_dp_ram #(
if (wren[i])
ram[waddr][i] <= wdata[i * 8 +: 8];
end
if (rden)
rdata_r <= ram[raddr];
rdata_r <= ram[raddr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
@@ -196,13 +188,11 @@ module VX_dp_ram #(
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
if (rden)
rdata_r <= ram[raddr];
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
reg [DATAW-1:0] prev_data;

6
hw/rtl/libs/VX_elastic_buffer.v
View File

@@ -2,10 +2,10 @@
`TRACING_OFF
module VX_elastic_buffer #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter DATAW = 1,
parameter SIZE = 2,
parameter OUT_REG = 0,
parameter LUTRAM = 0
parameter LUTRAM = 0
) (
input wire clk,
input wire reset,

18
hw/rtl/libs/VX_fifo_queue.v
View File

@@ -2,14 +2,14 @@
`TRACING_OFF
module VX_fifo_queue #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter ALM_FULL = (SIZE - 1),
parameter ALM_EMPTY = 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter OUT_REG = 0,
parameter LUTRAM = 1
parameter DATAW = 1,
parameter SIZE = 2,
parameter ALM_FULL = (SIZE - 1),
parameter ALM_EMPTY = 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter OUT_REG = 0,
parameter LUTRAM = 1
) (
input wire clk,
input wire reset,
@@ -163,7 +163,6 @@ module VX_fifo_queue #(
.wren (push),
.waddr (wr_ptr_r),
.wdata (data_in),
.rden (1'b1),
.raddr (rd_ptr_r),
.rdata (data_out)
);
@@ -206,7 +205,6 @@ module VX_fifo_queue #(
.wren (push),
.waddr (wr_ptr_r),
.wdata (data_in),
.rden (1'b1),
.raddr (rd_ptr_n_r),
.rdata (dout)
);

65
hw/rtl/libs/VX_find_first.v
View File

@@ -12,50 +12,33 @@ module VX_find_first #(
output wire [DATAW-1:0] data_o,
output wire valid_o
);
if (N > 1) begin
wire [N-1:0] valid_r;
wire [N-1:0][DATAW-1:0] data_r;
localparam TL = (1 << LOGN) - 1;
localparam TN = (1 << (LOGN+1)) - 1;
for (genvar i = 0; i < N; ++i) begin
assign valid_r[i] = REVERSE ? valid_i[N-1-i] : valid_i[i];
assign data_r[i] = REVERSE ? data_i[N-1-i] : data_i[i];
`IGNORE_WARNINGS_BEGIN
wire [TN-1:0] s_n;
wire [TN-1:0][DATAW-1:0] d_n;
`IGNORE_WARNINGS_END
for (genvar i = 0; i < N; ++i) begin
assign s_n[TL+i] = REVERSE ? valid_i[N-1-i] : valid_i[i];
assign d_n[TL+i] = REVERSE ? data_i[N-1-i] : data_i[i];
end
for (genvar i = TL+N; i < TN; ++i) begin
assign s_n[i] = 0;
assign d_n[i] = 'x;
end
for (genvar j = 0; j < LOGN; ++j) begin
for (genvar i = 0; i < (2**j); ++i) begin
assign s_n[2**j-1+i] = s_n[2**(j+1)-1+i*2] | s_n[2**(j+1)-1+i*2+1];
assign d_n[2**j-1+i] = s_n[2**(j+1)-1+i*2] ? d_n[2**(j+1)-1+i*2] : d_n[2**(j+1)-1+i*2+1];
end
`IGNORE_WARNINGS_BEGIN
wire [2**LOGN-1:0] s_n;
wire [2**LOGN-1:0][DATAW-1:0] d_n;
`IGNORE_WARNINGS_END
for (genvar i = 0; i < LOGN; ++i) begin
if (i == (LOGN-1)) begin
for (genvar j = 0; j < 2**i; ++j) begin
if ((j*2) < (N-1)) begin
assign s_n[2**i-1+j] = valid_r[j*2] | valid_r[j*2+1];
assign d_n[2**i-1+j] = valid_r[j*2] ? data_r[j*2] : data_r[j*2+1];
end
if ((j*2) == (N-1)) begin
assign s_n[2**i-1+j] = valid_r[j*2];
assign d_n[2**i-1+j] = data_r[j*2];
end
if ((j*2) > (N-1)) begin
assign s_n[2**i-1+j] = 0;
assign d_n[2**i-1+j] = 'x;
end
end
end else begin
for (genvar j = 0; j < 2**i; ++j) begin
assign s_n[2**i-1+j] = s_n[2**(i+1)-1+j*2] | s_n[2**(i+1)-1+j*2+1];
assign d_n[2**i-1+j] = s_n[2**(i+1)-1+j*2] ? d_n[2**(i+1)-1+j*2] : d_n[2**(i+1)-1+j*2+1];
end
end
end
end
assign valid_o = s_n[0];
assign data_o = d_n[0];
end else begin
assign valid_o = valid_i;
assign data_o = data_i[0];
end
assign valid_o = s_n[0];
assign data_o = d_n[0];
endmodule
`TRACING_ON

1
hw/rtl/libs/VX_index_buffer.v
View File

@@ -76,7 +76,6 @@ module VX_index_buffer #(
.wren (acquire_slot),
.waddr (write_addr_r),
.wdata (write_data),
.rden (1'b1),
.raddr (read_addr),
.rdata (read_data)
);

2
hw/rtl/libs/VX_skid_buffer.v
View File

@@ -5,7 +5,7 @@ module VX_skid_buffer #(
parameter DATAW = 1,
parameter PASSTHRU = 0,
parameter NOBACKPRESSURE = 0,
parameter OUT_REG = 0
parameter OUT_REG = 0
) (
input wire clk,
input wire reset,

28
hw/rtl/libs/VX_sp_ram.v
View File

@@ -5,10 +5,10 @@ module VX_sp_ram #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter OUT_REG = 0,
parameter OUT_REG = 0,
parameter NO_RWCHECK = 0,
parameter ADDRW = $clog2(SIZE),
parameter LUTRAM = 0,
parameter ADDRW = $clog2(SIZE),
parameter INIT_ENABLE = 0,
parameter INIT_FILE = "",
parameter [DATAW-1:0] INIT_VALUE = 0
@@ -16,8 +16,7 @@ module VX_sp_ram #(
input wire clk,
input wire [ADDRW-1:0] addr,
input wire [BYTEENW-1:0] wren,
input wire [DATAW-1:0] wdata,
input wire rden,
input wire [DATAW-1:0] wdata,
output wire [DATAW-1:0] rdata
);
@@ -47,8 +46,7 @@ module VX_sp_ram #(
if (wren[i])
ram[addr][i] <= wdata[i * 8 +: 8];
end
if (rden)
rdata_r <= ram[addr];
rdata_r <= ram[addr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
@@ -58,13 +56,11 @@ module VX_sp_ram #(
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
if (rden)
rdata_r <= ram[addr];
rdata_r <= ram[addr];
end
end
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
@@ -103,8 +99,7 @@ module VX_sp_ram #(
if (wren[i])
ram[addr][i] <= wdata[i * 8 +: 8];
end
if (rden)
rdata_r <= ram[addr];
rdata_r <= ram[addr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
@@ -114,13 +109,11 @@ module VX_sp_ram #(
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
if (rden)
rdata_r <= ram[addr];
rdata_r <= ram[addr];
end
end
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (NO_RWCHECK) begin
if (BYTEENW > 1) begin
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
@@ -185,8 +178,7 @@ module VX_sp_ram #(
if (wren[i])
ram[addr][i] <= wdata[i * 8 +: 8];
end
if (rden)
rdata_r <= ram[addr];
rdata_r <= ram[addr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
@@ -196,13 +188,11 @@ module VX_sp_ram #(
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
if (rden)
rdata_r <= ram[addr];
rdata_r <= ram[addr];
end
end
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
reg [DATAW-1:0] prev_data;