minor updates
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@@ -37,7 +37,7 @@ module VX_csr_data #(
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reg [`FRM_BITS+`FFG_BITS-1:0] csr_fcsr [`NUM_WARPS-1:0]; // fflags + frm
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always @(posedge clk) begin
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if (cmt_to_csr_if.upd_fflags) begin
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if (cmt_to_csr_if.has_fflags) begin
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csr_fflags[cmt_to_csr_if.warp_num] <= cmt_to_csr_if.fflags;
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csr_fcsr[cmt_to_csr_if.warp_num][`FFG_BITS-1:0] <= cmt_to_csr_if.fflags;
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end
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