Support exec multi-cycle for div/mul
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@@ -6,6 +6,7 @@ module VX_back_end (
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input wire schedule_delay,
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output wire out_mem_delay,
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output wire out_exec_delay,
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output wire gpr_stage_delay,
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VX_jal_response_inter VX_jal_rsp,
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VX_branch_response_inter VX_branch_rsp,
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@@ -32,7 +33,7 @@ assign VX_writeback_inter.wb_warp_num = VX_writeback_temp.wb_warp_num;
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VX_mw_wb_inter VX_mw_wb();
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wire no_slot_mem;
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wire no_slot_mem, no_slot_exec;
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VX_mem_req_inter VX_exe_mem_req();
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@@ -69,6 +70,7 @@ VX_gpr_stage VX_gpr_stage(
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.VX_csr_req (VX_csr_req),
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// End new
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.memory_delay (out_mem_delay),
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.exec_delay (out_exec_delay),
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.gpr_stage_delay (gpr_stage_delay)
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);
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@@ -91,7 +93,9 @@ VX_execute_unit VX_execUnit(
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.VX_exec_unit_req(VX_exec_unit_req),
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.VX_inst_exec_wb (VX_inst_exec_wb),
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.VX_jal_rsp (VX_jal_rsp),
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.VX_branch_rsp (VX_branch_rsp)
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.VX_branch_rsp (VX_branch_rsp),
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.out_delay (out_exec_delay),
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.no_slot_exec (no_slot_exec)
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);
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@@ -113,7 +117,8 @@ VX_writeback VX_wb(
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.VX_csr_wb (VX_csr_wb),
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.VX_writeback_inter(VX_writeback_temp),
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.no_slot_mem (no_slot_mem)
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.no_slot_mem (no_slot_mem),
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.no_slot_exec (no_slot_exec)
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);
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endmodule
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