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fpga fixes

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This commit is contained in:
Blaise Tine
2020-06-27 14:03:20 -07:00
parent d4e006d92d
commit 8302641510
28 changed files with 589 additions and 447 deletions
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151
hw/rtl/libs/VX_mult.v
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@@ -1,16 +1,14 @@
`include "VX_define.vh"
module VX_mult #(
parameter WIDTHA=1,
parameter WIDTHB=1,
parameter WIDTHP=1,
parameter REP="UNSIGNED",
parameter SPEED="MIXED", // "MIXED" or "HIGHEST"
parameter PIPELINE=0,
parameter FORCE_LE="NO"
parameter WIDTHA = 1,
parameter WIDTHB = 1,
parameter WIDTHP = 1,
parameter REP = "UNSIGNED",
parameter PIPELINE = 0
) (
input clock,
input aclr,
input clk,
input reset,
input clken,
input [WIDTHA-1:0] dataa,
@@ -19,102 +17,67 @@ module VX_mult #(
output reg [WIDTHP-1:0] result
);
generate
`ifdef QUARTUS
`ifdef QUARTUS
lpm_mult #(
.LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB),
.LPM_WIDTHP(WIDTHP),
.LPM_REPRESENTATION(REP),
.LPM_PIPELINE(PIPELINE),
.DSP_BLOCK_BALANCING("LOGIC ELEMENTS"),
.MAXIMIZE_SPEED(9)
) quartus_mult (
.clock(clk),
.aclr(reset),
.clken(clken),
.dataa(dataa),
.datab(datab),
.result(result)
);
localparam lpm_speed = (SPEED == "HIGHEST") ? 10 : 5;
`else
wire [WIDTHA-1:0] dataa_pipe_end;
wire [WIDTHB-1:0] datab_pipe_end;
if (FORCE_LE == "YES") begin
lpm_mult #(
.LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB),
.LPM_WIDTHP(WIDTHP),
.LPM_REPRESENTATION(REP),
.LPM_PIPELINE(PIPELINE),
.DSP_BLOCK_BALANCING("LOGIC ELEMENTS"),
.MAXIMIZE_SPEED(lpm_speed)
) quartus_mult (
.clock(clock),
.aclr(aclr),
.clken(clken),
.dataa(dataa),
.datab(datab),
.result(result)
);
end
else begin
lpm_mult#(
.LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB),
.LPM_WIDTHP(WIDTHP),
.LPM_REPRESENTATION(REP),
.LPM_PIPELINE(PIPELINE),
.MAXIMIZE_SPEED(lpm_speed)
) quartus_mult(
.clock(clock),
.aclr(aclr),
.clken(clken),
.dataa(dataa),
.datab(datab),
.result(result)
);
end
if (PIPELINE == 0) begin
assign dataa_pipe_end = dataa;
assign datab_pipe_end = datab;
end else begin
reg [WIDTHA-1:0] dataa_pipe [0:PIPELINE-1];
reg [WIDTHB-1:0] datab_pipe [0:PIPELINE-1];
`else
wire [WIDTHA-1:0] dataa_pipe_end;
wire [WIDTHB-1:0] datab_pipe_end;
if (PIPELINE == 0) begin
assign dataa_pipe_end = dataa;
assign datab_pipe_end = datab;
end else begin
reg [WIDTHA-1:0] dataa_pipe [0:PIPELINE-1];
reg [WIDTHB-1:0] datab_pipe [0:PIPELINE-1];
genvar i;
for (i = 0; i < PIPELINE-1; i++) begin : pipe_stages
always @(posedge clock or posedge aclr) begin
if (aclr) begin
dataa_pipe[i+1] <= 0;
datab_pipe[i+1] <= 0;
end
else if (clken) begin
dataa_pipe[i+1] <= dataa_pipe[i];
datab_pipe[i+1] <= datab_pipe[i];
end
end
end
always @(posedge clock or posedge aclr) begin
if (aclr) begin
dataa_pipe[0] <= 0;
datab_pipe[0] <= 0;
genvar i;
for (i = 0; i < PIPELINE; i++) begin
always @(posedge clk) begin
if (reset) begin
dataa_pipe[i] <= 0;
datab_pipe[i] <= 0;
end
else if (clken) begin
dataa_pipe[0] <= dataa;
datab_pipe[0] <= datab;
if (i == 0) begin
dataa_pipe[0] <= dataa;
datab_pipe[0] <= datab;
end else begin
dataa_pipe[i] <= dataa_pipe[i-1];
datab_pipe[i] <= datab_pipe[i-1];
end
end
end
assign dataa_pipe_end = dataa_pipe[PIPELINE-1];
assign datab_pipe_end = datab_pipe[PIPELINE-1];
end
/* * * * * * * * * * * * * * * * * * * * * * */
/* Do the actual fallback computation here */
/* * * * * * * * * * * * * * * * * * * * * * */
assign dataa_pipe_end = dataa_pipe[PIPELINE-1];
assign datab_pipe_end = datab_pipe[PIPELINE-1];
end
if (REP == "SIGNED") begin
assign result = $signed(dataa_pipe_end) * $signed(datab_pipe_end);
end
else begin
assign result = dataa_pipe_end * datab_pipe_end;
end
if (REP == "SIGNED") begin
assign result = $signed(dataa_pipe_end) * $signed(datab_pipe_end);
end
else begin
assign result = dataa_pipe_end * datab_pipe_end;
end
`endif
endgenerate
`endif
endmodule: VX_mult