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fpga fixes

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This commit is contained in:
Blaise Tine
2020-06-27 14:03:20 -07:00
parent d4e006d92d
commit 8302641510
28 changed files with 589 additions and 447 deletions
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96
hw/rtl/cache/VX_bank.v vendored
View File

@@ -52,6 +52,8 @@ module VX_bank #(
// Snooping request tag width
parameter SNP_REQ_TAG_WIDTH = 0
) (
`SCOPE_SIGNALS_CACHE_IO
input wire clk,
input wire reset,
@@ -153,7 +155,7 @@ module VX_bank #(
`UNUSED_PIN (size)
);
assign snp_req_ready = ~snrq_full;
assign snp_req_ready = !snrq_full;
wire dfpq_pop;
wire dfpq_empty;
@@ -223,7 +225,7 @@ module VX_bank #(
.reqq_full (reqq_full)
);
assign core_req_ready = ~reqq_full;
assign core_req_ready = !reqq_full;
assign reqq_push = (| core_req_valid) && core_req_ready;
wire mrvq_pop;
@@ -291,7 +293,7 @@ module VX_bank #(
wire qual_valid_st0;
wire [`LINE_ADDR_WIDTH-1:0] qual_addr_st0;
wire [`UP(`WORD_SELECT_WIDTH)-1:0] qual_wsel_st0;
wire qual_from_mrvq_st0;
wire qual_is_mrvq_st0;
wire [`WORD_WIDTH-1:0] qual_writeword_st0;
wire [`BANK_LINE_WIDTH-1:0] qual_writedata_st0;
@@ -308,7 +310,7 @@ module VX_bank #(
wire [`BANK_LINE_WIDTH-1:0] writedata_st1 [STAGE_1_CYCLES-1:0];
wire is_snp_st1 [STAGE_1_CYCLES-1:0];
wire snp_invalidate_st1 [STAGE_1_CYCLES-1:0];
wire from_mrvq_st1 [STAGE_1_CYCLES-1:0];
wire is_mrvq_st1 [STAGE_1_CYCLES-1:0];
assign qual_is_fill_st0 = dfpq_pop_unqual;
@@ -352,7 +354,7 @@ module VX_bank #(
reqq_pop_unqual ? reqq_req_writeword_st0 :
0;
assign qual_from_mrvq_st0 = mrvq_pop_unqual;
assign qual_is_mrvq_st0 = mrvq_pop_unqual;
`ifdef DBG_CORE_REQ_INFO
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
@@ -367,8 +369,8 @@ module VX_bank #(
.reset (reset),
.stall (stall_bank_pipe),
.flush (1'b0),
.in ({qual_from_mrvq_st0, qual_is_snp_st0, qual_snp_invalidate_st0, qual_going_to_write_st0, qual_valid_st0, qual_addr_st0, qual_wsel_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}),
.out ({from_mrvq_st1[0] , is_snp_st1[0], snp_invalidate_st1[0], going_to_write_st1[0], valid_st1[0], addr_st1[0], wsel_st1[0], writeword_st1[0], inst_meta_st1[0], is_fill_st1[0], writedata_st1[0]})
.in ({qual_is_mrvq_st0, qual_is_snp_st0, qual_snp_invalidate_st0, qual_going_to_write_st0, qual_valid_st0, qual_addr_st0, qual_wsel_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}),
.out ({is_mrvq_st1[0] , is_snp_st1[0], snp_invalidate_st1[0], going_to_write_st1[0], valid_st1[0], addr_st1[0], wsel_st1[0], writeword_st1[0], inst_meta_st1[0], is_fill_st1[0], writedata_st1[0]})
);
genvar i;
@@ -380,8 +382,8 @@ module VX_bank #(
.reset (reset),
.stall (stall_bank_pipe),
.flush (1'b0),
.in ({from_mrvq_st1[i-1], is_snp_st1[i-1], snp_invalidate_st1[i-1], going_to_write_st1[i-1], valid_st1[i-1], addr_st1[i-1], wsel_st1[i-1], writeword_st1[i-1], inst_meta_st1[i-1], is_fill_st1[i-1], writedata_st1[i-1]}),
.out ({from_mrvq_st1[i] , is_snp_st1[i], snp_invalidate_st1[i], going_to_write_st1[i], valid_st1[i], addr_st1[i], wsel_st1[i], writeword_st1[i], inst_meta_st1[i], is_fill_st1[i], writedata_st1[i]})
.in ({is_mrvq_st1[i-1], is_snp_st1[i-1], snp_invalidate_st1[i-1], going_to_write_st1[i-1], valid_st1[i-1], addr_st1[i-1], wsel_st1[i-1], writeword_st1[i-1], inst_meta_st1[i-1], is_fill_st1[i-1], writedata_st1[i-1]}),
.out ({is_mrvq_st1[i] , is_snp_st1[i], snp_invalidate_st1[i], going_to_write_st1[i], valid_st1[i], addr_st1[i], wsel_st1[i], writeword_st1[i], inst_meta_st1[i], is_fill_st1[i], writedata_st1[i]})
);
end
@@ -404,26 +406,31 @@ module VX_bank #(
wire mrvq_init_ready_state_st1e;
wire miss_add_because_miss;
wire valid_st1e;
wire from_mrvq_st1e;
wire is_mrvq_st1e;
wire mrvq_recover_ready_state_st1e;
wire[`LINE_ADDR_WIDTH-1:0] addr_st1e;
assign from_mrvq_st1e = from_mrvq_st1[STAGE_1_CYCLES-1];
wire tag_valid_st1e;
wire tag_match_st1e;
assign is_mrvq_st1e = is_mrvq_st1[STAGE_1_CYCLES-1];
assign valid_st1e = valid_st1 [STAGE_1_CYCLES-1];
assign is_snp_st1e = is_snp_st1 [STAGE_1_CYCLES-1];
assign snp_invalidate_st1e = snp_invalidate_st1 [STAGE_1_CYCLES-1];
assign addr_st1e = addr_st1[STAGE_1_CYCLES-1];
assign {tag_st1e, mem_rw_st1e, mem_byteen_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1];
assign st2_pending_hazard_st1e = (miss_add_because_miss)
&& ((addr_st2 == addr_st1[STAGE_1_CYCLES-1]) && !is_fill_st2);
&& ((addr_st2 == addr_st1e) && !is_fill_st2);
assign force_request_miss_st1e = (valid_st1e && !from_mrvq_st1e && (mrvq_pending_hazard_st1e || st2_pending_hazard_st1e))
|| (valid_st1e && from_mrvq_st1e && recover_mrvq_state_st2);
assign force_request_miss_st1e = (valid_st1e && !is_mrvq_st1e && (mrvq_pending_hazard_st1e || st2_pending_hazard_st1e))
|| (valid_st1e && is_mrvq_st1e && recover_mrvq_state_st2);
assign mrvq_recover_ready_state_st1e = valid_st1e
&& from_mrvq_st1e
&& is_mrvq_st1e
&& recover_mrvq_state_st2
&& (addr_st2 == addr_st1[STAGE_1_CYCLES-1]);
&& (addr_st2 == addr_st1e);
VX_tag_data_access #(
.CACHE_SIZE (CACHE_SIZE),
@@ -447,7 +454,7 @@ module VX_bank #(
// Actual Read/Write
.valid_req_st1e (valid_st1e),
.writefill_st1e (is_fill_st1[STAGE_1_CYCLES-1]),
.writeaddr_st1e (addr_st1[STAGE_1_CYCLES-1]),
.writeaddr_st1e (addr_st1e),
.wordsel_st1e (wsel_st1[STAGE_1_CYCLES-1]),
.writeword_st1e (writeword_st1[STAGE_1_CYCLES-1]),
.writedata_st1e (writedata_st1[STAGE_1_CYCLES-1]),
@@ -467,7 +474,10 @@ module VX_bank #(
.dirtyb_st1e (dirtyb_st1e),
.fill_saw_dirty_st1e (fill_saw_dirty_st1e),
.snp_to_mrvq_st1e (snp_to_mrvq_st1e),
.mrvq_init_ready_state_st1e(mrvq_init_ready_state_st1e)
.mrvq_init_ready_state_st1e(mrvq_init_ready_state_st1e),
.tag_valid_st1e (tag_valid_st1e),
.tag_match_st1e (tag_match_st1e)
);
`ifdef DBG_CORE_REQ_INFO
@@ -476,8 +486,8 @@ module VX_bank #(
end
`endif
wire qual_valid_st1e_2 = valid_st1e && !is_fill_st1[STAGE_1_CYCLES-1];
wire from_mrvq_st1e_st2 = from_mrvq_st1e;
wire qual_valid_st1e_2 = valid_st1e && !is_fill_st1[STAGE_1_CYCLES-1];
wire is_mrvq_st1e_st2 = is_mrvq_st1e;
wire valid_st2;
wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st2;
@@ -493,7 +503,7 @@ module VX_bank #(
wire is_snp_st2;
wire snp_invalidate_st2;
wire snp_to_mrvq_st2;
wire from_mrvq_st2;
wire is_mrvq_st2;
wire mrvq_init_ready_state_st2;
wire mrvq_recover_ready_state_st2;
wire mrvq_init_ready_state_unqual_st2;
@@ -507,8 +517,8 @@ module VX_bank #(
.reset (reset),
.stall (stall_bank_pipe),
.flush (1'b0),
.in ({mrvq_recover_ready_state_st1e, from_mrvq_st1e_st2, mrvq_init_ready_state_st1e , snp_to_mrvq_st1e, is_snp_st1e, snp_invalidate_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], wsel_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, dirtyb_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}),
.out ({mrvq_recover_ready_state_st2 , from_mrvq_st2 , mrvq_init_ready_state_unqual_st2, snp_to_mrvq_st2 , is_snp_st2 , snp_invalidate_st2, fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , wsel_st2, writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , dirtyb_st2, inst_meta_st2 })
.in ({mrvq_recover_ready_state_st1e, is_mrvq_st1e_st2, mrvq_init_ready_state_st1e , snp_to_mrvq_st1e, is_snp_st1e, snp_invalidate_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1e, wsel_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, dirtyb_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}),
.out ({mrvq_recover_ready_state_st2 , is_mrvq_st2 , mrvq_init_ready_state_unqual_st2, snp_to_mrvq_st2 , is_snp_st2 , snp_invalidate_st2, fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , wsel_st2, writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , dirtyb_st2, inst_meta_st2 })
);
`ifdef DBG_CORE_REQ_INFO
@@ -530,7 +540,7 @@ module VX_bank #(
|| dwbq_push_stall
|| dram_fill_req_stall);
assign recover_mrvq_state_st2 = miss_add && from_mrvq_st2;
assign recover_mrvq_state_st2 = miss_add && is_mrvq_st2;
wire [`LINE_ADDR_WIDTH-1:0] miss_add_addr = addr_st2;
wire [`UP(`WORD_SELECT_WIDTH)-1:0] miss_add_wsel = wsel_st2;
@@ -539,10 +549,10 @@ module VX_bank #(
wire miss_add_is_snp = is_snp_st2;
wire miss_add_snp_invalidate = snp_invalidate_st2;
wire miss_add_from_mrvq = valid_st2 && from_mrvq_st2 && !stall_bank_pipe;
wire miss_add_is_mrvq = valid_st2 && is_mrvq_st2 && !stall_bank_pipe;
assign mrvq_init_ready_state_hazard_st0_st1 = miss_add_unqual && qual_is_fill_st0 && (miss_add_addr == qual_addr_st0 );
assign mrvq_init_ready_state_hazard_st1e_st1 = miss_add_unqual && is_fill_st1[STAGE_1_CYCLES-1] && (miss_add_addr == addr_st1[STAGE_1_CYCLES-1]);
assign mrvq_init_ready_state_hazard_st0_st1 = miss_add_unqual && qual_is_fill_st0 && (miss_add_addr == qual_addr_st0);
assign mrvq_init_ready_state_hazard_st1e_st1 = miss_add_unqual && is_fill_st1[STAGE_1_CYCLES-1] && (miss_add_addr == addr_st1e);
assign mrvq_init_ready_state_st2 = mrvq_init_ready_state_unqual_st2
|| mrvq_init_ready_state_hazard_st0_st1
@@ -564,7 +574,7 @@ module VX_bank #(
// Enqueue
.miss_add (miss_add),
.from_mrvq (miss_add_from_mrvq),
.is_mrvq (miss_add_is_mrvq),
.miss_add_addr (miss_add_addr),
.miss_add_wsel (miss_add_wsel),
.miss_add_data (miss_add_data),
@@ -580,7 +590,7 @@ module VX_bank #(
// Broadcast
.is_fill_st1 (is_fill_st1[STAGE_1_CYCLES-1]),
.fill_addr_st1 (addr_st1[STAGE_1_CYCLES-1]),
.fill_addr_st1 (addr_st1e),
.pending_hazard (mrvq_pending_hazard_st1e),
// Dequeue
@@ -641,7 +651,7 @@ module VX_bank #(
wire dram_fill_req_unqual = miss_add_unqual
&& (!mrvq_init_ready_state_st2
|| (from_mrvq_st2 && !mrvq_recover_ready_state_st2));
|| (is_mrvq_st2 && !mrvq_recover_ready_state_st2));
assign dram_fill_req_valid = dram_fill_req_unqual
&& !(dwbq_push_stall
@@ -649,7 +659,7 @@ module VX_bank #(
|| cwbq_push_stall);
assign dram_fill_req_addr = addr_st2;
assign dram_fill_req_stall = dram_fill_req_unqual && ~dram_fill_req_ready;
assign dram_fill_req_stall = dram_fill_req_unqual && !dram_fill_req_ready;
// Enqueue DRAM writeback request
@@ -706,11 +716,11 @@ module VX_bank #(
end
// when both dwb and snp are asserted, first release the cwb, then release the snp.
assign dram_wb_req_valid = ~dwbq_empty && dwbq_is_dwb_out && (~dwbq_is_snp_out || dwbq_dual_valid_sel == 0);
assign snp_rsp_valid = ~dwbq_empty && dwbq_is_snp_out && (~dwbq_is_dwb_out || dwbq_dual_valid_sel == 1);
assign dram_wb_req_valid = !dwbq_empty && dwbq_is_dwb_out && (~dwbq_is_snp_out || dwbq_dual_valid_sel == 0);
assign snp_rsp_valid = !dwbq_empty && dwbq_is_snp_out && (~dwbq_is_dwb_out || dwbq_dual_valid_sel == 1);
assign dwbq_pop = (dwbq_is_dwb_out && ~dwbq_is_snp_out && dram_wb_req_fire)
|| (dwbq_is_snp_out && ~dwbq_is_dwb_out && snp_rsp_fire)
assign dwbq_pop = (dwbq_is_dwb_out && !dwbq_is_snp_out && dram_wb_req_fire)
|| (dwbq_is_snp_out && !dwbq_is_dwb_out && snp_rsp_fire)
|| (dwbq_is_dwb_out && dwbq_is_snp_out && snp_rsp_fire);
// bank pipeline stall
@@ -745,4 +755,20 @@ module VX_bank #(
end
`endif
`SCOPE_ASSIGN(scope_bank_valid_st0, qual_valid_st0);
`SCOPE_ASSIGN(scope_bank_valid_st1, valid_st1e);
`SCOPE_ASSIGN(scope_bank_valid_st2, valid_st2);
`SCOPE_ASSIGN(scope_bank_is_mrvq_st1, is_mrvq_st1e);
`SCOPE_ASSIGN(scope_bank_miss_st1, miss_st1e);
`SCOPE_ASSIGN(scope_bank_dirty_st1, dirty_st1e);
`SCOPE_ASSIGN(scope_bank_tag_valid_st1, tag_valid_st1e);
`SCOPE_ASSIGN(scope_bank_tag_match_st1, tag_match_st1e);
`SCOPE_ASSIGN(scope_bank_force_miss_st1, force_request_miss_st1e);
`SCOPE_ASSIGN(scope_bank_stall_pipe, stall_bank_pipe);
`SCOPE_ASSIGN(scope_bank_addr_st0, `LINE_TO_BYTE_ADDR(qual_addr_st0, BANK_ID));
`SCOPE_ASSIGN(scope_bank_addr_st1, `LINE_TO_BYTE_ADDR(addr_st1e, BANK_ID));
`SCOPE_ASSIGN(scope_bank_addr_st2, `LINE_TO_BYTE_ADDR(addr_st2, BANK_ID));
endmodule : VX_bank

58
hw/rtl/cache/VX_cache.v vendored
View File

@@ -65,7 +65,7 @@ module VX_cache #(
// Snooping forward tag width
parameter SNP_FWD_TAG_WIDTH = 1
) (
`SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_CACHE_IO
input wire clk,
input wire reset,
@@ -167,6 +167,8 @@ module VX_cache #(
wire [NUM_BANKS-1:0][SNP_REQ_TAG_WIDTH-1:0] per_bank_snp_rsp_tag;
wire [NUM_BANKS-1:0] per_bank_snp_rsp_ready;
`SCOPE_SIGNALS_CACHE_BANK_SELECT
wire snp_req_valid_qual;
wire [`DRAM_ADDR_WIDTH-1:0] snp_req_addr_qual;
wire snp_req_invalidate_qual;
@@ -352,28 +354,30 @@ module VX_cache #(
assign curr_bank_snp_rsp_ready = per_bank_snp_rsp_ready[i];
VX_bank #(
.BANK_ID (i),
.CACHE_ID (CACHE_ID),
.CACHE_SIZE (CACHE_SIZE),
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.CREQ_SIZE (CREQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.DRAM_ENABLE (DRAM_ENABLE),
.WRITE_ENABLE (WRITE_ENABLE),
.SNOOP_FORWARDING (SNOOP_FORWARDING),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS),
.SNP_REQ_TAG_WIDTH (SNP_REQ_TAG_WIDTH)
.BANK_ID (i),
.CACHE_ID (CACHE_ID),
.CACHE_SIZE (CACHE_SIZE),
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.CREQ_SIZE (CREQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.DRAM_ENABLE (DRAM_ENABLE),
.WRITE_ENABLE (WRITE_ENABLE),
.SNOOP_FORWARDING (SNOOP_FORWARDING),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS),
.SNP_REQ_TAG_WIDTH (SNP_REQ_TAG_WIDTH)
) bank (
`SCOPE_SIGNALS_CACHE_BANK_BIND
.clk (clk),
.reset (reset),
// Core request
@@ -452,11 +456,11 @@ module VX_cache #(
);
VX_cache_core_rsp_merge #(
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.NUM_REQUESTS (NUM_REQUESTS),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.NUM_REQUESTS (NUM_REQUESTS),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
) cache_core_rsp_merge (
.clk (clk),
.reset (reset),

4
hw/rtl/cache/VX_cache_dram_req_arb.v vendored
View File

@@ -56,7 +56,7 @@ module VX_cache_dram_req_arb #(
.clk (clk),
.reset (reset),
.dram_req (dram_req_valid && ~dram_req_rw),
.dram_req (dram_req_valid && !dram_req_rw),
.dram_req_addr(dram_req_addr),
.pref_pop (pref_pop),
@@ -91,7 +91,7 @@ module VX_cache_dram_req_arb #(
.dfqq_full (dfqq_full)
);
assign dram_fill_req_ready = ~dfqq_full;
assign dram_fill_req_ready = !dfqq_full;
wire [`BANK_BITS-1:0] dwb_bank;

8
hw/rtl/cache/VX_cache_miss_resrv.v vendored
View File

@@ -23,7 +23,7 @@ module VX_cache_miss_resrv #(
// Miss enqueue
input wire miss_add,
input wire from_mrvq,
input wire is_mrvq,
input wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr,
input wire[`UP(`WORD_SELECT_WIDTH)-1:0] miss_add_wsel,
input wire[`WORD_WIDTH-1:0] miss_add_data,
@@ -102,11 +102,11 @@ module VX_cache_miss_resrv #(
miss_resrv_is_snp_st0,
miss_resrv_snp_invalidate_st0} = metadata_table[dequeue_index];
wire mrvq_push = miss_add && enqueue_possible && !from_mrvq;
wire mrvq_push = miss_add && enqueue_possible && !is_mrvq;
wire mrvq_pop = miss_resrv_pop && dequeue_possible;
wire recover_state = miss_add && from_mrvq;
wire increment_head = !miss_add && from_mrvq;
wire recover_state = miss_add && is_mrvq;
wire increment_head = !miss_add && is_mrvq;
wire update_ready = (|make_ready);

2
hw/rtl/cache/VX_prefetcher.v vendored
View File

@@ -28,7 +28,7 @@ module VX_prefetcher #(
wire current_full;
wire current_empty;
assign current_valid = ~current_empty;
assign current_valid = !current_empty;
wire update_use = ((use_valid == 0) || ((use_valid-1) == 0)) && current_valid;

25
hw/rtl/cache/VX_tag_data_access.v vendored
View File

@@ -50,14 +50,17 @@ module VX_tag_data_access #(
output wire[BANK_LINE_SIZE-1:0] dirtyb_st1e,
output wire fill_saw_dirty_st1e,
output wire snp_to_mrvq_st1e,
output wire mrvq_init_ready_state_st1e
output wire mrvq_init_ready_state_st1e,
output wire tag_valid_st1e,
output wire tag_match_st1e
);
reg read_valid_st1c[STAGE_1_CYCLES-1:0];
reg read_dirty_st1c[STAGE_1_CYCLES-1:0];
reg[BANK_LINE_SIZE-1:0] read_dirtyb_st1c[STAGE_1_CYCLES-1:0];
reg[`TAG_SELECT_BITS-1:0] read_tag_st1c [STAGE_1_CYCLES-1:0];
reg[`BANK_LINE_WIDTH-1:0] read_data_st1c [STAGE_1_CYCLES-1:0];
wire read_valid_st1c[STAGE_1_CYCLES-1:0];
wire read_dirty_st1c[STAGE_1_CYCLES-1:0];
wire[BANK_LINE_SIZE-1:0] read_dirtyb_st1c[STAGE_1_CYCLES-1:0];
wire[`TAG_SELECT_BITS-1:0] read_tag_st1c [STAGE_1_CYCLES-1:0];
wire[`BANK_LINE_WIDTH-1:0] read_data_st1c [STAGE_1_CYCLES-1:0];
wire qual_read_valid_st1;
wire qual_read_dirty_st1;
@@ -135,7 +138,7 @@ module VX_tag_data_access #(
);
end
assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-1] || ~DRAM_ENABLE; // If shared memory, always valid
assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-1] || !DRAM_ENABLE; // If shared memory, always valid
assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-1] && DRAM_ENABLE && WRITE_ENABLE; // Dirty only applies in Dcache
assign use_read_tag_st1e = DRAM_ENABLE ? read_tag_st1c[STAGE_1_CYCLES-1] : writetag_st1e; // Tag is always the same in SM
assign use_read_dirtyb_st1e= read_dirtyb_st1c[STAGE_1_CYCLES-1];
@@ -177,11 +180,8 @@ module VX_tag_data_access #(
wire snoop_hit_no_pending = valid_req_st1e && is_snp_st1e && use_read_valid_st1e && tags_match && (use_read_dirty_st1e || snp_invalidate_st1e) && !force_request_miss_st1e;
wire req_invalid = valid_req_st1e && !is_snp_st1e && !use_read_valid_st1e && !writefill_st1e;
wire req_miss = valid_req_st1e && !is_snp_st1e && use_read_valid_st1e && !writefill_st1e && !tags_match;
wire real_miss = req_invalid || req_miss;
wire force_core_miss = (force_request_miss_st1e && !is_snp_st1e && !writefill_st1e && valid_req_st1e && !real_miss);
wire force_core_miss = (force_request_miss_st1e && !is_snp_st1e && !writefill_st1e && valid_req_st1e && !real_miss);
assign snp_to_mrvq_st1e = valid_req_st1e && is_snp_st1e && force_request_miss_st1e;
// The second term is basically saying always make an entry ready if there's already antoher entry waiting, even if you yourself see a miss
@@ -197,6 +197,9 @@ module VX_tag_data_access #(
assign fill_saw_dirty_st1e = real_writefill && dirty_st1e;
assign invalidate_line = snoop_hit_no_pending;
assign tag_valid_st1e = use_read_valid_st1e;
assign tag_match_st1e = tags_match;
endmodule