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Added Parameterization

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This commit is contained in:
Savan Roshan
2019-11-04 13:20:34 -05:00
parent a28a1c45c1
commit 8264339853
7 changed files with 609 additions and 578 deletions
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96
rtl/cache/VX_d_cache.v vendored
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@@ -14,13 +14,13 @@
//`include "cache_set.v"
module VX_d_cache
#(
/*#(
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 1,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8,
parameter NUM_REQ = 8
)
)*/
(
clk,
rst,
@@ -47,10 +47,10 @@ module VX_d_cache
i_m_ready
);
parameter NUMBER_BANKS = CACHE_BANKS;
localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
//parameter NUMBER_BANKS = `CACHE_BANKS;
//localparam NUM_WORDS_PER_BLOCK = `CACHE_BLOCK / (`CACHE_BANKS*4);
localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / NUMBER_BANKS);
//localparam CACHE_BLOCK_PER_BANK = (`CACHE_BLOCK / `CACHE_BANKS);
localparam CACHE_IDLE = 0; // Idle
localparam SEND_MEM_REQ = 1; // Write back this block into memory
@@ -59,18 +59,18 @@ module VX_d_cache
//parameter cache_entry = 9;
input wire clk, rst;
input wire [NUM_REQ-1:0] i_p_valid;
input wire [NUM_REQ-1:0][31:0] i_p_addr; // FIXME
input wire [NUM_REQ-1:0][31:0] i_p_writedata;
input wire [`NUM_REQ-1:0] i_p_valid;
input wire [`NUM_REQ-1:0][31:0] i_p_addr; // FIXME
input wire [`NUM_REQ-1:0][31:0] i_p_writedata;
input wire i_p_read_or_write; //, i_p_write;
output reg [NUM_REQ-1:0][31:0] o_p_readdata;
output reg [`NUM_REQ-1:0][31:0] o_p_readdata;
output wire o_p_delay;
output reg [31:0] o_m_evict_addr; // Address is xxxxxxxxxxoooobbbyy
output reg [31:0] o_m_read_addr;
output reg o_m_valid;
output reg[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
output reg[`CACHE_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
output reg o_m_read_or_write; //, o_m_write;
input wire[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
input wire[`CACHE_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
input wire i_m_ready;
input wire[2:0] i_p_mem_read;
@@ -78,41 +78,41 @@ module VX_d_cache
// Buffer for final data
reg [NUM_REQ-1:0][31:0] final_data_read;
reg [NUM_REQ-1:0][31:0] new_final_data_read;
wire[NUM_REQ-1:0][31:0] new_final_data_read_Qual;
reg [`NUM_REQ-1:0][31:0] final_data_read;
reg [`NUM_REQ-1:0][31:0] new_final_data_read;
wire[`NUM_REQ-1:0][31:0] new_final_data_read_Qual;
assign o_p_readdata = new_final_data_read_Qual;
wire[NUMBER_BANKS - 1 : 0][NUM_REQ-1:0] thread_track_banks; // Valid thread mask per bank
wire[NUMBER_BANKS - 1 : 0][$clog2(NUM_REQ)-1:0] index_per_bank; // Index of thread each bank will try to service
wire[NUMBER_BANKS - 1 : 0][NUM_REQ-1:0] use_mask_per_bank; // A mask of index_per_bank
wire[NUMBER_BANKS - 1 : 0] valid_per_bank; // Valid request going to each bank
wire[NUMBER_BANKS - 1 : 0][NUM_REQ-1:0] threads_serviced_per_bank; // Bank successfully serviced per bank
wire[`CACHE_BANKS - 1 : 0][`NUM_REQ-1:0] thread_track_banks; // Valid thread mask per bank
wire[`CACHE_BANKS - 1 : 0][$clog2(`NUM_REQ)-1:0] index_per_bank; // Index of thread each bank will try to service
wire[`CACHE_BANKS - 1 : 0][`NUM_REQ-1:0] use_mask_per_bank; // A mask of index_per_bank
wire[`CACHE_BANKS - 1 : 0] valid_per_bank; // Valid request going to each bank
wire[`CACHE_BANKS - 1 : 0][`NUM_REQ-1:0] threads_serviced_per_bank; // Bank successfully serviced per bank
wire[NUMBER_BANKS-1:0][31:0] readdata_per_bank; // Data read from each bank
wire[NUMBER_BANKS-1:0] hit_per_bank; // Whether each bank got a hit or a miss
wire[NUMBER_BANKS-1:0] eviction_wb;
reg[NUMBER_BANKS-1:0] eviction_wb_old;
wire[`CACHE_BANKS-1:0][31:0] readdata_per_bank; // Data read from each bank
wire[`CACHE_BANKS-1:0] hit_per_bank; // Whether each bank got a hit or a miss
wire[`CACHE_BANKS-1:0] eviction_wb;
reg[`CACHE_BANKS-1:0] eviction_wb_old;
wire[NUMBER_BANKS -1 : 0][$clog2(CACHE_WAYS)-1:0] evicted_way_new;
reg [NUMBER_BANKS -1 : 0][$clog2(CACHE_WAYS)-1:0] evicted_way_old;
wire[NUMBER_BANKS -1 : 0][$clog2(CACHE_WAYS)-1:0] way_used;
wire[`CACHE_BANKS -1 : 0][`CACHE_WAY_INDEX-1:0] evicted_way_new;
reg [`CACHE_BANKS -1 : 0][`CACHE_WAY_INDEX-1:0] evicted_way_old;
wire[`CACHE_BANKS -1 : 0][`CACHE_WAY_INDEX-1:0] way_used;
// Internal State
reg [3:0] state;
wire[3:0] new_state;
wire[NUM_REQ-1:0] use_valid; // Valid used throught the code
reg[NUM_REQ-1:0] stored_valid; // Saving the threads still left (bank conflict or bank miss)
wire[NUM_REQ-1:0] new_stored_valid; // New stored valid
wire[`NUM_REQ-1:0] use_valid; // Valid used throught the code
reg[`NUM_REQ-1:0] stored_valid; // Saving the threads still left (bank conflict or bank miss)
wire[`NUM_REQ-1:0] new_stored_valid; // New stored valid
reg[NUMBER_BANKS - 1 : 0][31:0] eviction_addr_per_bank;
reg[`CACHE_BANKS - 1 : 0][31:0] eviction_addr_per_bank;
reg[31:0] miss_addr;
reg[31:0] evict_addr;
@@ -127,39 +127,39 @@ module VX_d_cache
VX_cache_bank_valid #(.NUMBER_BANKS(NUMBER_BANKS)) multip_banks(
VX_cache_bank_valid #(.NUMBER_BANKS(`CACHE_BANKS)) multip_banks(
.i_p_valid (use_valid),
.i_p_addr (i_p_addr),
.thread_track_banks(thread_track_banks)
);
reg[NUM_REQ-1:0] threads_serviced_Qual;
reg[`NUM_REQ-1:0] threads_serviced_Qual;
reg[NUM_REQ-1:0] debug_hit_per_bank_mask[NUMBER_BANKS-1:0];
reg[`NUM_REQ-1:0] debug_hit_per_bank_mask[`CACHE_BANKS-1:0];
genvar bid;
for (bid = 0; bid < NUMBER_BANKS; bid=bid+1)
for (bid = 0; bid < `CACHE_BANKS; bid=bid+1)
begin
wire[NUM_REQ-1:0] use_threads_track_banks = thread_track_banks[bid];
wire[$clog2(NUM_REQ)-1:0] use_thread_index = index_per_bank[bid];
wire[`NUM_REQ-1:0] use_threads_track_banks = thread_track_banks[bid];
wire[$clog2(`NUM_REQ)-1:0] use_thread_index = index_per_bank[bid];
wire use_write_final_data = hit_per_bank[bid];
wire[31:0] use_data_final_data = readdata_per_bank[bid];
VX_priority_encoder_w_mask #(.N(NUM_REQ)) choose_thread(
VX_priority_encoder_w_mask #(.N(`NUM_REQ)) choose_thread(
.valids(use_threads_track_banks),
.mask (use_mask_per_bank[bid]),
.index (index_per_bank[bid]),
.found (valid_per_bank[bid])
);
assign debug_hit_per_bank_mask[bid] = {NUM_REQ{hit_per_bank[bid]}};
assign debug_hit_per_bank_mask[bid] = {`NUM_REQ{hit_per_bank[bid]}};
assign threads_serviced_per_bank[bid] = use_mask_per_bank[bid] & debug_hit_per_bank_mask[bid];
end
integer test_bid;
always @(*) begin
new_final_data_read = 0;
for (test_bid=0; test_bid < NUMBER_BANKS; test_bid=test_bid+1)
for (test_bid=0; test_bid < `CACHE_BANKS; test_bid=test_bid+1)
begin
if (hit_per_bank[test_bid]) begin
new_final_data_read[index_per_bank[test_bid]] = readdata_per_bank[test_bid];
@@ -168,7 +168,7 @@ module VX_d_cache
end
wire[NUMBER_BANKS - 1 : 0] detect_bank_miss;
wire[`CACHE_BANKS - 1 : 0] detect_bank_miss;
assign threads_serviced_Qual = threads_serviced_per_bank[0] | threads_serviced_per_bank[1] |
threads_serviced_per_bank[2] | threads_serviced_per_bank[3] |
threads_serviced_per_bank[4] | threads_serviced_per_bank[5] |
@@ -184,7 +184,7 @@ module VX_d_cache
genvar tid;
for (tid = 0; tid < NUM_REQ; tid =tid+1)
for (tid = 0; tid < `NUM_REQ; tid =tid+1)
begin
assign new_final_data_read_Qual[tid] = threads_serviced_Qual[tid] ? new_final_data_read[tid] : final_data_read[tid];
end
@@ -197,12 +197,12 @@ module VX_d_cache
assign o_p_delay = delay;
wire[NUMBER_BANKS - 1 : 0][$clog2(NUM_REQ)-1:0] send_index_to_bank = index_per_bank;
wire[`CACHE_BANKS - 1 : 0][$clog2(`NUM_REQ)-1:0] send_index_to_bank = index_per_bank;
wire[$clog2(NUMBER_BANKS)-1:0] miss_bank_index;
wire[`CACHE_WAY_INDEX-1:0] miss_bank_index;
wire miss_found;
VX_generic_priority_encoder #(.N(NUMBER_BANKS)) get_miss_index
VX_generic_priority_encoder #(.N(`CACHE_BANKS)) get_miss_index
(
.valids(detect_bank_miss),
.index (miss_bank_index),
@@ -258,7 +258,7 @@ module VX_d_cache
genvar bank_id;
generate
for (bank_id = 0; bank_id < NUMBER_BANKS; bank_id = bank_id + 1)
for (bank_id = 0; bank_id < `CACHE_BANKS; bank_id = bank_id + 1)
begin
wire[31:0] bank_addr = (state == SEND_MEM_REQ) ? evict_addr :
(state == RECIV_MEM_RSP) ? miss_addr :
@@ -280,12 +280,12 @@ module VX_d_cache
((state == SEND_MEM_REQ)) ? 1'b0 :
normal_valid_in;
VX_Cache_Bank #(
/*VX_Cache_Bank #(
.CACHE_SIZE(CACHE_SIZE),
.CACHE_WAYS(CACHE_WAYS),
.CACHE_BLOCK(CACHE_BLOCK),
.CACHE_BANKS(CACHE_BANKS)) bank_structure
(
.CACHE_BANKS(CACHE_BANKS)) bank_structure*/
VX_Cache_Bank bank_structure(
.clk (clk),
.rst (rst),
.state (state),