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added config.vh

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This commit is contained in:
Blaise Tine
2020-04-16 07:49:19 -04:00
parent c913e542e9
commit 81745f08c9
109 changed files with 1426 additions and 1544 deletions
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10
hw/rtl/shared_memory/VX_bank_valids.v
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@@ -1,4 +1,4 @@
`include "../VX_define.v"
`include "../VX_define.vh"
// Converts in_valids to bank_valids
module VX_bank_valids
@@ -7,16 +7,16 @@ module VX_bank_valids
parameter BITS_PER_BANK = 3
)
(
input wire[`NT_M1:0] in_valids,
input wire[`NT_M1:0][31:0] in_addr,
output reg[NB:0][`NT_M1:0] bank_valids
input wire[`NUM_THREADS-1:0] in_valids,
input wire[`NUM_THREADS-1:0][31:0] in_addr,
output reg[NB:0][`NUM_THREADS-1:0] bank_valids
);
integer i, j;
always@(*) begin
for(j = 0; j <= NB; j = j+1 ) begin
for(i = 0; i <= `NT_M1; i = i+1) begin
for(i = 0; i < `NUM_THREADS; i = i+1) begin
if(in_valids[i]) begin
if(in_addr[i][(2+BITS_PER_BANK-1):2] == j[BITS_PER_BANK-1:0]) begin
bank_valids[j][i] = 1'b1;

30
hw/rtl/shared_memory/VX_priority_encoder_sm.v
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@@ -1,4 +1,4 @@
`include "../VX_define.v"
`include "../VX_define.vh"
module VX_priority_encoder_sm
#(
@@ -10,9 +10,9 @@ module VX_priority_encoder_sm
//INPUTS
input wire clk,
input wire reset,
input wire[`NT_M1:0] in_valid,
input wire[`NT_M1:0][31:0] in_address,
input wire[`NT_M1:0][31:0] in_data,
input wire[`NUM_THREADS-1:0] in_valid,
input wire[`NUM_THREADS-1:0][31:0] in_address,
input wire[`NUM_THREADS-1:0][31:0] in_data,
// OUTPUTS
// To SM Module
output reg[NB:0] out_valid,
@@ -20,16 +20,16 @@ module VX_priority_encoder_sm
output reg[NB:0][31:0] out_data,
// To Processor
output wire[NB:0][`CLOG2(NUM_REQ) - 1:0] req_num,
output wire[NB:0][`LOG2UP(NUM_REQ) - 1:0] req_num,
output reg stall,
output wire send_data // Finished all of the requests
);
reg[`NT_M1:0] left_requests;
reg[`NT_M1:0] serviced;
reg[`NUM_THREADS-1:0] left_requests;
reg[`NUM_THREADS-1:0] serviced;
wire[`NT_M1:0] use_valid;
wire[`NUM_THREADS-1:0] use_valid;
wire requests_left = (|left_requests);
@@ -37,7 +37,7 @@ module VX_priority_encoder_sm
assign use_valid = (requests_left) ? left_requests : in_valid;
wire[NB:0][`NT_M1:0] bank_valids;
wire[NB:0][`NUM_THREADS-1:0] bank_valids;
VX_bank_valids #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_bank_valid(
.in_valids(use_valid),
.in_addr(in_address),
@@ -49,9 +49,9 @@ module VX_priority_encoder_sm
genvar curr_bank;
generate
for (curr_bank = 0; curr_bank <= NB; curr_bank = curr_bank + 1) begin : countones_blocks
wire[`CLOG2(`NT):0] num_valids;
wire[`LOG2UP(`NUM_THREADS):0] num_valids;
VX_countones #(.N(`NT)) valids_counter (
VX_countones #(.N(`NUM_THREADS)) valids_counter (
.valids(bank_valids[curr_bank]),
.count (num_valids)
);
@@ -64,7 +64,7 @@ module VX_priority_encoder_sm
assign stall = (|more_than_one_valid);
assign send_data = (!stall) && (|in_valid); // change
wire[NB:0][(`CLOG2(NUM_REQ)) - 1:0] internal_req_num;
wire[NB:0][(`LOG2UP(NUM_REQ)) - 1:0] internal_req_num;
wire[NB:0] internal_out_valid;
@@ -96,11 +96,11 @@ module VX_priority_encoder_sm
assign out_valid = internal_out_valid;
wire[`NT_M1:0] serviced_qual = in_valid & (serviced);
wire[`NUM_THREADS-1:0] serviced_qual = in_valid & (serviced);
wire[`NT_M1:0] new_left_requests = (left_requests == 0) ? (in_valid & ~serviced_qual) : (left_requests & ~ serviced_qual);
wire[`NUM_THREADS-1:0] new_left_requests = (left_requests == 0) ? (in_valid & ~serviced_qual) : (left_requests & ~ serviced_qual);
// wire[`NT_M1:0] new_left_requests = left_requests & ~(serviced_qual);
// wire[`NUM_THREADS-1:0] new_left_requests = left_requests & ~(serviced_qual);
always @(posedge clk, posedge reset) begin
if (reset) begin

35
hw/rtl/shared_memory/VX_shared_memory.v
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@@ -1,4 +1,4 @@
`include "../VX_define.v"
`include "../VX_define.vh"
module VX_shared_memory
#(
@@ -21,14 +21,14 @@ module VX_shared_memory
//INPUTS
input wire clk,
input wire reset,
input wire[`NT_M1:0] in_valid,
input wire[`NT_M1:0][31:0] in_address,
input wire[`NT_M1:0][31:0] in_data,
input wire[`NUM_THREADS-1:0] in_valid,
input wire[`NUM_THREADS-1:0][31:0] in_address,
input wire[`NUM_THREADS-1:0][31:0] in_data,
input wire[2:0] mem_read,
input wire[2:0] mem_write,
//OUTPUTS
output wire[`NT_M1:0] out_valid,
output wire[`NT_M1:0][31:0] out_data,
output wire[`NUM_THREADS-1:0] out_valid,
output wire[`NUM_THREADS-1:0][31:0] out_data,
output wire stall
);
@@ -39,8 +39,8 @@ reg[SM_BANKS - 1:0][31:0] temp_address;
reg[SM_BANKS - 1:0][31:0] temp_in_data;
reg[SM_BANKS - 1:0] temp_in_valid;
reg[`NT_M1:0] temp_out_valid;
reg[`NT_M1:0][31:0] temp_out_data;
reg[`NUM_THREADS-1:0] temp_out_valid;
reg[`NUM_THREADS-1:0][31:0] temp_out_data;
//reg [NB:0][6:0] block_addr;
//reg [NB:0][3:0][31:0] block_wdata;
@@ -54,20 +54,19 @@ reg [SM_BANKS - 1:0][SM_LOG_WORDS_PER_READ-1:0] block_we;
wire send_data;
//reg[NB:0][1:0] req_num;
reg[SM_BANKS - 1:0][`CLOG2(NUM_REQ) - 1:0] req_num; // not positive about this
wire [`NT_M1:0] orig_in_valid;
reg[SM_BANKS - 1:0][`LOG2UP(NUM_REQ) - 1:0] req_num; // not positive about this
wire [`NUM_THREADS-1:0] orig_in_valid;
genvar f;
generate
for(f = 0; f < `NT; f = f+1) begin : orig_in_valid_setup
assign orig_in_valid[f] = in_valid[f];
end
generate
for(f = 0; f < `NUM_THREADS; f = f+1) begin : orig_in_valid_setup
assign orig_in_valid[f] = in_valid[f];
end
assign out_valid = send_data ? temp_out_valid : 0;
assign out_data = send_data ? temp_out_data : 0;
endgenerate
assign out_valid = send_data ? temp_out_valid : 0;
assign out_data = send_data ? temp_out_data : 0;
endgenerate
//VX_priority_encoder_sm #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_priority_encoder_sm(