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added config.vh

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This commit is contained in:
Blaise Tine
2020-04-16 07:49:19 -04:00
parent c913e542e9
commit 81745f08c9
109 changed files with 1426 additions and 1544 deletions
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4
hw/rtl/interfaces/VX_branch_response_inter.v
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@@ -1,5 +1,5 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_BRANCH_RSP
@@ -9,7 +9,7 @@ interface VX_branch_response_inter ();
wire valid_branch;
wire branch_dir;
wire[31:0] branch_dest;
wire[`NW_M1:0] branch_warp_num;
wire[`NW_BITS-1:0] branch_warp_num;
endinterface

6
hw/rtl/interfaces/VX_csr_req_inter.v
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@@ -1,5 +1,5 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_CSR_REQ
@@ -7,8 +7,8 @@
interface VX_csr_req_inter ();
wire[`NT_M1:0] valid;
wire[`NW_M1:0] warp_num;
wire[`NUM_THREADS-1:0] valid;
wire[`NW_BITS-1:0] warp_num;
wire[4:0] rd;
wire[1:0] wb;
wire[4:0] alu_op;

14
hw/rtl/interfaces/VX_csr_wb_inter.v
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@@ -1,5 +1,5 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_CSR_WB_REQ
@@ -7,15 +7,13 @@
interface VX_csr_wb_inter ();
wire[`NT_M1:0] valid;
wire[`NW_M1:0] warp_num;
wire[4:0] rd;
wire[1:0] wb;
wire[`NUM_THREADS-1:0] valid;
wire[`NW_BITS-1:0] warp_num;
wire[4:0] rd;
wire[1:0] wb;
wire[`NT_M1:0][31:0] csr_result;
wire[`NUM_THREADS-1:0][31:0] csr_result;
endinterface
`endif

8
hw/rtl/interfaces/VX_dcache_request_inter.v
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@@ -1,5 +1,5 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_DCACHE_REQ
@@ -7,11 +7,11 @@
interface VX_dcache_request_inter ();
wire[`NT_M1:0][31:0] out_cache_driver_in_address;
wire[`NUM_THREADS-1:0][31:0] out_cache_driver_in_address;
wire[2:0] out_cache_driver_in_mem_read;
wire[2:0] out_cache_driver_in_mem_write;
wire[`NT_M1:0] out_cache_driver_in_valid;
wire[`NT_M1:0][31:0] out_cache_driver_in_data;
wire[`NUM_THREADS-1:0] out_cache_driver_in_valid;
wire[`NUM_THREADS-1:0][31:0] out_cache_driver_in_data;
endinterface

4
hw/rtl/interfaces/VX_dcache_response_inter.v
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@@ -1,5 +1,5 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_DCACHE_RSP
@@ -7,7 +7,7 @@
interface VX_dcache_response_inter ();
wire[`NT_M1:0][31:0] in_cache_driver_out_data;
wire[`NUM_THREADS-1:0][31:0] in_cache_driver_out_data;
wire delay;
endinterface

2
hw/rtl/interfaces/VX_dram_req_rsp_inter.v
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@@ -1,5 +1,5 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_DRAM_REQ_RSP_INTER

10
hw/rtl/interfaces/VX_exec_unit_req_inter.v
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@@ -1,5 +1,5 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_EXE_UNIT_REQ_INTER
@@ -8,8 +8,8 @@
interface VX_exec_unit_req_inter ();
// Meta
wire[`NT_M1:0] valid;
wire[`NW_M1:0] warp_num;
wire[`NUM_THREADS-1:0] valid;
wire[`NW_BITS-1:0] warp_num;
wire[31:0] curr_PC;
wire[31:0] PC_next;
@@ -18,8 +18,8 @@ interface VX_exec_unit_req_inter ();
wire[1:0] wb;
// Data and alu op
wire[`NT_M1:0][31:0] a_reg_data;
wire[`NT_M1:0][31:0] b_reg_data;
wire[`NUM_THREADS-1:0][31:0] a_reg_data;
wire[`NUM_THREADS-1:0][31:0] b_reg_data;
wire[4:0] alu_op;
wire[4:0] rs1;
wire[4:0] rs2;

6
hw/rtl/interfaces/VX_frE_to_bckE_req_inter.v
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@@ -1,5 +1,5 @@
`include "VX_define.v"
`include "VX_define.vh"
`ifndef VX_FrE_to_BE_INTER
@@ -30,8 +30,8 @@ interface VX_frE_to_bckE_req_inter ();
wire jal;
wire[31:0] jal_offset;
wire[31:0] PC_next;
wire[`NT_M1:0] valid;
wire[`NW_M1:0] warp_num;
wire[`NUM_THREADS-1:0] valid;
wire[`NW_BITS-1:0] warp_num;
// GPGPU stuff
wire is_wspawn;

4
hw/rtl/interfaces/VX_gpr_clone_inter.v
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@@ -1,5 +1,5 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_GPR_CLONE_INTER
@@ -9,7 +9,7 @@
interface VX_gpr_clone_inter ();
/* verilator lint_off UNUSED */
wire is_clone;
wire[`NW_M1:0] warp_num;
wire[`NW_BITS-1:0] warp_num;
/* verilator lint_on UNUSED */
endinterface

6
hw/rtl/interfaces/VX_gpr_data_inter.v
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@@ -1,13 +1,13 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_gpr_data_INTER
`define VX_gpr_data_INTER
interface VX_gpr_data_inter ();
wire[`NT_M1:0][31:0] a_reg_data;
wire[`NT_M1:0][31:0] b_reg_data;
wire[`NUM_THREADS-1:0][31:0] a_reg_data;
wire[`NUM_THREADS-1:0][31:0] b_reg_data;
endinterface

2
hw/rtl/interfaces/VX_gpr_jal_inter.v
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@@ -1,4 +1,4 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_GPR_JAL_INTER
`define VX_GPR_JAL_INTER

4
hw/rtl/interfaces/VX_gpr_read_inter.v
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@@ -1,4 +1,4 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_GPR_READ
`define VX_GPR_READ
@@ -8,7 +8,7 @@ interface VX_gpr_read_inter ();
wire[4:0] rs1;
wire[4:0] rs2;
wire[`NW_M1:0] warp_num;
wire[`NW_BITS-1:0] warp_num;
endinterface

6
hw/rtl/interfaces/VX_gpr_wspawn_inter.v
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@@ -1,4 +1,4 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_GPR_WSPAWN_INTER
`define VX_GPR_WSPAWN_INTER
@@ -7,8 +7,8 @@
interface VX_gpr_wspawn_inter ();
/* verilator lint_off UNUSED */
wire is_wspawn;
wire[`NW_M1:0] which_wspawn;
// wire[`NW_M1:0] warp_num;
wire[`NW_BITS-1:0] which_wspawn;
// wire[`NW_BITS-1:0] warp_num;
/* verilator lint_on UNUSED */
endinterface

6
hw/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v
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@@ -1,6 +1,6 @@
`include "../generic_cache/VX_cache_config.v"
`include "../generic_cache/VX_cache_config.vh"
`ifndef VX_GPU_DRAM_DCACHE_REQ
@@ -8,7 +8,7 @@
interface VX_gpu_dcache_dram_req_inter
#(
parameter BANK_LINE_SIZE_WORDS = 2
parameter BANK_LINE_WORDS = 2
)
();
@@ -18,7 +18,7 @@ interface VX_gpu_dcache_dram_req_inter
wire dram_req_read;
wire [31:0] dram_req_addr;
wire [31:0] dram_req_size;
wire [BANK_LINE_SIZE_WORDS-1:0][31:0] dram_req_data;
wire [BANK_LINE_WORDS-1:0][31:0] dram_req_data;
// Snoop
wire dram_because_of_snp;

6
hw/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v
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@@ -1,7 +1,7 @@
`include "../generic_cache/VX_cache_config.v"
`include "../generic_cache/VX_cache_config.vh"
`ifndef VX_GPU_DRAM_DCACHE_RES
@@ -9,13 +9,13 @@
interface VX_gpu_dcache_dram_res_inter
#(
parameter BANK_LINE_SIZE_WORDS = 2
parameter BANK_LINE_WORDS = 2
)
();
// DRAM Rsponse
wire dram_fill_rsp;
wire [31:0] dram_fill_rsp_addr;
wire [BANK_LINE_SIZE_WORDS-1:0][31:0] dram_fill_rsp_data;
wire [BANK_LINE_WORDS-1:0][31:0] dram_fill_rsp_data;
endinterface

4
hw/rtl/interfaces/VX_gpu_dcache_req_inter.v
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@@ -1,6 +1,6 @@
`include "../generic_cache/VX_cache_config.v"
`include "../generic_cache/VX_cache_config.vh"
`ifndef VX_GPU_DCACHE_REQ
@@ -20,7 +20,7 @@ interface VX_gpu_dcache_req_inter
wire [NUMBER_REQUESTS-1:0][2:0] core_req_mem_write;
wire [4:0] core_req_rd;
wire [NUMBER_REQUESTS-1:0][1:0] core_req_wb;
wire [`NW_M1:0] core_req_warp_num;
wire [`NW_BITS-1:0] core_req_warp_num;
wire [31:0] core_req_pc;
// Can't WB

4
hw/rtl/interfaces/VX_gpu_dcache_res_inter.v
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@@ -1,6 +1,6 @@
`include "../generic_cache/VX_cache_config.v"
`include "../generic_cache/VX_cache_config.vh"
`ifndef VX_GPU_DCACHE_RES
@@ -16,7 +16,7 @@ interface VX_gpu_dcache_res_inter
wire [NUMBER_REQUESTS-1:0] core_wb_valid;
wire [4:0] core_wb_req_rd;
wire [1:0] core_wb_req_wb;
wire [`NW_M1:0] core_wb_warp_num;
wire [`NW_BITS-1:0] core_wb_warp_num;
wire [NUMBER_REQUESTS-1:0][31:0] core_wb_readdata;
wire [NUMBER_REQUESTS-1:0][31:0] core_wb_pc;

2
hw/rtl/interfaces/VX_gpu_dcache_snp_req_inter.v
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@@ -1,7 +1,7 @@
`include "../generic_cache/VX_cache_config.v"
`include "../generic_cache/VX_cache_config.vh"
`ifndef VX_GPU_SNP_REQ

8
hw/rtl/interfaces/VX_gpu_inst_req_inter.v
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@@ -1,4 +1,4 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_GPU_INST_REQ_IN
@@ -6,8 +6,8 @@
interface VX_gpu_inst_req_inter();
wire[`NT_M1:0] valid;
wire[`NW_M1:0] warp_num;
wire[`NUM_THREADS-1:0] valid;
wire[`NW_BITS-1:0] warp_num;
wire is_wspawn;
wire is_tmc;
wire is_split;
@@ -16,7 +16,7 @@ interface VX_gpu_inst_req_inter();
wire[31:0] pc_next;
wire[`NT_M1:0][31:0] a_reg_data;
wire[`NUM_THREADS-1:0][31:0] a_reg_data;
wire[31:0] rd2;

2
hw/rtl/interfaces/VX_gpu_snp_req_rsp.v
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@@ -1,4 +1,4 @@
`include "../generic_cache/VX_cache_config.v"
`include "../generic_cache/VX_cache_config.vh"
`ifndef VX_GPU_SNP_REQ_RSP

2
hw/rtl/interfaces/VX_icache_request_inter.v
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@@ -1,5 +1,5 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_ICACHE_REQ

2
hw/rtl/interfaces/VX_icache_response_inter.v
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@@ -1,4 +1,4 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_ICACHE_RSP

8
hw/rtl/interfaces/VX_inst_exec_wb_inter.v
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@@ -1,5 +1,5 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_EXEC_UNIT_WB_INST_INTER
@@ -7,12 +7,12 @@
interface VX_inst_exec_wb_inter ();
wire[`NT_M1:0][31:0] alu_result;
wire[`NUM_THREADS-1:0][31:0] alu_result;
wire[31:0] exec_wb_pc;
wire[4:0] rd;
wire[1:0] wb;
wire[`NT_M1:0] wb_valid;
wire[`NW_M1:0] wb_warp_num;
wire[`NUM_THREADS-1:0] wb_valid;
wire[`NW_BITS-1:0] wb_warp_num;
endinterface

8
hw/rtl/interfaces/VX_inst_mem_wb_inter.v
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@@ -1,5 +1,5 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_MEM_WB_INST_INTER
@@ -7,12 +7,12 @@
interface VX_inst_mem_wb_inter ();
wire[`NT_M1:0][31:0] loaded_data;
wire[`NUM_THREADS-1:0][31:0] loaded_data;
wire[31:0] mem_wb_pc;
wire[4:0] rd;
wire[1:0] wb;
wire[`NT_M1:0] wb_valid;
wire[`NW_M1:0] wb_warp_num;
wire[`NUM_THREADS-1:0] wb_valid;
wire[`NW_BITS-1:0] wb_warp_num;
endinterface

6
hw/rtl/interfaces/VX_inst_meta_inter.v
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@@ -1,4 +1,4 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_F_D_INTER
@@ -7,8 +7,8 @@
interface VX_inst_meta_inter ();
wire[31:0] instruction;
wire[31:0] inst_pc;
wire[`NW_M1:0] warp_num;
wire[`NT_M1:0] valid;
wire[`NW_BITS-1:0] warp_num;
wire[`NUM_THREADS-1:0] valid;
endinterface

4
hw/rtl/interfaces/VX_jal_response_inter.v
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@@ -1,5 +1,5 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_JAL_RSP
@@ -9,7 +9,7 @@ interface VX_jal_response_inter ();
wire jal;
wire[31:0] jal_dest;
wire[`NW_M1:0] jal_warp_num;
wire[`NW_BITS-1:0] jal_warp_num;
endinterface

4
hw/rtl/interfaces/VX_join_inter.v
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@@ -1,5 +1,5 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_JOIN_INTER
@@ -8,7 +8,7 @@
interface VX_join_inter ();
wire is_join;
wire[`NW_M1:0] join_warp_num;
wire[`NW_BITS-1:0] join_warp_num;
endinterface

10
hw/rtl/interfaces/VX_lsu_req_inter.v
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@@ -1,5 +1,5 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_LSU_REQ_INTER
@@ -7,11 +7,11 @@
interface VX_lsu_req_inter ();
wire[`NT_M1:0] valid;
wire[`NUM_THREADS-1:0] valid;
wire[31:0] lsu_pc;
wire[`NW_M1:0] warp_num;
wire[`NT_M1:0][31:0] store_data;
wire[`NT_M1:0][31:0] base_address; // A reg data
wire[`NW_BITS-1:0] warp_num;
wire[`NUM_THREADS-1:0][31:0] store_data;
wire[`NUM_THREADS-1:0][31:0] base_address; // A reg data
wire[31:0] offset; // itype_immed
wire[2:0] mem_read;
wire[2:0] mem_write;

10
hw/rtl/interfaces/VX_mem_req_inter.v
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@@ -1,4 +1,4 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_MEM_REQ_IN
@@ -6,20 +6,20 @@
interface VX_mem_req_inter ();
wire[`NT_M1:0][31:0] alu_result;
wire[`NUM_THREADS-1:0][31:0] alu_result;
wire[2:0] mem_read;
wire[2:0] mem_write;
wire[4:0] rd;
wire[1:0] wb;
wire[4:0] rs1;
wire[4:0] rs2;
wire[`NT_M1:0][31:0] rd2;
wire[`NUM_THREADS-1:0][31:0] rd2;
wire[31:0] PC_next;
wire[31:0] curr_PC;
wire[31:0] branch_offset;
wire[2:0] branch_type;
wire[`NT_M1:0] valid;
wire[`NW_M1:0] warp_num;
wire[`NUM_THREADS-1:0] valid;
wire[`NW_BITS-1:0] warp_num;
endinterface

10
hw/rtl/interfaces/VX_mw_wb_inter.v
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@@ -1,5 +1,5 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_MW_WB_INTER
@@ -7,13 +7,13 @@
interface VX_mw_wb_inter ();
wire[`NT_M1:0][31:0] alu_result;
wire[`NT_M1:0][31:0] mem_result;
wire[`NUM_THREADS-1:0][31:0] alu_result;
wire[`NUM_THREADS-1:0][31:0] mem_result;
wire[4:0] rd;
wire[1:0] wb;
wire[31:0] PC_next;
wire[`NT_M1:0] valid;
wire [`NW_M1:0] warp_num;
wire[`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
endinterface

16
hw/rtl/interfaces/VX_warp_ctl_inter.v
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@@ -1,5 +1,5 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_WARP_CTL_INTER
@@ -7,26 +7,26 @@
interface VX_warp_ctl_inter ();
wire[`NW_M1:0] warp_num;
wire[`NW_BITS-1:0] warp_num;
wire change_mask;
wire[`NT_M1:0] thread_mask;
wire[`NUM_THREADS-1:0] thread_mask;
wire wspawn;
wire[31:0] wspawn_pc;
wire[`NW-1:0] wspawn_new_active;
wire[`NUM_WARPS-1:0] wspawn_new_active;
wire ebreak;
// barrier
wire is_barrier;
wire[31:0] barrier_id;
wire[$clog2(`NW):0] num_warps;
wire[$clog2(`NUM_WARPS):0] num_warps;
wire is_split;
wire dont_split;
wire[`NW_M1:0] split_warp_num;
wire[`NT_M1:0] split_new_mask;
wire[`NT_M1:0] split_later_mask;
wire[`NW_BITS-1:0] split_warp_num;
wire[`NUM_THREADS-1:0] split_new_mask;
wire[`NUM_THREADS-1:0] split_later_mask;
wire[31:0] split_save_pc;

8
hw/rtl/interfaces/VX_wb_inter.v
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@@ -1,4 +1,4 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_WB_INTER
@@ -7,12 +7,12 @@
interface VX_wb_inter ();
wire[`NT_M1:0][31:0] write_data;
wire[`NUM_THREADS-1:0][31:0] write_data;
wire[31:0] wb_pc;
wire[4:0] rd;
wire[1:0] wb;
wire[`NT_M1:0] wb_valid;
wire[`NW_M1:0] wb_warp_num;
wire[`NUM_THREADS-1:0] wb_valid;
wire[`NW_BITS-1:0] wb_warp_num;
endinterface

4
hw/rtl/interfaces/VX_wstall_inter.v
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@@ -1,4 +1,4 @@
`include "../VX_define.v"
`include "../VX_define.vh"
`ifndef VX_WSTALL_INTER
@@ -7,7 +7,7 @@
interface VX_wstall_inter();
wire wstall;
wire[`NW_M1:0] warp_num;
wire[`NW_BITS-1:0] warp_num;
endinterface