added config.vh
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@@ -1,4 +1,4 @@
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`include "VX_cache_config.v"
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`include "VX_cache_config.vh"
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module VX_cache_wb_sel_merge
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#(
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@@ -53,7 +53,7 @@ module VX_cache_wb_sel_merge
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input wire [NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_wb_tid,
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input wire [NUMBER_BANKS-1:0][4:0] per_bank_wb_rd,
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input wire [NUMBER_BANKS-1:0][1:0] per_bank_wb_wb,
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input wire [NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num,
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input wire [NUMBER_BANKS-1:0][`NW_BITS-1:0] per_bank_wb_warp_num,
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input wire [NUMBER_BANKS-1:0][`WORD_SIZE_RNG] per_bank_wb_data,
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input wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_pc,
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input wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_address,
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@@ -67,7 +67,7 @@ module VX_cache_wb_sel_merge
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output reg [NUMBER_REQUESTS-1:0][31:0] core_wb_pc,
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output wire [4:0] core_wb_req_rd,
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output wire [1:0] core_wb_req_wb,
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output wire [`NW_M1:0] core_wb_warp_num,
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output wire [`NW_BITS-1:0] core_wb_warp_num,
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output reg [NUMBER_REQUESTS-1:0][31:0] core_wb_address
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);
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@@ -105,7 +105,7 @@ module VX_cache_wb_sel_merge
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core_wb_pc = 0;
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core_wb_address = 0;
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for (this_bank = 0; this_bank < NUMBER_BANKS; this_bank = this_bank + 1) begin
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if ((FUNC_ID == `LLFUNC_ID) || (FUNC_ID == `L3FUNC_ID)) begin
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if ((FUNC_ID == `L2FUNC_ID) || (FUNC_ID == `L3FUNC_ID)) begin
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if (found_bank && !core_wb_valid[per_bank_wb_tid[this_bank]] && per_bank_wb_valid[this_bank] && ((this_bank == main_bank_index) || (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index]))) begin
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core_wb_valid[per_bank_wb_tid[this_bank]] = 1;
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