added config.vh
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12
hw/rtl/cache/VX_d_cache_tb.v
vendored
12
hw/rtl/cache/VX_d_cache_tb.v
vendored
@@ -1,4 +1,4 @@
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`include "VX_define.v"
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`include "VX_define.vh"
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`include "VX_d_cache.v"
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module VX_d_cache_tb;
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@@ -6,13 +6,13 @@ module VX_d_cache_tb;
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parameter NUMBER_BANKS = 8;
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reg clk, reset, im_ready;
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reg [`NT_M1:0] i_p_valid;
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reg [`NT_M1:0][13:0] i_p_addr; // FIXME
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reg [`NUM_THREADS-1:0] i_p_valid;
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reg [`NUM_THREADS-1:0][13:0] i_p_addr; // FIXME
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reg i_p_initial_request;
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reg [`NT_M1:0][31:0] i_p_writedata;
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reg [`NUM_THREADS-1:0][31:0] i_p_writedata;
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reg i_p_read_or_write; //, i_p_write;
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reg [`NT_M1:0][31:0] o_p_readdata;
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reg [`NT_M1:0] o_p_readdata_valid;
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reg [`NUM_THREADS-1:0][31:0] o_p_readdata;
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reg [`NUM_THREADS-1:0] o_p_readdata_valid;
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reg o_p_waitrequest;
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reg [13:0] o_m_addr; // Only one address is sent out at a time to memory
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reg o_m_valid;
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