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instruction buffer optimization

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This commit is contained in:
Blaise Tine
2021-08-02 19:54:28 -07:00
parent 26f553b75b
commit 80f62e8a41
1 changed files with 26 additions and 26 deletions
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52
hw/rtl/VX_ibuffer.v
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@@ -91,8 +91,8 @@ module VX_ibuffer #(
/////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////
reg [`NUM_WARPS-1:0] valid_table, valid_table_n; reg [`NUM_WARPS-1:0] valid_table, valid_table_n;
reg [`NUM_WARPS-1:0] schedule_table, schedule_table_n;
reg [`NW_BITS-1:0] deq_wid, deq_wid_n; reg [`NW_BITS-1:0] deq_wid, deq_wid_n;
reg [`NW_BITS-1:0] deq_wid_rr, deq_wid_rr_n;
reg deq_valid, deq_valid_n; reg deq_valid, deq_valid_n;
reg [DATAW-1:0] deq_instr, deq_instr_n; reg [DATAW-1:0] deq_instr, deq_instr_n;
reg [NWARPSW-1:0] num_warps; reg [NWARPSW-1:0] num_warps;
@@ -108,34 +108,34 @@ module VX_ibuffer #(
end end
end end
// round-robin warp scheduling
VX_rr_arbiter #(
.NUM_REQS (`NUM_WARPS)
) rr_arbiter (
.clk (clk),
.reset (reset),
.enable (ibuffer_if.ready),
.requests (valid_table_n),
.grant_index (deq_wid_rr_n),
`UNUSED_PIN (grant_onehot),
`UNUSED_PIN (grant_valid)
);
// schedule the next instruction to issue // schedule the next instruction to issue
always @(*) begin always @(*) begin
deq_valid_n = enq_fire;
deq_wid_n = decode_if.wid;
deq_instr_n = q_data_in;
if (num_warps > 1) begin if (num_warps > 1) begin
deq_valid_n = 1; deq_valid_n = 1;
for (integer i = `NUM_WARPS-1; i >= 0; --i) begin deq_wid_n = deq_wid_rr;
if (schedule_table[i]) begin deq_instr_n = q_data_out[deq_wid_rr];
deq_wid_n = `NW_BITS'(i);
deq_instr_n = q_data_out[i];
end
end
end else if (1 == num_warps && !(deq_fire && q_alm_empty[deq_wid])) begin end else if (1 == num_warps && !(deq_fire && q_alm_empty[deq_wid])) begin
deq_valid_n = 1; deq_valid_n = 1;
deq_wid_n = deq_wid; deq_wid_n = deq_wid;
deq_instr_n = deq_fire ? q_data_prev[deq_wid] : q_data_out[deq_wid]; deq_instr_n = deq_fire ? q_data_prev[deq_wid] : q_data_out[deq_wid];
end
end
// do round-robin scheduling with multiple active warps
always @(*) begin
if ($countones(schedule_table) <= 1) begin
schedule_table_n = valid_table_n;
end else begin end else begin
schedule_table_n = schedule_table; deq_valid_n = enq_fire;
deq_wid_n = decode_if.wid;
deq_instr_n = q_data_in;
end end
schedule_table_n[deq_wid_n] = 0;
end end
wire warp_added = enq_fire && q_empty[decode_if.wid]; wire warp_added = enq_fire && q_empty[decode_if.wid];
@@ -143,14 +143,14 @@ module VX_ibuffer #(
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
valid_table <= 0; valid_table <= 0;
deq_valid <= 0; deq_valid <= 0;
num_warps <= 0; num_warps <= 0;
schedule_table <= 0; deq_wid_rr <= 0;
end else begin end else begin
valid_table <= valid_table_n; valid_table <= valid_table_n;
deq_valid <= deq_valid_n; deq_valid <= deq_valid_n;
schedule_table <= schedule_table_n; deq_wid_rr <= deq_wid_rr_n;
if (warp_added && !warp_removed) begin if (warp_added && !warp_removed) begin
num_warps <= num_warps + NWARPSW'(1); num_warps <= num_warps + NWARPSW'(1);