Before fixing miss rsrv for ST->LD sequences

2020-03-03 16:57:05 -08:00
parent 361fc2c3fe
commit 80af320fdb
6 changed files with 110 additions and 20 deletions
--- a/rtl/VX_cache/VX_cache_dram_req_arb.v
+++ b/rtl/VX_cache/VX_cache_dram_req_arb.v
@@ -63,6 +63,7 @@ module VX_cache_dram_req_arb (
 	assign dram_req_write = dwb_valid;
 	assign dram_req_read  = dfqq_req && !dwb_valid;
 	assign dram_req_addr  = dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr;
+	assign dram_req_size  = `BANK_LINE_SIZE_BYTES;
 	assign dram_req_data  = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0;

 endmodule