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simx timing simulation refactoring

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This commit is contained in:
Blaise Tine
2021-11-14 08:52:34 -05:00
parent 9656779d48
commit 808bddb586
22 changed files with 1123 additions and 903 deletions
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22
sim/simX/memsim.cpp
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@@ -8,32 +8,26 @@ using namespace vortex;
class MemSim::Impl {
private:
MemSim* simobject_;
std::vector<std::queue<MemReq>> inputs_;
uint32_t num_banks_;
uint32_t latency_;
public:
Impl(MemSim* simobject, uint32_t num_banks, uint32_t latency)
: simobject_(simobject)
, inputs_(num_banks)
, num_banks_(num_banks)
, latency_(latency)
{}
void handleMemRequest(const MemReq& mem_req, uint32_t port_id) {
inputs_.at(port_id).push(mem_req);
}
void step(uint64_t /*cycle*/) {
for (uint32_t i = 0, n = inputs_.size(); i < n; ++i) {
auto& queue = inputs_.at(i);
if (queue.empty())
for (uint32_t i = 0, n = num_banks_; i < n; ++i) {
MemReq mem_req;
if (!simobject_->MemReqPorts.at(i).read(&mem_req))
continue;
auto& entry = queue.front();
if (!entry.write) {
if (!mem_req.write) {
MemRsp mem_rsp;
mem_rsp.tag = entry.tag;
mem_rsp.tag = mem_req.tag;
simobject_->MemRspPorts.at(i).send(mem_rsp, latency_);
}
queue.pop();
}
}
};
@@ -45,7 +39,7 @@ MemSim::MemSim(const SimContext& ctx,
uint32_t latency)
: SimObject<MemSim>(ctx, "MemSim")
, impl_(new Impl(this, num_banks, latency))
, MemReqPorts(num_banks, {this, impl_, &Impl::handleMemRequest})
, MemReqPorts(num_banks, this)
, MemRspPorts(num_banks, this)
{}