minor update

2021-07-20 21:23:31 -07:00
parent aa7b0da877
commit 8048796102
9 changed files with 81 additions and 81 deletions
--- a/hw/rtl/interfaces/VX_mem_rsp_if.v
+++ b/hw/rtl/interfaces/VX_mem_rsp_if.v
@@ -4,14 +4,14 @@
 `include "../cache/VX_cache_define.vh"

 interface VX_mem_rsp_if #(
-    parameter MEM_LINE_WIDTH = 1,
-    parameter MEM_TAG_WIDTH  = 1
+    parameter LINE_WIDTH = 1,
+    parameter TAG_WIDTH  = 1
 ) ();

-    wire                        valid;    
-    wire [MEM_LINE_WIDTH-1:0]   data;
-    wire [MEM_TAG_WIDTH-1:0]    tag;  
-    wire                        ready;      
+    wire                    valid;    
+    wire [LINE_WIDTH-1:0]   data;
+    wire [TAG_WIDTH-1:0]    tag;  
+    wire                    ready;      

 endinterface