wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

minor update

Browse Source
This commit is contained in:
Blaise Tine
2021-07-20 21:23:31 -07:00
parent aa7b0da877
commit 8048796102
9 changed files with 81 additions and 81 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
hw/rtl/interfaces/VX_dcache_req_if.v
View File

@@ -4,9 +4,9 @@
`include "../cache/VX_cache_define.vh"
interface VX_dcache_req_if #(
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter TAG_WIDTH = 1
) ();
wire [NUM_REQS-1:0] valid;
@@ -14,7 +14,7 @@ interface VX_dcache_req_if #(
wire [NUM_REQS-1:0][WORD_SIZE-1:0] byteen;
wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] addr;
wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] data;
wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] tag;
wire [NUM_REQS-1:0][TAG_WIDTH-1:0] tag;
wire [NUM_REQS-1:0] ready;
endinterface

8
hw/rtl/interfaces/VX_dcache_rsp_if.v
View File

@@ -4,15 +4,15 @@
`include "../cache/VX_cache_define.vh"
interface VX_dcache_rsp_if #(
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter TAG_WIDTH = 1
) ();
wire valid;
wire [NUM_REQS-1:0] tmask;
wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] data;
wire [CORE_TAG_WIDTH-1:0] tag;
wire [TAG_WIDTH-1:0] tag;
wire ready;
endinterface

6
hw/rtl/interfaces/VX_icache_req_if.v
View File

@@ -4,13 +4,13 @@
`include "../cache/VX_cache_define.vh"
interface VX_icache_req_if #(
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
parameter WORD_SIZE = 1,
parameter TAG_WIDTH = 1
) ();
wire valid;
wire [`WORD_ADDR_WIDTH-1:0] addr;
wire [CORE_TAG_WIDTH-1:0] tag;
wire [TAG_WIDTH-1:0] tag;
wire ready;
endinterface

12
hw/rtl/interfaces/VX_icache_rsp_if.v
View File

@@ -4,14 +4,14 @@
`include "../cache/VX_cache_define.vh"
interface VX_icache_rsp_if #(
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
parameter WORD_SIZE = 1,
parameter TAG_WIDTH = 1
) ();
wire valid;
wire [`WORD_WIDTH-1:0] data;
wire [CORE_TAG_WIDTH-1:0] tag;
wire ready;
wire valid;
wire [`WORD_WIDTH-1:0] data;
wire [TAG_WIDTH-1:0] tag;
wire ready;
endinterface

22
hw/rtl/interfaces/VX_mem_req_if.v
View File

@@ -4,19 +4,19 @@
`include "../cache/VX_cache_define.vh"
interface VX_mem_req_if #(
parameter MEM_LINE_WIDTH = 1,
parameter MEM_ADDR_WIDTH = 1,
parameter MEM_TAG_WIDTH = 1,
parameter MEM_LINE_SIZE = MEM_LINE_WIDTH / 8
parameter LINE_WIDTH = 1,
parameter ADDR_WIDTH = 1,
parameter TAG_WIDTH = 1,
parameter LINE_SIZE = LINE_WIDTH / 8
) ();
wire valid;
wire rw;
wire [MEM_LINE_SIZE-1:0] byteen;
wire [MEM_ADDR_WIDTH-1:0] addr;
wire [MEM_LINE_WIDTH-1:0] data;
wire [MEM_TAG_WIDTH-1:0] tag;
wire ready;
wire valid;
wire rw;
wire [LINE_SIZE-1:0] byteen;
wire [ADDR_WIDTH-1:0] addr;
wire [LINE_WIDTH-1:0] data;
wire [TAG_WIDTH-1:0] tag;
wire ready;
endinterface

12
hw/rtl/interfaces/VX_mem_rsp_if.v
View File

@@ -4,14 +4,14 @@
`include "../cache/VX_cache_define.vh"
interface VX_mem_rsp_if #(
parameter MEM_LINE_WIDTH = 1,
parameter MEM_TAG_WIDTH = 1
parameter LINE_WIDTH = 1,
parameter TAG_WIDTH = 1
) ();
wire valid;
wire [MEM_LINE_WIDTH-1:0] data;
wire [MEM_TAG_WIDTH-1:0] tag;
wire ready;
wire valid;
wire [LINE_WIDTH-1:0] data;
wire [TAG_WIDTH-1:0] tag;
wire ready;
endinterface