Modifications to allow 64-bit riscv tests to run on travis CI
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@@ -256,15 +256,18 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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// RV32I: XOR
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rddata[t] = rsdata[t][0] ^ rsdata[t][1];
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break;
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case 5:
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case 5: {
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XWord shamt_mask = (1 << log2up(XLEN)) - 1;
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XWord shamt = rsdata[t][1] & shamt_mask;
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if (func7) {
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// RV32I: SRA
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rddata[t] = XWordI(rsdata[t][0]) >> XWordI(rsdata[t][1]);
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rddata[t] = XWordI(rsdata[t][0]) >> shamt;
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} else {
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// RV32I: SRL
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rddata[t] = XWord(rsdata[t][0]) >> XWord(rsdata[t][1]);
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rddata[t] = XWord(rsdata[t][0]) >> shamt;
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}
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break;
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}
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case 6:
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// RV32I: OR
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rddata[t] = rsdata[t][0] | rsdata[t][1];
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@@ -315,7 +318,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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rddata[t] = result;
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} else {
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// RV64I: SRLI
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XWord result = rsdata[t][0] >> immsrc;
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XWord result = XWord(rsdata[t][0]) >> immsrc;
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rddata[t] = result;
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}
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break;
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@@ -413,15 +416,18 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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// RV64I: SLLW
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rddata[t] = sext64((Word)rsdata[t][0] << (Word)rsdata[t][1], 32);
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break;
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case 5:
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case 5: {
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Word shamt_mask = 0x1F;
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Word shamt = rsdata[t][1] & shamt_mask;
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if (func7) {
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// RV64I: SRAW
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rddata[t] = sext64((WordI)rsdata[t][0] >> (WordI)rsdata[t][1], 32);
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rddata[t] = sext64((WordI)rsdata[t][0] >> shamt, 32);
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} else {
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// RV64I: SRLW
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rddata[t] = sext64((Word)rsdata[t][0] >> (Word)rsdata[t][1], 32);
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rddata[t] = sext64((Word)rsdata[t][0] >> shamt, 32);
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}
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break;
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}
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default:
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std::abort();
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}
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@@ -449,11 +455,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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case 5:
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if (func7) {
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// RV64I: SRAIW
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XWord result = sext64((WordI)rsdata[t][0] >> (WordI)immsrc, 32);
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XWord result = sext64((WordI)rsdata[t][0] >> immsrc, 32);
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rddata[t] = result;
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} else {
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// RV64I: SRLIW
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XWord result = sext64((Word)rsdata[t][0] >> (Word)immsrc, 32);
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XWord result = sext64((Word)rsdata[t][0] >> immsrc, 32);
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rddata[t] = result;
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}
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break;
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