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pipeline refactoring: centralized issue buffer

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This commit is contained in:
Blaise Tine
2020-07-26 11:21:08 -04:00
parent 1f63f9da25
commit 7c86b68977
62 changed files with 923 additions and 820 deletions
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74
hw/rtl/libs/VX_cam_buffer.v Normal file
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@@ -0,0 +1,74 @@
`include "VX_define.vh"
module VX_cam_buffer #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter RPORTS = 1,
parameter ADDRW = `LOG2UP(SIZE)
) (
input wire clk,
input wire reset,
input wire [DATAW-1:0] write_data,
output wire [ADDRW-1:0] write_addr,
input wire acquire_slot,
input wire [RPORTS-1:0][ADDRW-1:0] read_addr,
output reg [RPORTS-1:0][DATAW-1:0] read_data,
input wire [RPORTS-1:0] release_slot,
output wire full
);
reg [DATAW-1:0] entries [SIZE-1:0];
reg [SIZE-1:0] free_slots, free_slots_n;
reg [ADDRW-1:0] write_addr_r;
reg full_r;
wire free_valid;
wire [ADDRW-1:0] free_index;
VX_priority_encoder #(
.N(SIZE)
) free_slots_encoder (
.data_in (free_slots_n),
.data_out (free_index),
.valid_out (free_valid)
);
integer i;
always @(*) begin
free_slots_n = free_slots;
if (acquire_slot) begin
free_slots_n[write_addr_r] = 0;
end
for (i = 0; i < RPORTS; i++) begin
if (release_slot[i]) begin
free_slots_n[read_addr[i]] = 1;
end
assign read_data[i] = entries[read_addr[i]];
end
end
always @(posedge clk) begin
if (reset) begin
free_slots <= {SIZE{1'b1}};
full_r <= 1'b0;
write_addr_r <= ADDRW'(1'b0);
end else begin
if (acquire_slot) begin
assert(1 == free_slots[write_addr]);
entries[write_addr] <= write_data;
end
for (i = 0; i < RPORTS; i++) begin
if (release_slot[i]) begin
assert(0 == free_slots[read_addr[i]]);
end
end
free_slots <= free_slots_n;
write_addr_r <= free_index;
full_r <= ~free_valid;
end
end
assign write_addr = write_addr_r;
assign full = full_r;
endmodule

21
hw/rtl/libs/VX_divide.v
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@@ -12,6 +12,7 @@ module VX_divide #(
input wire clk,
input wire reset,
input wire clk_en,
input wire [WIDTHN-1:0] numer,
input wire [WIDTHD-1:0] denom,
@@ -31,7 +32,7 @@ module VX_divide #(
.quotient (quotient_unqual),
.remain (remainder_unqual),
.aclr (1'b0),
.clken (1'b1)
.clken (clk_en)
);
defparam
@@ -43,8 +44,8 @@ module VX_divide #(
quartus_div.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE",
quartus_div.lpm_pipeline = PIPELINE;
assign quotient = quotient_unqual[WIDTHQ-1:0];
assign remainder = remainder_unqual[WIDTHR-1:0];
assign quotient = quotient_unqual [WIDTHQ-1:0];
assign remainder = remainder_unqual [WIDTHR-1:0];
`else
@@ -82,8 +83,8 @@ module VX_divide #(
end
if (PIPELINE == 0) begin
assign quotient = quotient_unqual[WIDTHQ-1:0];
assign remainder = remainder_unqual[WIDTHR-1:0];
assign quotient = quotient_unqual [WIDTHQ-1:0];
assign remainder = remainder_unqual [WIDTHR-1:0];
end else begin
reg [WIDTHN-1:0] quotient_pipe [0:PIPELINE-1];
reg [WIDTHD-1:0] remainder_pipe [0:PIPELINE-1];
@@ -95,14 +96,14 @@ module VX_divide #(
quotient_pipe[i] <= 0;
remainder_pipe[i] <= 0;
end
else begin
else if (clk_en) begin
if (i == 0) begin
quotient_pipe[0] <= quotient_unqual;
remainder_pipe[0] <= remainder_unqual;
quotient_pipe[i] <= quotient_unqual;
remainder_pipe[i] <= remainder_unqual;
end else begin
quotient_pipe[i] <= quotient_pipe[i-1];
remainder_pipe[i] <= remainder_pipe[i-1];
end
remainder_pipe[i] <= remainder_pipe[i-1];
end
end
end
end

8
hw/rtl/libs/VX_generic_queue.v
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@@ -1,9 +1,9 @@
`include "VX_define.vh"
module VX_generic_queue #(
parameter DATAW = 1,
parameter SIZE = 16,
parameter BUFFERED_OUTPUT = 1
parameter DATAW = 1,
parameter SIZE = 16,
parameter BUFFERED = 1
) (
input wire clk,
input wire reset,
@@ -58,7 +58,7 @@ module VX_generic_queue #(
reg [DATAW-1:0] data [SIZE-1:0];
`endif
if (0 == BUFFERED_OUTPUT) begin
if (0 == BUFFERED) begin
reg [`LOG2UP(SIZE):0] rd_ptr_r;
reg [`LOG2UP(SIZE):0] wr_ptr_r;

75
hw/rtl/libs/VX_mult.v
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@@ -1,75 +0,0 @@
`include "VX_define.vh"
module VX_mult #(
parameter WIDTHA = 1,
parameter WIDTHB = 1,
parameter WIDTHP = 1,
parameter SIGNED = 0,
parameter PIPELINE = 0
) (
input wire clk,
input wire reset,
input wire [WIDTHA-1:0] dataa,
input wire [WIDTHB-1:0] datab,
output wire [WIDTHP-1:0] result
);
`ifdef QUARTUS
lpm_mult quartus_mult (
.clock (clk),
.dataa (dataa),
.datab (datab),
.result (result),
.sclr (reset),
.aclr (1'b0),
.clken (1'b1),
.sum (1'b0)
);
defparam quartus_mult.lpm_type = "LPM_MULT",
quartus_mult.lpm_widtha = WIDTHA,
quartus_mult.lpm_widthb = WIDTHB,
quartus_mult.lpm_widthp = WIDTHP,
quartus_mult.lpm_representation = SIGNED ? "SIGNED" : "UNSIGNED",
quartus_mult.lpm_pipeline = PIPELINE,
quartus_mult.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9";
`else
wire [WIDTHP-1:0] result_unqual;
if (SIGNED) begin
assign result_unqual = $signed(dataa) * $signed(datab);
end else begin
assign result_unqual = dataa * datab;
end
if (PIPELINE == 0) begin
assign result = result_unqual;
end else begin
reg [WIDTHP-1:0] result_pipe [0:PIPELINE-1];
genvar i;
for (i = 0; i < PIPELINE; i++) begin
always @(posedge clk) begin
if (reset) begin
result_pipe[i] <= 0;
end
else begin
if (i == 0) begin
result_pipe[0] <= result_unqual;
end else begin
result_pipe[i] <= result_pipe[i-1];
end
end
end
end
assign result = result_pipe[PIPELINE-1];
end
`endif
endmodule

1
hw/rtl/libs/VX_priority_encoder.v
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@@ -8,6 +8,7 @@ module VX_priority_encoder #(
output reg valid_out
);
integer i;
always @(*) begin
data_out = 0;
valid_out = 0;