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pipeline refactoring: centralized issue buffer

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This commit is contained in:
Blaise Tine
2020-07-26 11:21:08 -04:00
parent 1f63f9da25
commit 7c86b68977
62 changed files with 923 additions and 820 deletions
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88
hw/rtl/VX_writeback.v
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@@ -10,79 +10,87 @@ module VX_writeback #(
VX_commit_if alu_commit_if,
VX_commit_if lsu_commit_if,
VX_commit_if mul_commit_if,
VX_commit_fp_if fpu_commit_if,
VX_commit_if fpu_commit_if,
VX_commit_if csr_commit_if,
VX_commit_is_if commit_is_if,
// outputs
VX_wb_if writeback_if
);
wire alu_valid = (| alu_commit_if.valid) && alu_commit_if.wb;
wire lsu_valid = (| lsu_commit_if.valid) && lsu_commit_if.wb;
wire csr_valid = (| csr_commit_if.valid) && csr_commit_if.wb;
wire mul_valid = (| mul_commit_if.valid) && mul_commit_if.wb;
wire fpu_valid = (| fpu_commit_if.valid) && fpu_commit_if.wb;
wire alu_valid = alu_commit_if.valid && commit_is_if.alu_data.wb;
wire lsu_valid = lsu_commit_if.valid && commit_is_if.lsu_data.wb;
wire csr_valid = csr_commit_if.valid && commit_is_if.csr_data.wb;
wire mul_valid = mul_commit_if.valid && commit_is_if.mul_data.wb;
wire fpu_valid = fpu_commit_if.valid && commit_is_if.fpu_data.wb;
VX_wb_if writeback_tmp_if();
assign writeback_tmp_if.valid = lsu_valid ? lsu_commit_if.valid :
fpu_valid ? fpu_commit_if.valid :
mul_valid ? mul_commit_if.valid :
alu_valid ? alu_commit_if.valid :
csr_valid ? csr_commit_if.valid :
assign writeback_tmp_if.valid = alu_valid ? alu_commit_if.valid :
lsu_valid ? lsu_commit_if.valid :
csr_valid ? csr_commit_if.valid :
mul_valid ? mul_commit_if.valid :
fpu_valid ? fpu_commit_if.valid :
0;
assign writeback_tmp_if.warp_num = lsu_valid ? lsu_commit_if.warp_num :
fpu_valid ? fpu_commit_if.warp_num :
mul_valid ? mul_commit_if.warp_num :
alu_valid ? alu_commit_if.warp_num :
csr_valid ? csr_commit_if.warp_num :
assign writeback_tmp_if.warp_num = alu_valid ? commit_is_if.alu_data.warp_num :
lsu_valid ? commit_is_if.lsu_data.warp_num :
csr_valid ? commit_is_if.csr_data.warp_num :
mul_valid ? commit_is_if.mul_data.warp_num :
fpu_valid ? commit_is_if.fpu_data.warp_num :
0;
assign writeback_tmp_if.thread_mask = alu_valid ? commit_is_if.alu_data.thread_mask :
lsu_valid ? commit_is_if.lsu_data.thread_mask :
csr_valid ? commit_is_if.csr_data.thread_mask :
mul_valid ? commit_is_if.mul_data.thread_mask :
fpu_valid ? commit_is_if.fpu_data.thread_mask :
0;
assign writeback_tmp_if.rd = lsu_valid ? lsu_commit_if.rd :
fpu_valid ? fpu_commit_if.rd :
mul_valid ? mul_commit_if.rd :
alu_valid ? alu_commit_if.rd :
csr_valid ? csr_commit_if.rd :
assign writeback_tmp_if.rd = alu_valid ? commit_is_if.alu_data.rd :
lsu_valid ? commit_is_if.lsu_data.rd :
csr_valid ? commit_is_if.csr_data.rd :
mul_valid ? commit_is_if.mul_data.rd :
fpu_valid ? commit_is_if.fpu_data.rd :
0;
assign writeback_tmp_if.rd_is_fp = lsu_valid ? 0 :
fpu_valid ? fpu_commit_if.rd_is_fp :
mul_valid ? 0 :
alu_valid ? 0 :
assign writeback_tmp_if.rd_is_fp = alu_valid ? 0 :
lsu_valid ? 0 :
csr_valid ? 0 :
mul_valid ? 0 :
fpu_valid ? commit_is_if.fpu_data.rd_is_fp :
0;
assign writeback_tmp_if.data = lsu_valid ? lsu_commit_if.data :
fpu_valid ? fpu_commit_if.data :
mul_valid ? mul_commit_if.data :
alu_valid ? alu_commit_if.data :
csr_valid ? csr_commit_if.data :
assign writeback_tmp_if.data = alu_valid ? alu_commit_if.data :
lsu_valid ? lsu_commit_if.data :
csr_valid ? csr_commit_if.data :
mul_valid ? mul_commit_if.data :
fpu_valid ? fpu_commit_if.data :
0;
wire stall = ~writeback_if.ready && (| writeback_if.valid);
wire stall = ~writeback_if.ready && writeback_if.valid;
VX_generic_register #(
.N(`NUM_THREADS + `NW_BITS + `NR_BITS + (`NUM_THREADS * 32) + 1)
.N(1 + `NW_BITS + `NUM_THREADS + `NR_BITS + (`NUM_THREADS * 32) + 1)
) wb_reg (
.clk (clk),
.reset (reset),
.stall (stall),
.flush (0),
.in ({writeback_tmp_if.valid, writeback_tmp_if.warp_num, writeback_tmp_if.rd, writeback_tmp_if.rd_is_fp, writeback_tmp_if.data}),
.out ({writeback_if.valid, writeback_if.warp_num, writeback_if.rd, writeback_if.rd_is_fp, writeback_if.data})
.in ({writeback_tmp_if.valid, writeback_tmp_if.warp_num, writeback_tmp_if.thread_mask, writeback_tmp_if.rd, writeback_tmp_if.rd_is_fp, writeback_tmp_if.data}),
.out ({writeback_if.valid, writeback_if.warp_num, writeback_if.thread_mask, writeback_if.rd, writeback_if.rd_is_fp, writeback_if.data})
);
assign lsu_commit_if.ready = !stall;
assign fpu_commit_if.ready = !stall && !lsu_valid;
assign mul_commit_if.ready = !stall && !lsu_valid && !fpu_valid;
assign alu_commit_if.ready = !stall && !lsu_valid && !fpu_valid && !mul_valid;
assign csr_commit_if.ready = !stall && !lsu_valid && !fpu_valid && !mul_valid && !alu_valid;
assign alu_commit_if.ready = !stall;
assign lsu_commit_if.ready = !stall && !alu_valid;
assign csr_commit_if.ready = !stall && !alu_valid && !lsu_valid;
assign mul_commit_if.ready = !stall && !alu_valid && !lsu_valid && !csr_valid;
assign fpu_commit_if.ready = !stall && !alu_valid && !lsu_valid && !csr_valid && !mul_valid;
// special workaround to control RISC-V benchmarks termination on Verilator
reg [31:0] last_data_wb /* verilator public */;
always @(posedge clk) begin
if ((| writeback_tmp_if.valid) && ~stall && (writeback_tmp_if.rd == 28)) begin
if (writeback_tmp_if.valid && ~stall && (writeback_tmp_if.rd == 28)) begin
last_data_wb <= writeback_tmp_if.data[0];
end
end