pipeline refactoring: centralized issue buffer

2020-07-26 11:21:08 -04:00
parent 1f63f9da25
commit 7c86b68977
62 changed files with 923 additions and 820 deletions
--- a/hw/rtl/VX_gpr_ram.v
+++ b/hw/rtl/VX_gpr_ram.v
@@ -35,8 +35,6 @@ module VX_gpr_ram (
                    ram[waddr][i][3] <= wdata[i][31:24];
                end
            end
-            assert(~(|we) || (waddr != 0)); // ensure r0 is never written!
-            assert(0 == ram[0]);
        end
        
        assign rs1_data = ram[rs1];