unused variables refactoring

hw/rtl/VX_commit.v

@@ -11,7 +11,9 @@ module VX_commit #(
     VX_commit_if    ld_commit_if,
     VX_commit_if    st_commit_if, 
     VX_commit_if    csr_commit_if,
+`ifdef EXT_F_ENABLE
     VX_commit_if    fpu_commit_if,
+`endif
     VX_commit_if    gpu_commit_if,
 
     // outputs
@@ -26,14 +28,18 @@ module VX_commit #(
     wire ld_commit_fire  = ld_commit_if.valid && ld_commit_if.ready;
     wire st_commit_fire  = st_commit_if.valid && st_commit_if.ready;
     wire csr_commit_fire = csr_commit_if.valid && csr_commit_if.ready;
+`ifdef EXT_F_ENABLE
     wire fpu_commit_fire = fpu_commit_if.valid && fpu_commit_if.ready;
+`endif
     wire gpu_commit_fire = gpu_commit_if.valid && gpu_commit_if.ready;
 
     wire commit_fire = alu_commit_fire
                     || ld_commit_fire
                     || st_commit_fire
                     || csr_commit_fire
+                `ifdef EXT_F_ENABLE
                     || fpu_commit_fire
+                `endif
                     || gpu_commit_fire;
 
     wire [`NUM_THREADS-1:0] commit_tmask1, commit_tmask2, commit_tmask3; 
@@ -41,7 +47,9 @@ module VX_commit #(
     assign commit_tmask1 = alu_commit_fire ? alu_commit_if.tmask:
                            ld_commit_fire  ? ld_commit_if.tmask:                                           
                            csr_commit_fire ? csr_commit_if.tmask:
+                        `ifdef EXT_F_ENABLE
                            fpu_commit_fire ? fpu_commit_if.tmask:
+                        `endif
                                              0;
 
     assign commit_tmask2 = st_commit_fire ? st_commit_if.tmask : 0;
@@ -72,8 +80,9 @@ module VX_commit #(
         .alu_commit_if  (alu_commit_if),
         .ld_commit_if   (ld_commit_if),        
         .csr_commit_if  (csr_commit_if),
+    `ifdef EXT_F_ENABLE
         .fpu_commit_if  (fpu_commit_if),
-
+    `endif
         .writeback_if   (writeback_if)
     );
 
@@ -101,19 +110,19 @@ module VX_commit #(
             `PRINT_ARRAY1D(csr_commit_if.data, `NUM_THREADS);
             $write("\n");
         end      
+    `ifdef EXT_F_ENABLE
         if (fpu_commit_if.valid && fpu_commit_if.ready) begin
             $write("%t: core%0d-commit: wid=%0d, PC=%0h, ex=FPU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, fpu_commit_if.wid, fpu_commit_if.PC, fpu_commit_if.tmask, fpu_commit_if.wb, fpu_commit_if.rd);
             `PRINT_ARRAY1D(fpu_commit_if.data, `NUM_THREADS);
             $write("\n");
         end
+    `endif
         if (gpu_commit_if.valid && gpu_commit_if.ready) begin
             $write("%t: core%0d-commit: wid=%0d, PC=%0h, ex=GPU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, gpu_commit_if.wid, gpu_commit_if.PC, gpu_commit_if.tmask, gpu_commit_if.wb, gpu_commit_if.rd);
             `PRINT_ARRAY1D(gpu_commit_if.data, `NUM_THREADS);
             $write("\n");
         end
     end
-`else    
-    `UNUSED_VAR (fpu_commit_if.PC)
 `endif
 
 endmodule

hw/rtl/VX_csr_data.v

@@ -12,7 +12,10 @@ module VX_csr_data #(
 `endif
 
     VX_cmt_to_csr_if                cmt_to_csr_if,
+
+`ifdef EXT_F_ENABLE
     VX_fpu_to_csr_if                fpu_to_csr_if,  
+`endif
 
     input wire                      read_enable,
     input wire[`CSR_ADDR_BITS-1:0]  read_addr,
@@ -42,6 +45,7 @@ module VX_csr_data #(
 
     always @(posedge clk) begin
     
+    `ifdef EXT_F_ENABLE
         if (reset) begin
             fcsr <= '0;
         end
@@ -50,6 +54,7 @@ module VX_csr_data #(
             fcsr[fpu_to_csr_if.write_wid][`FFG_BITS-1:0] <= fcsr[fpu_to_csr_if.write_wid][`FFG_BITS-1:0] 
                                                           | fpu_to_csr_if.write_fflags;
         end
+    `endif
 
         if (write_enable) begin
             case (write_addr)
@@ -212,6 +217,8 @@ module VX_csr_data #(
 
     assign read_data = read_data_r;
 
+`ifdef EXT_F_ENABLE    
     assign fpu_to_csr_if.read_frm = fcsr[fpu_to_csr_if.read_wid][`FRM_BITS+`FFG_BITS-1:`FFG_BITS];
+`endif
 
 endmodule

hw/rtl/VX_csr_unit.v

@@ -12,15 +12,16 @@ module VX_csr_unit #(
 `endif
 
     VX_cmt_to_csr_if    cmt_to_csr_if,
-    VX_fpu_to_csr_if    fpu_to_csr_if,
-    
     VX_csr_req_if       csr_req_if,
     VX_commit_if        csr_commit_if,
     
-    input wire          busy,
+`ifdef EXT_F_ENABLE
-
+    VX_fpu_to_csr_if    fpu_to_csr_if,
     input wire[`NUM_WARPS-1:0] fpu_pending,
-    output wire[`NUM_WARPS-1:0] pending
+`endif
+
+    output wire[`NUM_WARPS-1:0] pending,
+    input wire          busy
 );    
     wire csr_we_s1;
     wire [`CSR_ADDR_BITS-1:0] csr_addr_s1;    
@@ -41,7 +42,9 @@ module VX_csr_unit #(
         .perf_pipeline_if (perf_pipeline_if),
     `endif
         .cmt_to_csr_if  (cmt_to_csr_if),
+    `ifdef EXT_F_ENABLE
         .fpu_to_csr_if  (fpu_to_csr_if), 
+    `endif
         .read_enable    (csr_req_if.valid),
         .read_addr      (csr_req_if.addr),
         .read_wid       (csr_req_if.wid),      
@@ -79,7 +82,11 @@ module VX_csr_unit #(
         endcase
     end
 
+`ifdef EXT_F_ENABLE
     wire stall_in = fpu_pending[csr_req_if.wid];
+`else 
+    wire stall_in = 0;
+`endif
 
     wire csr_req_valid = csr_req_if.valid && !stall_in;  
 

hw/rtl/VX_execute.v

@@ -24,7 +24,9 @@ module VX_execute #(
     VX_alu_req_if       alu_req_if,
     VX_lsu_req_if       lsu_req_if,    
     VX_csr_req_if       csr_req_if,  
+`ifdef EXT_F_ENABLE
     VX_fpu_req_if       fpu_req_if,    
+`endif
     VX_gpu_req_if       gpu_req_if,
     
     // outputs
@@ -34,14 +36,18 @@ module VX_execute #(
     VX_commit_if        ld_commit_if,
     VX_commit_if        st_commit_if,
     VX_commit_if        csr_commit_if,
+`ifdef EXT_F_ENABLE
     VX_commit_if        fpu_commit_if,
+`endif
     VX_commit_if        gpu_commit_if,
     
     input wire          busy
 );
+`ifdef EXT_F_ENABLE
     VX_fpu_to_csr_if     fpu_to_csr_if();     
-    wire[`NUM_WARPS-1:0] csr_pending;
     wire[`NUM_WARPS-1:0] fpu_pending;
+    wire[`NUM_WARPS-1:0] csr_pending;
+`endif    
 
     `RESET_RELAY (alu_reset);
     `RESET_RELAY (lsu_reset);
@@ -81,11 +87,15 @@ module VX_execute #(
         .perf_pipeline_if (perf_pipeline_if),
     `endif    
         .cmt_to_csr_if  (cmt_to_csr_if),  
-        .fpu_to_csr_if  (fpu_to_csr_if), 
         .csr_req_if     (csr_req_if),   
         .csr_commit_if  (csr_commit_if),
+    `ifdef EXT_F_ENABLE  
+        .fpu_to_csr_if  (fpu_to_csr_if),
         .fpu_pending    (fpu_pending),        
         .pending        (csr_pending),
+    `else
+        `UNUSED_PIN (pending),
+    `endif        
         .busy           (busy)
     );
 
@@ -103,22 +113,6 @@ module VX_execute #(
         .csr_pending    (csr_pending),
         .pending        (fpu_pending) 
     );
-`else
-    `UNUSED_VAR (csr_pending)
-    `UNUSED_VAR (fpu_to_csr_if.read_frm)
-    assign fpu_req_if.ready     = 0;
-    assign fpu_commit_if.valid  = 0;
-    assign fpu_commit_if.wid    = 0;
-    assign fpu_commit_if.PC     = 0;
-    assign fpu_commit_if.tmask  = 0;
-    assign fpu_commit_if.wb     = 0;
-    assign fpu_commit_if.rd     = 0;
-    assign fpu_commit_if.data   = 0;  
-    assign fpu_to_csr_if.write_enable = 0;  
-    assign fpu_to_csr_if.write_wid = 0;
-    assign fpu_to_csr_if.write_fflags = 0;
-    assign fpu_to_csr_if.read_wid = 0;
-    assign fpu_pending = 0;
 `endif
 
     VX_gpu_unit #(

hw/rtl/VX_instr_demux.v

@@ -12,14 +12,18 @@ module VX_instr_demux (
     VX_alu_req_if   alu_req_if,
     VX_lsu_req_if   lsu_req_if,
     VX_csr_req_if   csr_req_if,
+`ifdef EXT_F_ENABLE
     VX_fpu_req_if   fpu_req_if,
+`endif
     VX_gpu_req_if   gpu_req_if    
 );
     wire [`NT_BITS-1:0] tid;
     wire alu_req_ready;
     wire lsu_req_ready;
     wire csr_req_ready;
+`ifdef EXT_F_ENABLE
     wire fpu_req_ready;
+`endif
     wire gpu_req_ready;
 
     VX_priority_encoder #(
@@ -108,7 +112,6 @@ module VX_instr_demux (
     );
 `else
     `UNUSED_VAR (gpr_rsp_if.rs3_data)
-    assign fpu_req_ready = 0;
 `endif
 
     // gpu unit
@@ -136,7 +139,9 @@ module VX_instr_demux (
         `EX_ALU: ready_r = alu_req_ready;
         `EX_LSU: ready_r = lsu_req_ready;
         `EX_CSR: ready_r = csr_req_ready;
+    `ifdef EXT_F_ENABLE
         `EX_FPU: ready_r = fpu_req_ready;
+    `endif
         `EX_GPU: ready_r = gpu_req_ready;
         default: ready_r = 1'b1; // ignore NOPs
         endcase

hw/rtl/VX_issue.v

@@ -18,7 +18,9 @@ module VX_issue #(
     VX_alu_req_if   alu_req_if,
     VX_lsu_req_if   lsu_req_if,    
     VX_csr_req_if   csr_req_if,
+`ifdef EXT_F_ENABLE
     VX_fpu_req_if   fpu_req_if,    
+`endif
     VX_gpu_req_if   gpu_req_if
 );
     VX_ibuffer_if ibuffer_if();
@@ -84,7 +86,9 @@ module VX_issue #(
         .alu_req_if (alu_req_if),
         .lsu_req_if (lsu_req_if),        
         .csr_req_if (csr_req_if),
+    `ifdef EXT_F_ENABLE
         .fpu_req_if (fpu_req_if),
+    `endif
         .gpu_req_if (gpu_req_if)
     );     
 
@@ -203,6 +207,7 @@ module VX_issue #(
             `PRINT_ARRAY1D(csr_req_if.rs1_data, `NUM_THREADS);
             $write("\n");
         end
+    `ifdef EXT_F_ENABLE
         if (fpu_req_if.valid && fpu_req_if.ready) begin
             $write("%t: core%0d-issue: wid=%0d, PC=%0h, ex=FPU, tmask=%b, rd=%0d, rs1_data=", 
                 $time, CORE_ID, fpu_req_if.wid, fpu_req_if.PC, fpu_req_if.tmask, fpu_req_if.rd);   
@@ -213,6 +218,7 @@ module VX_issue #(
             `PRINT_ARRAY1D(fpu_req_if.rs3_data, `NUM_THREADS);
             $write("\n");
         end
+    `endif
         if (gpu_req_if.valid && gpu_req_if.ready) begin
             $write("%t: core%0d-issue: wid=%0d, PC=%0h, ex=GPU, tmask=%b, rd=%0d, rs1_data=", 
                 $time, CORE_ID, gpu_req_if.wid, gpu_req_if.PC, gpu_req_if.tmask, gpu_req_if.rd);   

hw/rtl/VX_muldiv.v

@@ -83,9 +83,9 @@ module VX_muldiv (
     for (genvar i = 0; i < `NUM_THREADS; i++) begin
         wire [32:0] mul_in1 = {is_signed_mul_a & alu_in1[i][31], alu_in1[i]};
         wire [32:0] mul_in2 = {is_signed_mul_b & alu_in2[i][31], alu_in2[i]};
-    `IGNORE_WARNINGS_BEGIN
+    `IGNORE_UNUSED_BEGIN
         wire [65:0] mul_result_tmp;
-    `IGNORE_WARNINGS_END
+    `IGNORE_UNUSED_END
 
         VX_multiplier #(
             .WIDTHA  (33),

hw/rtl/VX_pipeline.v

@@ -116,7 +116,9 @@ module VX_pipeline #(
     VX_alu_req_if       alu_req_if();
     VX_lsu_req_if       lsu_req_if();
     VX_csr_req_if       csr_req_if();
+`ifdef EXT_F_ENABLE 
     VX_fpu_req_if       fpu_req_if(); 
+`endif
     VX_gpu_req_if       gpu_req_if();
     VX_writeback_if     writeback_if();     
     VX_wstall_if        wstall_if();
@@ -125,7 +127,9 @@ module VX_pipeline #(
     VX_commit_if        ld_commit_if();
     VX_commit_if        st_commit_if();
     VX_commit_if        csr_commit_if();  
+`ifdef EXT_F_ENABLE
     VX_commit_if        fpu_commit_if();     
+`endif
     VX_commit_if        gpu_commit_if();     
 
 `ifdef PERF_ENABLE
@@ -183,7 +187,9 @@ module VX_pipeline #(
         .alu_req_if     (alu_req_if),
         .lsu_req_if     (lsu_req_if),        
         .csr_req_if     (csr_req_if),
+    `ifdef EXT_F_ENABLE
         .fpu_req_if     (fpu_req_if),
+    `endif
         .gpu_req_if     (gpu_req_if)
     );
 
@@ -208,7 +214,9 @@ module VX_pipeline #(
         .alu_req_if     (alu_req_if),
         .lsu_req_if     (lsu_req_if),        
         .csr_req_if     (csr_req_if),
+    `ifdef EXT_F_ENABLE
         .fpu_req_if     (fpu_req_if),
+    `endif
         .gpu_req_if     (gpu_req_if),
 
         .warp_ctl_if    (warp_ctl_if),
@@ -217,7 +225,9 @@ module VX_pipeline #(
         .ld_commit_if   (ld_commit_if),        
         .st_commit_if   (st_commit_if),       
         .csr_commit_if  (csr_commit_if),
+    `ifdef EXT_F_ENABLE
         .fpu_commit_if  (fpu_commit_if),
+    `endif
         .gpu_commit_if  (gpu_commit_if),        
         
         .busy           (busy)
@@ -233,7 +243,9 @@ module VX_pipeline #(
         .ld_commit_if   (ld_commit_if),        
         .st_commit_if   (st_commit_if),
         .csr_commit_if  (csr_commit_if),
+    `ifdef EXT_F_ENABLE
         .fpu_commit_if  (fpu_commit_if),
+    `endif
         .gpu_commit_if  (gpu_commit_if),
         
         .writeback_if   (writeback_if),

hw/rtl/VX_platform.vh

@@ -13,9 +13,9 @@
     `define DEBUG_BLOCK(x)
 `endif
 
-`define DEBUG_BEGIN /* verilator lint_off UNUSED */ 
+`define IGNORE_UNUSED_BEGIN   /* verilator lint_off UNUSED */
 
-`define DEBUG_END   /* verilator lint_on UNUSED */     
+`define IGNORE_UNUSED_END     /* verilator lint_on UNUSED */
 
 `define IGNORE_WARNINGS_BEGIN /* verilator lint_off UNUSED */ \
                               /* verilator lint_off PINCONNECTEMPTY */ \

hw/rtl/VX_warp_sched.v

@@ -155,9 +155,9 @@ module VX_warp_sched #(
 
     // calculate active barrier status
 
-`IGNORE_WARNINGS_BEGIN
+`IGNORE_UNUSED_BEGIN
     wire [`NW_BITS:0] active_barrier_count;
-`IGNORE_WARNINGS_END
+`IGNORE_UNUSED_END
     assign active_barrier_count = $countones(barrier_stall_mask[warp_ctl_if.barrier.id]);
 
     assign reached_barrier_limit = (active_barrier_count[`NW_BITS-1:0] == warp_ctl_if.barrier.size_m1);

hw/rtl/VX_writeback.v

@@ -10,7 +10,9 @@ module VX_writeback #(
     VX_commit_if    alu_commit_if,
     VX_commit_if    ld_commit_if,  
     VX_commit_if    csr_commit_if,
+`ifdef EXT_F_ENABLE
     VX_commit_if    fpu_commit_if,
+`endif
 
     // outputs
     VX_writeback_if writeback_if
@@ -19,6 +21,11 @@ module VX_writeback #(
     `UNUSED_PARAM (CORE_ID)
 
     localparam DATAW = `NW_BITS + 32 + `NUM_THREADS + `NR_BITS + (`NUM_THREADS * 32) + 1;
+`ifdef EXT_F_ENABLE
+    localparam NUM_RSPS = 4;
+`else
+    localparam NUM_RSPS = 3;
+`endif
 
     wire wb_valid;
     wire [`NW_BITS-1:0] wb_wid;
@@ -28,28 +35,38 @@ module VX_writeback #(
     wire [`NUM_THREADS-1:0][31:0] wb_data;
     wire wb_eop;
 
-    wire [3:0][DATAW-1:0] rsp_data;
+    wire [NUM_RSPS-1:0] rsp_valid;
-    wire [3:0] rsp_ready;
+    wire [NUM_RSPS-1:0][DATAW-1:0] rsp_data;
+    wire [NUM_RSPS-1:0] rsp_ready;
     wire stall;
 
-    wire ld_valid  =  ld_commit_if.valid && ld_commit_if.wb;    
+    assign rsp_valid = {
-    wire fpu_valid = fpu_commit_if.valid && fpu_commit_if.wb;
+        csr_commit_if.valid && csr_commit_if.wb,
-    wire csr_valid = csr_commit_if.valid && csr_commit_if.wb;
+        alu_commit_if.valid && alu_commit_if.wb,
-    wire alu_valid = alu_commit_if.valid && alu_commit_if.wb;
         
-    assign rsp_data[0] = { ld_commit_if.wid,  ld_commit_if.PC,  ld_commit_if.tmask,  ld_commit_if.rd,  ld_commit_if.data,  ld_commit_if.eop};
+    `ifdef EXT_F_ENABLE
-    assign rsp_data[1] = {fpu_commit_if.wid, fpu_commit_if.PC, fpu_commit_if.tmask, fpu_commit_if.rd, fpu_commit_if.data, fpu_commit_if.eop};
+        fpu_commit_if.valid && fpu_commit_if.wb,
-    assign rsp_data[2] = {csr_commit_if.wid, csr_commit_if.PC, csr_commit_if.tmask, csr_commit_if.rd, csr_commit_if.data, csr_commit_if.eop};
+    `endif
-    assign rsp_data[3] = {alu_commit_if.wid, alu_commit_if.PC, alu_commit_if.tmask, alu_commit_if.rd, alu_commit_if.data, alu_commit_if.eop};
+        ld_commit_if.valid  && ld_commit_if.wb
+    };
+
+    assign rsp_data = {            
+        {csr_commit_if.wid, csr_commit_if.PC, csr_commit_if.tmask, csr_commit_if.rd, csr_commit_if.data, csr_commit_if.eop},
+        {alu_commit_if.wid, alu_commit_if.PC, alu_commit_if.tmask, alu_commit_if.rd, alu_commit_if.data, alu_commit_if.eop},
+    `ifdef EXT_F_ENABLE
+        {fpu_commit_if.wid, fpu_commit_if.PC, fpu_commit_if.tmask, fpu_commit_if.rd, fpu_commit_if.data, fpu_commit_if.eop},
+    `endif                        
+        { ld_commit_if.wid, ld_commit_if.PC,  ld_commit_if.tmask,  ld_commit_if.rd,  ld_commit_if.data,  ld_commit_if.eop}
+    };
     
     VX_stream_arbiter #(            
-        .NUM_REQS (4),
+        .NUM_REQS (NUM_RSPS),
         .DATAW    (DATAW),        
         .TYPE     ("X")
     ) rsp_arb (
         .clk       (clk),
         .reset     (reset),
-        .valid_in  ({alu_valid, csr_valid, fpu_valid, ld_valid}),
+        .valid_in  (rsp_valid),
         .data_in   (rsp_data),
         .ready_in  (rsp_ready),
         .valid_out (wb_valid),
@@ -58,9 +75,15 @@ module VX_writeback #(
     );
 
     assign  ld_commit_if.ready = rsp_ready[0] || ~ld_commit_if.wb;
+`ifdef EXT_F_ENABLE
     assign fpu_commit_if.ready = rsp_ready[1] || ~fpu_commit_if.wb;
+    assign alu_commit_if.ready = rsp_ready[2] || ~alu_commit_if.wb;
+    assign csr_commit_if.ready = rsp_ready[3] || ~csr_commit_if.wb;
+`else
+    assign alu_commit_if.ready = rsp_ready[1] || ~alu_commit_if.wb;
     assign csr_commit_if.ready = rsp_ready[2] || ~csr_commit_if.wb;
-    assign alu_commit_if.ready = rsp_ready[3] || ~alu_commit_if.wb;
+`endif
+    
     
     assign stall = ~writeback_if.ready && writeback_if.valid;
     

hw/rtl/afu/vortex_afu.sv

@@ -129,9 +129,9 @@ wire                      cmd_scope_write;
 
 // MMIO controller ////////////////////////////////////////////////////////////
 
-`IGNORE_WARNINGS_BEGIN
+`IGNORE_UNUSED_BEGIN
 t_ccip_c0_ReqMmioHdr mmio_hdr;
-`IGNORE_WARNINGS_END
+`IGNORE_UNUSED_END
 assign mmio_hdr = t_ccip_c0_ReqMmioHdr'(cp2af_sRxPort.c0.hdr);
 
 `STATIC_ASSERT(($bits(t_ccip_c0_ReqMmioHdr)-$bits(mmio_hdr.address)) == 12, ("Oops!"))
@@ -148,21 +148,6 @@ assign cmd_scope_write = cp2af_sRxPort.c0.mmioWrValid && (MMIO_SCOPE_WRITE == mm
 wire [COUT_QUEUE_DATAW-1:0] cout_q_dout;
 wire cout_q_full, cout_q_empty;
 
-/*
-`DEBUG_BEGIN
-wire cp2af_sRxPort_c0_mmioWrValid = cp2af_sRxPort.c0.mmioWrValid;
-wire cp2af_sRxPort_c0_mmioRdValid = cp2af_sRxPort.c0.mmioRdValid;
-wire cp2af_sRxPort_c0_rspValid = cp2af_sRxPort.c0.rspValid;
-wire cp2af_sRxPort_c1_rspValid = cp2af_sRxPort.c1.rspValid;
-wire cp2af_sRxPort_c0TxAlmFull = cp2af_sRxPort.c0TxAlmFull;
-wire cp2af_sRxPort_c1TxAlmFull = cp2af_sRxPort.c1TxAlmFull;
-wire[$bits(mmio_hdr.address)-1:0] mmio_hdr_address = mmio_hdr.address;
-wire[$bits(mmio_hdr.length)-1:0] mmio_hdr_length = mmio_hdr.length;
-wire[$bits(mmio_hdr.tid)-1:0] mmio_hdr_tid = mmio_hdr.tid;
-wire[$bits(cp2af_sRxPort.c0.hdr.mdata)-1:0] cp2af_sRxPort_c0_hdr_mdata = cp2af_sRxPort.c0.hdr.mdata;
-`DEBUG_END
-*/
-
 wire [2:0] cmd_type = (cp2af_sRxPort.c0.mmioWrValid 
                     && (MMIO_CMD_TYPE == mmio_hdr.address)) ? 3'(cp2af_sRxPort.c0.data) : 3'h0;
 

hw/rtl/cache/VX_bank.v

@@ -93,10 +93,10 @@ module VX_bank #(
     `UNUSED_PARAM (CORE_TAG_ID_BITS)
     
 `ifdef DBG_CACHE_REQ_INFO
-`IGNORE_WARNINGS_BEGIN
+`IGNORE_UNUSED_BEGIN
     wire [31:0]         debug_pc_sel, debug_pc_st0,  debug_pc_st1;
     wire [`NW_BITS-1:0] debug_wid_sel, debug_wid_st0, debug_wid_st1;
-`IGNORE_WARNINGS_END
+`IGNORE_UNUSED_END
 `endif    
 
     wire [NUM_PORTS-1:0] creq_pmask;

hw/rtl/cache/VX_data_access.v

@@ -18,15 +18,15 @@ module VX_data_access #(
     input wire                          reset,
 
 `ifdef DBG_CACHE_REQ_INFO
-`IGNORE_WARNINGS_BEGIN
+`IGNORE_UNUSED_BEGIN
     input wire[31:0]                    debug_pc,
     input wire[`NW_BITS-1:0]            debug_wid,
-`IGNORE_WARNINGS_END
+`IGNORE_UNUSED_END
 `endif
 
-`IGNORE_WARNINGS_BEGIN
+`IGNORE_UNUSED_BEGIN
     input wire[`LINE_ADDR_WIDTH-1:0]    addr,
-`IGNORE_WARNINGS_END
+`IGNORE_UNUSED_END
 
     // reading
     input wire                          readen,

hw/rtl/cache/VX_miss_resrv.v

@@ -25,12 +25,12 @@ module VX_miss_resrv #(
     input wire reset,
 
 `ifdef DBG_CACHE_REQ_INFO
-`IGNORE_WARNINGS_BEGIN
+`IGNORE_UNUSED_BEGIN
     input wire[31:0]                    deq_debug_pc,
     input wire[`NW_BITS-1:0]            deq_debug_wid,
     input wire[31:0]                    enq_debug_pc,
     input wire[`NW_BITS-1:0]            enq_debug_wid,
-`IGNORE_WARNINGS_END
+`IGNORE_UNUSED_END
 `endif
 
     // enqueue

hw/rtl/cache/VX_shared_mem.v

@@ -257,10 +257,10 @@ module VX_shared_mem #(
     );
 
 `ifdef DBG_CACHE_REQ_INFO
-`IGNORE_WARNINGS_BEGIN
+`IGNORE_UNUSED_BEGIN
     wire [NUM_BANKS-1:0][31:0]         debug_pc_st0, debug_pc_st1;
     wire [NUM_BANKS-1:0][`NW_BITS-1:0] debug_wid_st0, debug_wid_st1;
-`IGNORE_WARNINGS_END
+`IGNORE_UNUSED_END
 
     for (genvar i = 0; i < NUM_BANKS; ++i) begin
         if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin        
@@ -276,9 +276,9 @@ module VX_shared_mem #(
 `ifdef DBG_PRINT_CACHE_BANK
     
     reg is_multi_tag_req;
-`IGNORE_WARNINGS_BEGIN
+`IGNORE_UNUSED_BEGIN
     reg [CORE_TAG_WIDTH-1:0] core_req_tag_sel;
-`IGNORE_WARNINGS_END
+`IGNORE_UNUSED_END
 
     always @(*) begin                      
         core_req_tag_sel ='x;

hw/rtl/cache/VX_tag_access.v

@@ -18,10 +18,10 @@ module VX_tag_access #(
     input wire                          reset,
 
 `ifdef DBG_CACHE_REQ_INFO
-`IGNORE_WARNINGS_BEGIN
+`IGNORE_UNUSED_BEGIN
     input wire[31:0]                    debug_pc,
     input wire[`NW_BITS-1:0]            debug_wid,
-`IGNORE_WARNINGS_END
+`IGNORE_UNUSED_END
 `endif
     
     // read/fill

hw/rtl/interfaces/VX_fpu_req_if.v

@@ -3,10 +3,6 @@
 
 `include "VX_define.vh"
 
-`ifndef EXTF_F_ENABLE
-    `IGNORE_WARNINGS_BEGIN
-`endif
-
 interface VX_fpu_req_if ();
 
     wire                    valid;

hw/rtl/interfaces/VX_writeback_if.v

@@ -9,13 +9,11 @@ interface VX_writeback_if ();
 
     wire [`NUM_THREADS-1:0]         tmask;
     wire [`NW_BITS-1:0]             wid; 
-`IGNORE_WARNINGS_BEGIN
     wire [31:0]                     PC;
-`IGNORE_WARNINGS_END
     wire [`NR_BITS-1:0]             rd;
     wire [`NUM_THREADS-1:0][31:0]   data;
-
     wire                            eop;
+    
     wire                            ready;
 
 endinterface

hw/rtl/libs/VX_fifo_queue.v

@@ -95,9 +95,7 @@ module VX_fifo_queue #(
                     used_r <= used_r + ADDRW'($signed(2'(push) - 2'(pop)));
                 end else begin 
                     // (SIZE == 2);
-                `IGNORE_WARNINGS_BEGIN
+                    used_r[0] <= used_r[0] ^ (push ^ pop);
-                    used_r <= used_r ^ (push ^ pop);
-                `IGNORE_WARNINGS_END
                 end                
             end                   
         end

hw/rtl/libs/VX_onehot_encoder.v

@@ -67,10 +67,7 @@ module VX_onehot_encoder #(
         for (genvar j = 0; j < LN; ++j) begin
             wire [N-1:0] mask;
             for (genvar i = 0; i < N; ++i) begin
-            `IGNORE_WARNINGS_BEGIN
+                assign mask[i] = i[j];
-                wire [LN-1:0] i_w = i;
-            `IGNORE_WARNINGS_END
-                assign mask[i] = i_w[j];
             end
             assign data_out[j] = |(mask & data_in);
         end

hw/rtl/libs/VX_skid_buffer.v

@@ -115,9 +115,7 @@ module VX_skid_buffer #(
                         ready_in_r  <= 1;
                         valid_out_r <= rd_ptr_r;
                     end
-                `IGNORE_WARNINGS_BEGIN
                     rd_ptr_r <= rd_ptr_r ^ (push ^ pop);
-                `IGNORE_WARNINGS_END   
                 end                   
             end