unused variables refactoring

hw/rtl/cache/VX_bank.v

@@ -93,10 +93,10 @@ module VX_bank #(
     `UNUSED_PARAM (CORE_TAG_ID_BITS)
     
 `ifdef DBG_CACHE_REQ_INFO
-`IGNORE_WARNINGS_BEGIN
+`IGNORE_UNUSED_BEGIN
     wire [31:0]         debug_pc_sel, debug_pc_st0,  debug_pc_st1;
     wire [`NW_BITS-1:0] debug_wid_sel, debug_wid_st0, debug_wid_st1;
-`IGNORE_WARNINGS_END
+`IGNORE_UNUSED_END
 `endif    
 
     wire [NUM_PORTS-1:0] creq_pmask;

hw/rtl/cache/VX_data_access.v

@@ -18,15 +18,15 @@ module VX_data_access #(
     input wire                          reset,
 
 `ifdef DBG_CACHE_REQ_INFO
-`IGNORE_WARNINGS_BEGIN
+`IGNORE_UNUSED_BEGIN
     input wire[31:0]                    debug_pc,
     input wire[`NW_BITS-1:0]            debug_wid,
-`IGNORE_WARNINGS_END
+`IGNORE_UNUSED_END
 `endif
 
-`IGNORE_WARNINGS_BEGIN
+`IGNORE_UNUSED_BEGIN
     input wire[`LINE_ADDR_WIDTH-1:0]    addr,
-`IGNORE_WARNINGS_END
+`IGNORE_UNUSED_END
 
     // reading
     input wire                          readen,

hw/rtl/cache/VX_miss_resrv.v

@@ -25,12 +25,12 @@ module VX_miss_resrv #(
     input wire reset,
 
 `ifdef DBG_CACHE_REQ_INFO
-`IGNORE_WARNINGS_BEGIN
+`IGNORE_UNUSED_BEGIN
     input wire[31:0]                    deq_debug_pc,
     input wire[`NW_BITS-1:0]            deq_debug_wid,
     input wire[31:0]                    enq_debug_pc,
     input wire[`NW_BITS-1:0]            enq_debug_wid,
-`IGNORE_WARNINGS_END
+`IGNORE_UNUSED_END
 `endif
 
     // enqueue

hw/rtl/cache/VX_shared_mem.v

@@ -257,10 +257,10 @@ module VX_shared_mem #(
     );
 
 `ifdef DBG_CACHE_REQ_INFO
-`IGNORE_WARNINGS_BEGIN
+`IGNORE_UNUSED_BEGIN
     wire [NUM_BANKS-1:0][31:0]         debug_pc_st0, debug_pc_st1;
     wire [NUM_BANKS-1:0][`NW_BITS-1:0] debug_wid_st0, debug_wid_st1;
-`IGNORE_WARNINGS_END
+`IGNORE_UNUSED_END
 
     for (genvar i = 0; i < NUM_BANKS; ++i) begin
         if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin        
@@ -276,9 +276,9 @@ module VX_shared_mem #(
 `ifdef DBG_PRINT_CACHE_BANK
     
     reg is_multi_tag_req;
-`IGNORE_WARNINGS_BEGIN
+`IGNORE_UNUSED_BEGIN
     reg [CORE_TAG_WIDTH-1:0] core_req_tag_sel;
-`IGNORE_WARNINGS_END
+`IGNORE_UNUSED_END
 
     always @(*) begin                      
         core_req_tag_sel ='x;

hw/rtl/cache/VX_tag_access.v

@@ -18,10 +18,10 @@ module VX_tag_access #(
     input wire                          reset,
 
 `ifdef DBG_CACHE_REQ_INFO
-`IGNORE_WARNINGS_BEGIN
+`IGNORE_UNUSED_BEGIN
     input wire[31:0]                    debug_pc,
     input wire[`NW_BITS-1:0]            debug_wid,
-`IGNORE_WARNINGS_END
+`IGNORE_UNUSED_END
 `endif
     
     // read/fill