unused variables refactoring

2021-08-05 01:46:26 -07:00
parent 80f62e8a41
commit 7b8fe11e6a
22 changed files with 140 additions and 105 deletions
--- a/hw/rtl/VX_muldiv.v
+++ b/hw/rtl/VX_muldiv.v
@@ -83,9 +83,9 @@ module VX_muldiv (
    for (genvar i = 0; i < `NUM_THREADS; i++) begin
        wire [32:0] mul_in1 = {is_signed_mul_a & alu_in1[i][31], alu_in1[i]};
        wire [32:0] mul_in2 = {is_signed_mul_b & alu_in2[i][31], alu_in2[i]};
-    `IGNORE_WARNINGS_BEGIN
+    `IGNORE_UNUSED_BEGIN
        wire [65:0] mul_result_tmp;
-    `IGNORE_WARNINGS_END
+    `IGNORE_UNUSED_END

        VX_multiplier #(
            .WIDTHA  (33),