diff --git a/docs/Vortex.pptx b/docs/Vortex.pptx index fc73d9ce..89e1128e 100755 Binary files a/docs/Vortex.pptx and b/docs/Vortex.pptx differ diff --git a/rtl/cache/Makefile b/rtl/cache/Makefile index e1247633..3e92307a 100644 --- a/rtl/cache/Makefile +++ b/rtl/cache/Makefile @@ -2,7 +2,7 @@ all: RUNFILE VERILATOR: - verilator --compiler gcc --Wno-UNOPTFLAT -Wall --trace -cc VX_d_cache_encapsulate.v -Iinterfaces/ --exe d_cache_test_bench.cpp -CFLAGS -std=c++11 + verilator --compiler gcc --Wno-UNOPTFLAT -Wall --trace -cc VX_d_cache_encapsulate.v -Irtl --exe d_cache_test_bench.cpp -CFLAGS -std=c++11 RUNFILE: VERILATOR (cd obj_dir && make -j -f VVX_d_cache_encapsulate.mk) diff --git a/rtl/cache/VX_d_cache_encapsulate.v b/rtl/cache/VX_d_cache_encapsulate.v index 8549ec52..a35c322a 100644 --- a/rtl/cache/VX_d_cache_encapsulate.v +++ b/rtl/cache/VX_d_cache_encapsulate.v @@ -1,5 +1,5 @@ -`include "VX_define.v" +`include "../VX_define.v" // `define NUM_WORDS_PER_BLOCK 4 diff --git a/simX/obj_dir/Vcache_simX b/simX/obj_dir/Vcache_simX new file mode 100755 index 00000000..c373f08a Binary files /dev/null and b/simX/obj_dir/Vcache_simX differ diff --git a/simX/obj_dir/Vcache_simX.cpp b/simX/obj_dir/Vcache_simX.cpp new file mode 100644 index 00000000..4f758862 --- /dev/null +++ b/simX/obj_dir/Vcache_simX.cpp @@ -0,0 +1,5493 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Vcache_simX.h for the primary calling header + +#include "Vcache_simX.h" // For This +#include "Vcache_simX__Syms.h" + + +//-------------------- +// STATIC VARIABLES + +VL_ST_SIG8(Vcache_simX::__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[16],1,0); +VL_ST_SIG8(Vcache_simX::__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[16],0,0); +VL_ST_SIG(Vcache_simX::__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[16],31,0); +VL_ST_SIG8(Vcache_simX::__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[16],1,0); +VL_ST_SIG8(Vcache_simX::__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[16],0,0); +VL_ST_SIG(Vcache_simX::__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[16],31,0); +VL_ST_SIG8(Vcache_simX::__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[16],1,0); +VL_ST_SIG8(Vcache_simX::__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[16],0,0); +VL_ST_SIG(Vcache_simX::__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[16],31,0); +VL_ST_SIG8(Vcache_simX::__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[16],1,0); +VL_ST_SIG8(Vcache_simX::__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[16],0,0); +VL_ST_SIG(Vcache_simX::__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[16],31,0); +VL_ST_SIG8(Vcache_simX::__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[16],1,0); +VL_ST_SIG8(Vcache_simX::__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[16],0,0); +VL_ST_SIG(Vcache_simX::__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[16],31,0); +VL_ST_SIG8(Vcache_simX::__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[16],1,0); +VL_ST_SIG8(Vcache_simX::__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[16],0,0); +VL_ST_SIG(Vcache_simX::__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[16],31,0); +VL_ST_SIG8(Vcache_simX::__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index[16],1,0); +VL_ST_SIG8(Vcache_simX::__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found[16],0,0); +VL_ST_SIG(Vcache_simX::__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i[16],31,0); +VL_ST_SIG8(Vcache_simX::__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index[16],1,0); +VL_ST_SIG8(Vcache_simX::__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found[16],0,0); +VL_ST_SIG(Vcache_simX::__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[16],31,0); +VL_ST_SIG8(Vcache_simX::__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[16],1,0); +VL_ST_SIG8(Vcache_simX::__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[16],0,0); +VL_ST_SIG(Vcache_simX::__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[16],31,0); + +//-------------------- + +VL_CTOR_IMP(Vcache_simX) { + Vcache_simX__Syms* __restrict vlSymsp = __VlSymsp = new Vcache_simX__Syms(this, name()); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + VL_CELL (__PVT__cache_simX__DOT__VX_dram_req_rsp_icache, Vcache_simX_VX_dram_req_rsp_inter__N1_NB4); + VL_CELL (__PVT__cache_simX__DOT__VX_dcache_req, Vcache_simX_VX_dcache_request_inter); + VL_CELL (__PVT__cache_simX__DOT__VX_dram_req_rsp, Vcache_simX_VX_dram_req_rsp_inter__N4_NB4); + VL_CELL (__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi8); + VL_CELL (__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi8); + VL_CELL (__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi8); + VL_CELL (__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure, Vcache_simX_VX_Cache_Bank__pi8); + // Reset internal values + + // Reset structure values + _ctor_var_reset(); +} + +void Vcache_simX::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +Vcache_simX::~Vcache_simX() { + delete __VlSymsp; __VlSymsp=NULL; +} + +//-------------------- + + +void Vcache_simX::eval() { + VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vcache_simX::eval\n"); ); + Vcache_simX__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +#ifdef VL_DEBUG + // Debug assertions + _eval_debug_assertions(); +#endif // VL_DEBUG + // Initialize + if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp); + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + while (VL_LIKELY(__Vchange)) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n");); + vlSymsp->__Vm_activity = true; + _eval(vlSymsp); + __Vchange = _change_request(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge"); + } +} + +void Vcache_simX::_eval_initial_loop(Vcache_simX__Syms* __restrict vlSymsp) { + vlSymsp->__Vm_didInit = true; + _eval_initial(vlSymsp); + vlSymsp->__Vm_activity = true; + int __VclockLoop = 0; + QData __Vchange = 1; + while (VL_LIKELY(__Vchange)) { + _eval_settle(vlSymsp); + _eval(vlSymsp); + __Vchange = _change_request(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge"); + } +} + +//-------------------- +// Internal Methods + +VL_INLINE_OPT void Vcache_simX::_combo__TOP__1(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_combo__TOP__1\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read + = ((IData)(vlTOPp->in_icache_valid_pc_addr) + ? ((IData)(vlTOPp->in_icache_valid_pc_addr) + ? 2U : 7U) : 7U); + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid + = ((0xeU & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) + | vlTOPp->in_dcache_in_valid[0U]); + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid + = ((0xdU & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) + | (vlTOPp->in_dcache_in_valid[1U] << 1U)); + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid + = ((0xbU & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) + | (vlTOPp->in_dcache_in_valid[2U] << 2U)); + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid + = ((7U & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) + | (vlTOPp->in_dcache_in_valid[3U] << 3U)); +} + +void Vcache_simX::_settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_settle__TOP__2\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + VL_SIGW(__Vtemp19,127,0,4); + VL_SIGW(__Vtemp20,127,0,4); + VL_SIGW(__Vtemp21,127,0,4); + VL_SIGW(__Vtemp22,127,0,4); + // Body + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read + = ((IData)(vlTOPp->in_icache_valid_pc_addr) + ? ((IData)(vlTOPp->in_icache_valid_pc_addr) + ? 2U : 7U) : 7U); + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid + = ((0xeU & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) + | vlTOPp->in_dcache_in_valid[0U]); + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid + = ((0xdU & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) + | (vlTOPp->in_dcache_in_valid[1U] << 1U)); + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid + = ((0xbU & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) + | (vlTOPp->in_dcache_in_valid[2U] << 2U)); + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid + = ((7U & (IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid)) + | (vlTOPp->in_dcache_in_valid[3U] << 3U)); + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + = vlTOPp->in_dcache_in_address[0U]; + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + = vlTOPp->in_dcache_in_address[1U]; + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + = vlTOPp->in_dcache_in_address[2U]; + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + = vlTOPp->in_dcache_in_address[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way)) + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way)) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U] << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[0U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[1U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[2U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[3U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[4U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[5U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[6U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[7U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3fffff800000) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [0U]))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x7fffff) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [0U])) << 0x17U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)) + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [0U] << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid) + : (IData)(vlTOPp->in_icache_valid_pc_addr)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid + = ((IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid) + & VL_NEGATE_I((IData)((0xffU == (0xffU & + ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U))))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid + = ((IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid) + & VL_NEGATE_I((IData)((0xffU != (0xffU & + ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U))))))); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 1U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 1U; + } + // ALWAYS at ../rtl/cache/VX_cache_bank_valid.v:24 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1 + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid)) + ? (IData)(vlTOPp->in_dcache_mem_read) : 7U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid)) + ? (IData)(vlTOPp->in_dcache_mem_write) : 7U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) + | (1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) + | (2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) + | (4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) + | (8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write + = ((7U != (IData)(vlTOPp->in_dcache_mem_write)) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)) + ? (IData)(vlTOPp->in_dcache_mem_write) : 7U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)) + ? (IData)(vlTOPp->in_dcache_mem_read) : 7U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid + = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid)) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid) + : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid)); + // ALWAYS at ../rtl/VX_priority_encoder_w_mask.v:17 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = 0U; + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = 1U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests)) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests) + : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)); + // ALWAYS at ../rtl/cache/VX_cache_bank_valid.v:18 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks + = (((~ ((IData)(1U) << (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U]))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) + | ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid)) + << (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U]))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks + = (((~ ((IData)(1U) << (0xfU & ((IData)(1U) + + (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U]))))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) + | ((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) + >> 1U)) << (0xfU & ((IData)(1U) + + (0xcU & + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U]))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks + = (((~ ((IData)(1U) << (0xfU & ((IData)(2U) + + (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U]))))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) + | ((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) + >> 2U)) << (0xfU & ((IData)(2U) + + (0xcU & + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U]))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks + = (((~ ((IData)(1U) << (0xfU & ((IData)(3U) + + (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U]))))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) + | ((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) + >> 3U)) << (0xfU & ((IData)(3U) + + (0xcU & + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U]))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr + : (vlTOPp->in_icache_pc_addr >> (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index) + << 5U))))); + // ALWAYS at ../rtl/shared_memory/VX_bank_valids.v:22 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfffeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & (0U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 2U)))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfffdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffffeU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & ((0U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + >> 2U)))) + << 1U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfffbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffffcU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & ((0U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + >> 2U)))) + << 2U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfff7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffff8U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & ((0U == (3U & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + >> 2U))) + << 3U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xffefU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & (1U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 2U))))) + << 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xffdfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffffe0U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 4U) & ((1U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + >> 2U)))) + << 5U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xffbfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffffc0U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 4U) & ((1U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + >> 2U)))) + << 6U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xff7fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffff80U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 4U) & ((1U == (3U + & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + >> 2U))) + << 7U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfeffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & (2U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 2U))))) + << 8U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfdffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffe00U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 8U) & ((2U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + >> 2U)))) + << 9U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfbffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffc00U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 8U) & ((2U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + >> 2U)))) + << 0xaU)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xf7ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffff800U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 8U) & ((2U == (3U + & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + >> 2U))) + << 0xbU)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xefffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & (3U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 2U))))) + << 0xcU)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xdfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffe000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 0xcU) & ((3U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + >> 2U)))) + << 0xdU)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xbfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffc000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 0xcU) & ((3U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + >> 2U)))) + << 0xeU)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0x7fffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffff8000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 0xcU) & ((3U == (3U + & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + >> 2U))) + << 0xfU)))); + // ALWAYS at ../rtl/VX_priority_encoder_w_mask.v:16 + vlTOPp->__Vtableidx6 = (0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index + = vlTOPp->__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index + [vlTOPp->__Vtableidx6]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found + = vlTOPp->__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found + [vlTOPp->__Vtableidx6]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i + = vlTOPp->__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i + [vlTOPp->__Vtableidx6]; + // ALWAYS at ../rtl/VX_priority_encoder_w_mask.v:16 + vlTOPp->__Vtableidx7 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index + = vlTOPp->__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index + [vlTOPp->__Vtableidx7]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found + = vlTOPp->__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found + [vlTOPp->__Vtableidx7]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i + = vlTOPp->__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i + [vlTOPp->__Vtableidx7]; + // ALWAYS at ../rtl/VX_priority_encoder_w_mask.v:16 + vlTOPp->__Vtableidx8 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 8U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index + = vlTOPp->__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index + [vlTOPp->__Vtableidx8]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found + = vlTOPp->__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found + [vlTOPp->__Vtableidx8]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i + = vlTOPp->__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i + [vlTOPp->__Vtableidx8]; + // ALWAYS at ../rtl/VX_priority_encoder_w_mask.v:16 + vlTOPp->__Vtableidx9 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 0xcU)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index + = vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index + [vlTOPp->__Vtableidx9]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found + = vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found + [vlTOPp->__Vtableidx9]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i + = vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i + [vlTOPp->__Vtableidx9]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access + = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem + = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way)) + | (1U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) + & ((0x7fffffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way)) + == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U)))) ? 1U + : 0U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way)) + | (2U & (((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x7fffffU & (IData)( + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way + >> 0x17U))) + == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U)))) + ? 1U : 0U) << 1U))); + // ALWAYS at ../rtl/VX_countones.v:14 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids = 0U; + if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + } + if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + } + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + } + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + } + // ALWAYS at ../rtl/VX_countones.v:14 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids = 0U; + if ((0x80U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids))); + } + if ((0x40U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids))); + } + if ((0x20U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids))); + } + if ((0x10U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids))); + } + // ALWAYS at ../rtl/VX_countones.v:14 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids = 0U; + if ((0x800U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids))); + } + if ((0x400U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids))); + } + if ((0x200U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids))); + } + if ((0x100U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids))); + } + // ALWAYS at ../rtl/VX_countones.v:14 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids = 0U; + if ((0x8000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids))); + } + if ((0x4000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids))); + } + if ((0x2000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids))); + } + if ((0x1000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids))); + } + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:16 + vlTOPp->__Vtableidx1 = (0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index + = vlTOPp->__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index + [vlTOPp->__Vtableidx1]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found + = vlTOPp->__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found + [vlTOPp->__Vtableidx1]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i + = vlTOPp->__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i + [vlTOPp->__Vtableidx1]; + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:16 + vlTOPp->__Vtableidx2 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index + = vlTOPp->__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index + [vlTOPp->__Vtableidx2]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found + = vlTOPp->__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found + [vlTOPp->__Vtableidx2]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i + = vlTOPp->__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i + [vlTOPp->__Vtableidx2]; + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:16 + vlTOPp->__Vtableidx3 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 8U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index + = vlTOPp->__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index + [vlTOPp->__Vtableidx3]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found + = vlTOPp->__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found + [vlTOPp->__Vtableidx3]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i + = vlTOPp->__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i + [vlTOPp->__Vtableidx3]; + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:16 + vlTOPp->__Vtableidx4 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 0xcU)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index + = vlTOPp->__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index + [vlTOPp->__Vtableidx4]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found + = vlTOPp->__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found + [vlTOPp->__Vtableidx4]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i + = vlTOPp->__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i + [vlTOPp->__Vtableidx4]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank + = ((0xfff0U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) + | (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found) + ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index)) + : 0U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank + = ((0xfcU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank + = ((0xff0fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) + | (0xf0U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found) + ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index)) + : 0U) << 4U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank + = ((0xf3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank + = ((0xf0ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) + | (0xf00U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found) + ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index)) + : 0U) << 8U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank + = ((0xcfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index) + << 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank + = ((0xfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) + | (0xf000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found) + ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index)) + : 0U) << 0xcU))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found) + << 3U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank + = ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index) + << 6U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[0U] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[1U] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[2U] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[3U] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we + = ((0xfff0U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? 0xfU : 0U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we + = ((0xff0fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? 0xfU : 0U) << 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? 0xfU : 0U) << 8U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we + = ((0xfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? 0xfU : 0U) << 0xcU)); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 1U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | (1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | ((1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids)) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | ((1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids)) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | ((1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids)) + << 3U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num + = ((0xfcU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num + = ((0xf3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num + = ((0xcfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index) + << 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num + = ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index) + << 6U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found) + << 3U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 1U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 2U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 3U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))])); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))])); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))])); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update) + : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index)); + // ALWAYS at ../rtl/shared_memory/VX_priority_encoder_sm.v:88 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) + | ((IData)(1U) << (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) + | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 2U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) + | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 4U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) + | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 6U)))); + __Vtemp19[0U] = 0U; + __Vtemp19[1U] = 0U; + __Vtemp19[2U] = 0U; + __Vtemp19[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[0U] + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? __Vtemp19[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num))] + : 0U); + __Vtemp20[0U] = 0U; + __Vtemp20[1U] = 0U; + __Vtemp20[2U] = 0U; + __Vtemp20[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[1U] + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? __Vtemp20[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 2U))] : 0U); + __Vtemp21[0U] = 0U; + __Vtemp21[1U] = 0U; + __Vtemp21[2U] = 0U; + __Vtemp21[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[2U] + = ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? __Vtemp21[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 4U))] : 0U); + __Vtemp22[0U] = 0U; + __Vtemp22[1U] = 0U; + __Vtemp22[2U] = 0U; + __Vtemp22[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[3U] + = ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? __Vtemp22[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 6U))] : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num))] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 2U))] : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + = ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 4U))] : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + = ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 6U))] : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write + = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write + = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid) + >> 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write + = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid) + >> 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write + = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid) + >> 3U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + = ((0xffff0000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way) + | (0xffffU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + ? 0U : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + = ((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way) + | (0xffff0000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we) + : 0U) << 0x10U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual + = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))) + ? (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + + (4U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))) + : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? ((((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U + : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) - (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))) + >> 8U) : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? ((((0U == (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U))] + >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))) + >> 0x10U) : ((((0U + == + (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U + : + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + + (4U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (4U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U))] + >> + (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))) + >> 0x18U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + = (0x7fffffU & ((0x2dU >= (0x3fU & ((IData)(0x17U) + * (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))) + ? (IData)((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way + >> (0x3fU & ((IData)(0x17U) + * (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))))) + : 0U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use + = (1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) + >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[1U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][1U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[2U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][2U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[3U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][3U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[4U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[5U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][1U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[6U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][2U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[7U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][3U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[8U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[9U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][1U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xaU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][2U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xbU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][3U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xcU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xdU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][1U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xeU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][2U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xfU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][3U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) + >> 1U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access) + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U)))) & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__new_left_requests + = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests)) + ? ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))) + : ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual)))); + // ALWAYS at ../rtl/shared_memory/VX_shared_memory.v:118 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[4U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[5U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[6U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[7U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[8U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[9U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xaU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xbU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xcU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xdU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xeU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xfU] = 0U; + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfffff80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we + = ((0xfcU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) + | (3U & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 0x1cU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 4U)))); + VL_ASSIGNSEL_WIII(32,(0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + << 1U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[0U]); + } + } + } + } else { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfffff80U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2)); + VL_ASSIGNSEL_WIII(32, + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + << 5U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 4U))]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) + | ((IData)(1U) + << (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)))); + } + } + } + } + } + } + } + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfffc07fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1) + << 7U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we + = ((0xf3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) + | (0xcU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 2U))))); + VL_ASSIGNSEL_WIII(32,(0x1ffU + & ((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U)))), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[1U]); + } + } + } + } else { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfffc07fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2) + << 7U)); + VL_ASSIGNSEL_WIII(32, + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + << 2U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, + (((0U + == + (0x1fU + & ((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))))) + ? 0U + : + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + (0xfU + & (((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))) + >> 5U))] + >> + (0x1fU + & ((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) + | ((IData)(1U) + << (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 3U)))); + } + } + } + } + } + } + } + if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfe03fffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1) + << 0xeU)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we + = ((0xcfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) + | (0x30U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U])); + VL_ASSIGNSEL_WIII(32,(0x1ffU + & ((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U)))), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[2U]); + } + } + } + } else { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfe03fffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2) + << 0xeU)); + VL_ASSIGNSEL_WIII(32, + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 1U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, + (((0U + == + (0x1fU + & ((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))))) + ? 0U + : + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + (0xfU + & (((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))) + >> 5U))] + >> + (0x1fU + & ((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) + | ((IData)(1U) + << (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 6U)))); + } + } + } + } + } + } + } + if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 0x18U)))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 + = (0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 6U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0x1fffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1) + << 0x15U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we + = ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) + | (0xc0U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 2U))); + VL_ASSIGNSEL_WIII(32,(0x1ffU + & ((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U)))), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[3U]); + } + } + } + } else { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 + = (0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 6U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0x1fffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2) + << 0x15U)); + VL_ASSIGNSEL_WIII(32, + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 4U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, + (((0U + == + (0x1fU + & ((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))))) + ? 0U + : + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + (0xfU + & (((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))) + >> 5U))] + >> + (0x1fU + & ((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) + | ((IData)(1U) + << (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 9U)))); + } + } + } + } + } + } + } + // ALWAYS at ../rtl/cache/VX_d_cache.v:183 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read = 0U; + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read + = (((~ ((IData)(0xffffffffU) << (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index) + << 5U)))) + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffffff00U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffff0000U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)))) + : 0U) << (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index) + << 5U)))); + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[0U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank; + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = 0U; + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = 1U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state + = (0xfU & (((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss)) + ? 1U : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + ? 2U : (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready))) + ? 2U : 0U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) + ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index)) + : 0U) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask + [0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__update_global_way_to_evict + = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank))); + vlTOPp->out_icache_stall = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))); +} + +VL_INLINE_OPT void Vcache_simX::_settle__TOP__3(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_settle__TOP__3\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb)) + | (1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[1U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[2U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[3U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[0U] + = (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)) + | (((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU)))) & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[0U] + = ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb)) + | (2U & (((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)) + << 1U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[4U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[5U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[6U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[7U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[1U] + = (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)) + | ((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU)))) & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use)) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[1U] + = ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb)) + | (4U & (((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)) + << 2U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[8U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[9U] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xaU] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xbU] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[2U] + = (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)) + | ((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU)))) & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use)) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[2U] + = ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb)) + | (8U & (((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual)) + << 3U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xcU] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xdU] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xeU] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata[0xfU] + = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[3U] + = (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)) + | ((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU)))) & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use)) + << 3U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[3U] + = ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[0U] + = (0xfU & VL_NEGATE_I((IData)((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[1U] + = (0xfU & VL_NEGATE_I((IData)((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) + >> 1U))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[2U] + = (0xfU & VL_NEGATE_I((IData)((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) + >> 2U))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[3U] + = (0xfU & VL_NEGATE_I((IData)((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) + >> 3U))))); + // ALWAYS at ../rtl/cache/VX_d_cache.v:183 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[3U] = 0U; + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + << 5U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[0U]); + } + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + << 3U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[1U]); + } + if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + << 1U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[2U]); + } + if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 1U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[3U]); + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state + = (0xfU & (((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss))) + ? 1U : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? 2U : (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready))) + ? 2U : 0U)))); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:16 + vlTOPp->__Vtableidx5 = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index + = vlTOPp->__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index + [vlTOPp->__Vtableidx5]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found + = vlTOPp->__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found + [vlTOPp->__Vtableidx5]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i + = vlTOPp->__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i + [vlTOPp->__Vtableidx5]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank + = ((0xfff0U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank) + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask + [0U])); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank + = ((0xff0fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank)) + | (0xfffffff0U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank) + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask + [1U] << 4U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank + = ((0xf0ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank)) + | (0xffffff00U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank) + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask + [2U] << 8U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank + = ((0xfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank)) + | (0xfffff000U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank) + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask + [3U] << 0xcU)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__update_global_way_to_evict + = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state))); + // ALWAYS at ../rtl/cache/VX_d_cache.v:203 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual + = (0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual + = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank) + >> 4U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual + = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank) + >> 8U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual + = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank) + >> 0xcU))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[0U] + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[0U] + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[1U] + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[1U] + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[1U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[2U] + = ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[2U] + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[2U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[3U] + = ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read[3U] + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[3U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual))); + vlTOPp->out_dcache_stall = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))); +} + +VL_INLINE_OPT void Vcache_simX::_sequent__TOP__4(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_sequent__TOP__4\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + VL_SIG8(__Vdly__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state,3,0); + VL_SIG8(__Vdly__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict,0,0); + VL_SIG8(__Vdly__cache_simX__DOT__dmem_controller__DOT__icache__DOT__state,3,0); + VL_SIG8(__Vdly__cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict,0,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0,0,0); + VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32,0,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32,0,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32,0,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32,0,0); + VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32,6,0); + VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32,7,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32,0,0); + VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33,6,0); + VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33,7,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33,0,0); + VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34,6,0); + VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34,7,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34,0,0); + VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35,6,0); + VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35,7,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35,0,0); + VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36,6,0); + VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36,7,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36,0,0); + VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37,6,0); + VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37,7,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37,0,0); + VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38,6,0); + VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38,7,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38,0,0); + VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39,6,0); + VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39,7,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39,0,0); + VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40,6,0); + VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40,7,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40,0,0); + VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41,6,0); + VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41,7,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41,0,0); + VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42,6,0); + VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42,7,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42,0,0); + VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43,6,0); + VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43,7,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43,0,0); + VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44,6,0); + VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44,7,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44,0,0); + VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45,6,0); + VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45,7,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45,0,0); + VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46,6,0); + VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46,7,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46,0,0); + VL_SIG8(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47,6,0); + VL_SIG8(__Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47,7,0); + VL_SIG8(__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47,0,0); 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+ __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 0U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 0U; + __Vdly__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict; + // ALWAYS at ../rtl/shared_memory/VX_shared_memory_block.v:36 + if (vlTOPp->reset) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind = 0U; + while (VL_GTS_III(1,32,32, 0x80U, vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind)) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind + = ((IData)(1U) + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind); + } + } else { + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 5U)), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)], + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we))]); + } + } + // ALWAYS at ../rtl/shared_memory/VX_shared_memory_block.v:36 + if (vlTOPp->reset) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind = 0U; + while (VL_GTS_III(1,32,32, 0x80U, vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind)) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind + = ((IData)(1U) + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind); + } + } else { + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 3U)), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))], + (((0U == (0x1fU & ((IData)(0x80U) + + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 3U))))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[ + ((IData)(1U) + + (0xfU & + (((IData)(0x80U) + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 3U))) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x80U) + + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 3U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[ + (0xfU & (((IData)(0x80U) + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 3U))) + >> 5U))] + >> (0x1fU & ((IData)(0x80U) + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 3U))))))); + } + } + // ALWAYS at ../rtl/shared_memory/VX_shared_memory_block.v:36 + if (vlTOPp->reset) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind = 0U; + while (VL_GTS_III(1,32,32, 0x80U, vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind)) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind + = ((IData)(1U) + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind); + } + } else { + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 1U)), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))], + (((0U == (0x1fU & ((IData)(0x100U) + + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 1U))))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[ + ((IData)(1U) + + (0xfU & + (((IData)(0x100U) + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 1U))) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x100U) + + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 1U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[ + (0xfU & (((IData)(0x100U) + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 1U))) + >> 5U))] + >> (0x1fU & ((IData)(0x100U) + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + << 1U))))))); + } + } + // ALWAYS at ../rtl/shared_memory/VX_shared_memory_block.v:36 + if (vlTOPp->reset) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind = 0U; + while (VL_GTS_III(1,32,32, 0x80U, vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind)) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[(0x7fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind)][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind + = ((IData)(1U) + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind); + } + } else { + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 1U)), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))], + (((0U == (0x1fU & ((IData)(0x180U) + + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 1U))))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[ + ((IData)(1U) + + (0xfU & + (((IData)(0x180U) + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 1U))) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x180U) + + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 1U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[ + (0xfU & (((IData)(0x180U) + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 1U))) + >> 5U))] + >> (0x1fU & ((IData)(0x180U) + + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 1U))))))); + } + } + // ALWAYS at cache_simX.v:93 + if (vlTOPp->reset) { + vlTOPp->cache_simX__DOT__icache_i_m_ready = 0U; + vlTOPp->cache_simX__DOT__dcache_i_m_ready = 0U; + } else { + vlTOPp->cache_simX__DOT__icache_i_m_ready = + (1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)); + vlTOPp->cache_simX__DOT__dcache_i_m_ready = + (1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)); + } + __Vdly__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state; + // ALWAYS at ../rtl/shared_memory/VX_priority_encoder_sm.v:105 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests + = ((IData)(vlTOPp->reset) ? 0U : ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__new_left_requests) + : 0U)); + // ALWAYS at ../rtl/cache/VX_d_cache.v:251 + if (vlTOPp->reset) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read = 0U; + __Vdly__cache_simX__DOT__dmem_controller__DOT__icache__DOT__state = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr = 0U; + __Vdly__cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict = 0U; + } else { + __Vdly__cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict + = (1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__update_global_way_to_evict) + ? ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict)) + : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid; + if ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found) + ? (vlTOPp->in_icache_pc_addr >> + (0x1fU & (((0U >= (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index) + >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index))) + << 5U))) : 0U); + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual; + __Vdly__cache_simX__DOT__dmem_controller__DOT__icache__DOT__state + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state; + } + // ALWAYS at ../rtl/cache/VX_cache_data.v:79 + if (vlTOPp->reset) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind = 0x20U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 1U; + } else { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = 4U; + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 + = (1U & ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 1U; + } + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 + = (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U)); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 1U; + } + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))) { + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 1U; + } + if ((1U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 + = (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U]); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 0U; + } + if ((2U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] + << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U] + >> 8U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 8U; + } + if ((4U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] + << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U] + >> 0x10U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 0x10U; + } + if ((8U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U] + >> 0x18U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 0x18U; + } + if ((0x10U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 + = (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U]); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 0x20U; + } + if ((0x20U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] + << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] + >> 8U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 0x28U; + } + if ((0x40U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] + << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] + >> 0x10U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 0x30U; + } + if ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] + >> 0x18U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 0x38U; + } + if ((0x100U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 + = (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U]); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 0x40U; + } + if ((0x200U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] + << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] + >> 8U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 0x48U; + } + if ((0x400U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] + << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] + >> 0x10U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 0x50U; + } + if ((0x800U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] + >> 0x18U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 0x58U; + } + if ((0x1000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 + = (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U]); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 0x60U; + } + if ((0x2000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] + << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] + >> 8U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 0x68U; + } + if ((0x4000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] + << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] + >> 0x10U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 0x70U; + } + if ((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] + >> 0x18U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 0x78U; + } + } + // ALWAYS at ../rtl/cache/VX_cache_data.v:79 + if (vlTOPp->reset) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind = 0x20U; + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 1U; + } else { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = 4U; + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 + = (1U & ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != (0xffffU & + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U))))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 1U; + } + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 + = (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U)); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 1U; + } + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))) { + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 1U; + } + if ((0x10000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 + = (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U]); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U; + } + if ((0x20000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] + << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] + >> 8U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 8U; + } + if ((0x40000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] + << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] + >> 0x10U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0x10U; + } + if ((0x80000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] + >> 0x18U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0x18U; + } + if ((0x100000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 + = (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U]); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0x20U; + } + if ((0x200000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] + << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] + >> 8U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0x28U; + } + if ((0x400000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] + << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] + >> 0x10U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0x30U; + } + if ((0x800000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] + >> 0x18U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0x38U; + } + if ((0x1000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 + = (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U]); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0x40U; + } + if ((0x2000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] + << 0x18U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] + >> 8U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0x48U; + } + if ((0x4000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] + << 0x10U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] + >> 0x10U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0x50U; + } + if ((0x8000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 + = (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] + >> 0x18U))); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0x58U; + } + if ((0x10000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 + = (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U]); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0x60U; + } + if ((0x20000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 + = (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] + >> 8U)); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0x68U; + } + if ((0x40000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 + = (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] + >> 0x10U)); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0x70U; + } + if ((0x80000000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)) { + __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 + = (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] + >> 0x18U)); + __Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 1U; + __Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 0x78U; + } + } + // ALWAYS at ../rtl/cache/VX_d_cache.v:251 + if (vlTOPp->reset) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[3U] = 0U; + __Vdly__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr = 0U; + __Vdly__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict = 0U; + } else { + __Vdly__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict + = (1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__update_global_way_to_evict) + ? ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict)) + : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid; + if ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found) + ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> (7U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index) + << 1U))))] : 0U); + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[0U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[1U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[2U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read[3U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[3U]; + __Vdly__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict + = __Vdly__cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state + = __Vdly__cache_simX__DOT__dmem_controller__DOT__icache__DOT__state; + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85 + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[4U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[5U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[6U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[7U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[8U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[9U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xaU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xbU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xcU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xdU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xeU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xfU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x10U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x11U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x12U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x13U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x14U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x15U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x16U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x17U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x18U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x19U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1aU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1bU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1cU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1dU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1eU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U; + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0U] + = __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82 + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][3U] = 0U; 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+ vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][1U] = 0U; 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+ vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1fU][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1fU][3U] = 0U; + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32); 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+ } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40); 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+ } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47); + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83 + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[4U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[5U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[6U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[7U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[8U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[9U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xaU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xbU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xcU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xdU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xeU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xfU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x10U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x11U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x12U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x13U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x14U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x15U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x16U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x17U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x18U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x19U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1aU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1bU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1cU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1dU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1eU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U; + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0U] + = __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:84 + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[4U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[5U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[6U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[7U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[8U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[9U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0xaU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0xbU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0xcU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0xdU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0xeU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0xfU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x10U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x11U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x12U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x13U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x14U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x15U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x16U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x17U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x18U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x19U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1aU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1bU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1cU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1dU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1eU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U; + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0U] = 1U; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85 + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[4U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[5U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[6U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[7U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[8U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[9U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xaU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xbU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xcU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xdU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xeU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xfU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x10U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x11U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x12U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x13U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x14U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x15U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x16U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x17U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x18U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x19U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1aU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1bU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1cU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1dU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1eU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U; + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0U] + = __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82 + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xaU][0U] = 0U; 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+ vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0x1fU][2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0x1fU][3U] = 0U; + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32); 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+ } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46); + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47), + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U], __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47); + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83 + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[4U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[5U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[6U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[7U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[8U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[9U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xaU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xbU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xcU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xdU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xeU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xfU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x10U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x11U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x12U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x13U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x14U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x15U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x16U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x17U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x18U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x19U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1aU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1bU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1cU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1dU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1eU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U; + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0U] + = __Vdlyvval__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:84 + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[4U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[5U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[6U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[7U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[8U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[9U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xaU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xbU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xcU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xdU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xeU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xfU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x10U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x11U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x12U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x13U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x14U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x15U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x16U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x17U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x18U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x19U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1aU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1bU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1cU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1dU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1eU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U; + } + if (__Vdlyvset__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0U] = 1U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict + = __Vdly__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state + = __Vdly__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way)) + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[0U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[1U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[2U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[3U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3fffff800000) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [0U]))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)) + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way)) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U] << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[4U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[5U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[6U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[7U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x7fffff) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [0U])) << 0x17U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [0U] << 1U)); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 1U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = 1U; + } +} + +VL_INLINE_OPT void Vcache_simX::_combo__TOP__5(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_combo__TOP__5\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + VL_SIGW(__Vtemp128,127,0,4); + VL_SIGW(__Vtemp129,127,0,4); + VL_SIGW(__Vtemp130,127,0,4); + VL_SIGW(__Vtemp131,127,0,4); + // Body + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + = vlTOPp->in_dcache_in_address[0U]; + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + = vlTOPp->in_dcache_in_address[1U]; + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + = vlTOPp->in_dcache_in_address[2U]; + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + = vlTOPp->in_dcache_in_address[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid) + : (IData)(vlTOPp->in_icache_valid_pc_addr)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid + = ((IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid) + & VL_NEGATE_I((IData)((0xffU == (0xffU & + ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U))))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid + = ((IData)(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid) + & VL_NEGATE_I((IData)((0xffU != (0xffU & + ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U))))))); + // ALWAYS at ../rtl/cache/VX_cache_bank_valid.v:24 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1 + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid)) + ? (IData)(vlTOPp->in_dcache_mem_read) : 7U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid)) + ? (IData)(vlTOPp->in_dcache_mem_write) : 7U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) + | (1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) + | (2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) + | (4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)) + | (8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write + = ((7U != (IData)(vlTOPp->in_dcache_mem_write)) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)) + ? (IData)(vlTOPp->in_dcache_mem_write) : 7U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)) + ? (IData)(vlTOPp->in_dcache_mem_read) : 7U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid + = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid)) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid) + : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid)); + // ALWAYS at ../rtl/VX_priority_encoder_w_mask.v:17 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = 0U; + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = 1U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests)) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests) + : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid)); + // ALWAYS at ../rtl/cache/VX_cache_bank_valid.v:18 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks + = (((~ ((IData)(1U) << (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U]))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) + | ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid)) + << (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U]))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks + = (((~ ((IData)(1U) << (0xfU & ((IData)(1U) + + (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U]))))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) + | ((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) + >> 1U)) << (0xfU & ((IData)(1U) + + (0xcU & + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U]))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks + = (((~ ((IData)(1U) << (0xfU & ((IData)(2U) + + (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U]))))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) + | ((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) + >> 2U)) << (0xfU & ((IData)(2U) + + (0xcU & + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U]))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks + = (((~ ((IData)(1U) << (0xfU & ((IData)(3U) + + (0xcU & vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U]))))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)) + | ((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid) + >> 3U)) << (0xfU & ((IData)(3U) + + (0xcU & + vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U]))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr + : (vlTOPp->in_icache_pc_addr >> (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index) + << 5U))))); + // ALWAYS at ../rtl/shared_memory/VX_bank_valids.v:22 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfffeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & (0U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 2U)))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfffdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffffeU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & ((0U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + >> 2U)))) + << 1U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfffbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffffcU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & ((0U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + >> 2U)))) + << 2U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfff7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffff8U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & ((0U == (3U & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + >> 2U))) + << 3U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xffefU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & (1U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 2U))))) + << 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xffdfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffffe0U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 4U) & ((1U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + >> 2U)))) + << 5U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xffbfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffffc0U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 4U) & ((1U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + >> 2U)))) + << 6U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xff7fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffff80U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 4U) & ((1U == (3U + & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + >> 2U))) + << 7U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfeffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & (2U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 2U))))) + << 8U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfdffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffe00U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 8U) & ((2U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + >> 2U)))) + << 9U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xfbffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffffc00U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 8U) & ((2U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + >> 2U)))) + << 0xaU)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xf7ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xfffff800U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 8U) & ((2U == (3U + & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + >> 2U))) + << 0xbU)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xefffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + & (3U == (3U & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 0x1eU) | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 2U))))) + << 0xcU)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xdfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffe000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 0xcU) & ((3U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + >> 2U)))) + << 0xdU)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0xbfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffffc000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 0xcU) & ((3U == (3U + & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + << 0x1eU) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[2U] + >> 2U)))) + << 0xeU)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids + = ((0x7fffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)) + | (0xffff8000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid) + << 0xcU) & ((3U == (3U + & (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[3U] + >> 2U))) + << 0xfU)))); + // ALWAYS at ../rtl/VX_priority_encoder_w_mask.v:16 + vlTOPp->__Vtableidx6 = (0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index + = vlTOPp->__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index + [vlTOPp->__Vtableidx6]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found + = vlTOPp->__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found + [vlTOPp->__Vtableidx6]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i + = vlTOPp->__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i + [vlTOPp->__Vtableidx6]; + // ALWAYS at ../rtl/VX_priority_encoder_w_mask.v:16 + vlTOPp->__Vtableidx7 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index + = vlTOPp->__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index + [vlTOPp->__Vtableidx7]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found + = vlTOPp->__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found + [vlTOPp->__Vtableidx7]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i + = vlTOPp->__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i + [vlTOPp->__Vtableidx7]; + // ALWAYS at ../rtl/VX_priority_encoder_w_mask.v:16 + vlTOPp->__Vtableidx8 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 8U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index + = vlTOPp->__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index + [vlTOPp->__Vtableidx8]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found + = vlTOPp->__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found + [vlTOPp->__Vtableidx8]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i + = vlTOPp->__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i + [vlTOPp->__Vtableidx8]; + // ALWAYS at ../rtl/VX_priority_encoder_w_mask.v:16 + vlTOPp->__Vtableidx9 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 0xcU)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index + = vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index + [vlTOPp->__Vtableidx9]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found + = vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found + [vlTOPp->__Vtableidx9]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i + = vlTOPp->__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i + [vlTOPp->__Vtableidx9]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access + = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem + = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way)) + | (1U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) + & ((0x7fffffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way)) + == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U)))) ? 1U + : 0U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way)) + | (2U & (((((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x7fffffU & (IData)( + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way + >> 0x17U))) + == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U)))) + ? 1U : 0U) << 1U))); + // ALWAYS at ../rtl/VX_countones.v:14 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids = 0U; + if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + } + if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + } + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + } + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + } + // ALWAYS at ../rtl/VX_countones.v:14 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids = 0U; + if ((0x80U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids))); + } + if ((0x40U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids))); + } + if ((0x20U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids))); + } + if ((0x10U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids))); + } + // ALWAYS at ../rtl/VX_countones.v:14 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids = 0U; + if ((0x800U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids))); + } + if ((0x400U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids))); + } + if ((0x200U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids))); + } + if ((0x100U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids))); + } + // ALWAYS at ../rtl/VX_countones.v:14 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids = 0U; + if ((0x8000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids))); + } + if ((0x4000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids))); + } + if ((0x2000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids))); + } + if ((0x1000U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids + = (7U & ((IData)(1U) + (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids))); + } + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:16 + vlTOPp->__Vtableidx1 = (0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index + = vlTOPp->__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index + [vlTOPp->__Vtableidx1]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found + = vlTOPp->__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found + [vlTOPp->__Vtableidx1]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i + = vlTOPp->__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i + [vlTOPp->__Vtableidx1]; + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:16 + vlTOPp->__Vtableidx2 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index + = vlTOPp->__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index + [vlTOPp->__Vtableidx2]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found + = vlTOPp->__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found + [vlTOPp->__Vtableidx2]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i + = vlTOPp->__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i + [vlTOPp->__Vtableidx2]; + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:16 + vlTOPp->__Vtableidx3 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 8U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index + = vlTOPp->__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index + [vlTOPp->__Vtableidx3]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found + = vlTOPp->__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found + [vlTOPp->__Vtableidx3]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i + = vlTOPp->__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i + [vlTOPp->__Vtableidx3]; + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:16 + vlTOPp->__Vtableidx4 = (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 0xcU)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index + = vlTOPp->__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index + [vlTOPp->__Vtableidx4]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found + = vlTOPp->__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found + [vlTOPp->__Vtableidx4]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i + = vlTOPp->__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i + [vlTOPp->__Vtableidx4]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank + = ((0xfff0U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) + | (0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found) + ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index)) + : 0U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank + = ((0xfcU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank + = ((0xff0fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) + | (0xf0U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found) + ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index)) + : 0U) << 4U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank + = ((0xf3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank + = ((0xf0ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) + | (0xf00U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found) + ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index)) + : 0U) << 8U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank + = ((0xcfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index) + << 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank + = ((0xfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank)) + | (0xf000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found) + ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index)) + : 0U) << 0xcU))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found) + << 3U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank + = ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index) + << 6U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[0U] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[1U] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[2U] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata[3U] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we + = ((0xfff0U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? 0xfU : 0U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we + = ((0xff0fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? 0xfU : 0U) << 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? 0xfU : 0U) << 8U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we + = ((0xfffU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + ? 0xfU : 0U) << 0xcU)); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 1U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | (1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | ((1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids)) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | ((1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids)) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | ((1U < (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids)) + << 3U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num + = ((0xfcU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid + = ((0xeU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num + = ((0xf3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid + = ((0xdU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num + = ((0xcfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index) + << 4U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid + = ((0xbU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found) + << 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num + = ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index) + << 6U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid + = ((7U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found) + << 3U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 1U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 2U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in + = (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)) + | ((~ ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__dcache_i_m_ready)))) + & ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 3U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))])); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))])); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + = ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr + : vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))])); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[0U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[1U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[2U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write[3U]; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update) + : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index)); + // ALWAYS at ../rtl/shared_memory/VX_priority_encoder_sm.v:88 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) + | ((IData)(1U) << (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) + | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 2U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) + | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 4U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced) + | ((IData)(1U) << (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 6U)))); + __Vtemp128[0U] = 0U; + __Vtemp128[1U] = 0U; + __Vtemp128[2U] = 0U; + __Vtemp128[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[0U] + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? __Vtemp128[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num))] + : 0U); + __Vtemp129[0U] = 0U; + __Vtemp129[1U] = 0U; + __Vtemp129[2U] = 0U; + __Vtemp129[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[1U] + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? __Vtemp129[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 2U))] : 0U); + __Vtemp130[0U] = 0U; + __Vtemp130[1U] = 0U; + __Vtemp130[2U] = 0U; + __Vtemp130[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[2U] + = ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? __Vtemp130[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 4U))] : 0U); + __Vtemp131[0U] = 0U; + __Vtemp131[1U] = 0U; + __Vtemp131[2U] = 0U; + __Vtemp131[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[3U] + = ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? __Vtemp131[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 6U))] : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num))] + : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 2U))] : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + = ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 4U))] : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + = ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)) + ? vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 6U))] : 0U); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write + = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write + = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid) + >> 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write + = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid) + >> 2U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write + = ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid) + >> 3U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + = ((0xffff0000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way) + | (0xffffU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + ? 0U : (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)) + << 1U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + = ((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way) + | (0xffff0000U & (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we) + : 0U) << 0x10U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual + = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read))) + ? (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + + (4U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))) + : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? ((((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U + : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) - (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))) + >> 8U) : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? ((((0U == (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U))] + >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))) + >> 0x10U) : ((((0U + == + (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U + : + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + + (4U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (4U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U))] + >> + (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))) + >> 0x18U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + = (0x7fffffU & ((0x2dU >= (0x3fU & ((IData)(0x17U) + * (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))) + ? (IData)((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way + >> (0x3fU & ((IData)(0x17U) + * (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))))) + : 0U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use + = (1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way) + >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[1U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][1U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[2U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][2U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[3U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][3U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[4U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[5U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][1U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[6U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][2U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[7U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][3U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[8U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[9U] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][1U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xaU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][2U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xbU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][3U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xcU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xdU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][1U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xeU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][2U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[0xfU] + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][3U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) + >> 1U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access) + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + == (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U)))) & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__new_left_requests + = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests)) + ? ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))) + : ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual)))); + // ALWAYS at ../rtl/shared_memory/VX_shared_memory.v:118 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[1U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[2U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[3U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[4U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[5U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[6U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[7U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[8U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[9U] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xaU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xbU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xcU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xdU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xeU] = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xfU] = 0U; + if ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfffff80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we + = ((0xfcU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) + | (3U & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 0x1cU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 4U)))); + VL_ASSIGNSEL_WIII(32,(0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + << 1U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[0U]); + } + } + } + } else { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfffff80U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2)); + VL_ASSIGNSEL_WIII(32, + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + << 5U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + (3U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[0U] + >> 4U))]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) + | ((IData)(1U) + << (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num)))); + } + } + } + } + } + } + } + if ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfffc07fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1) + << 7U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we + = ((0xf3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) + | (0xcU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 2U))))); + VL_ASSIGNSEL_WIII(32,(0x1ffU + & ((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U)))), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[1U]); + } + } + } + } else { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfffc07fU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2) + << 7U)); + VL_ASSIGNSEL_WIII(32, + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + << 2U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, + (((0U + == + (0x1fU + & ((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))))) + ? 0U + : + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + (0xfU + & (((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))) + >> 5U))] + >> + (0x1fU + & ((IData)(0x80U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[1U] + << 1U))))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) + | ((IData)(1U) + << (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 3U)))); + } + } + } + } + } + } + } + if ((4U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 8U) | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + >> 0x18U))))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfe03fffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1) + << 0xeU)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we + = ((0xcfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) + | (0x30U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U])); + VL_ASSIGNSEL_WIII(32,(0x1ffU + & ((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U)))), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[2U]); + } + } + } + } else { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 + = (0x7fU & ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 0x1aU) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + >> 6U))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0xfe03fffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2) + << 0xeU)); + VL_ASSIGNSEL_WIII(32, + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 1U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, + (((0U + == + (0x1fU + & ((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))))) + ? 0U + : + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + (0xfU + & (((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))) + >> 5U))] + >> + (0x1fU + & ((IData)(0x100U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[2U] + << 1U))))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) + | ((IData)(1U) + << (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 6U)))); + } + } + } + } + } + } + } + if ((8U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid))) { + if ((0xffU == (0xffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 0x18U)))) { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 + = (0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 6U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0x1fffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1) + << 0x15U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we + = ((0x3fU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we)) + | (0xc0U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 2U))); + VL_ASSIGNSEL_WIII(32,(0x1ffU + & ((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U)))), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata, + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data[3U]); + } + } + } + } else { + if ((7U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((1U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + if ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read))) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 + = (0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + >> 6U)); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = ((0x1fffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2) + << 0x15U)); + VL_ASSIGNSEL_WIII(32, + (0x60U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 4U)), vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data, + (((0U + == + (0x1fU + & ((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))))) + ? 0U + : + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata[ + (0xfU + & (((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))) + >> 5U))] + >> + (0x1fU + & ((IData)(0x180U) + + + (0x60U + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address[3U] + << 1U))))))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) + | ((IData)(1U) + << (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num) + >> 9U)))); + } + } + } + } + } + } + } + // ALWAYS at ../rtl/cache/VX_d_cache.v:183 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read = 0U; + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read + = (((~ ((IData)(0xffffffffU) << (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index) + << 5U)))) + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read) + | (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffffff00U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffff0000U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)))) + : 0U) << (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index) + << 5U)))); + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[0U] + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank; + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = 0U; + if (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss) { + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = 0U; + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = 1U; + } + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state + = (0xfU & (((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss)) + ? 1U : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + ? 2U : (((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (~ (IData)(vlTOPp->cache_simX__DOT__icache_i_m_ready))) + ? 2U : 0U)))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) + ? ((IData)(1U) << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index)) + : 0U) & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask + [0U]); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__update_global_way_to_evict + = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state))); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read); + vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid + = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank))); + vlTOPp->out_icache_stall = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))); +} + +void Vcache_simX::_eval(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_eval\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_combo__TOP__1(vlSymsp); + vlTOPp->__Vm_traceActivity = (2U | vlTOPp->__Vm_traceActivity); + if ((((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk))) + | ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) { + vlTOPp->_sequent__TOP__4(vlSymsp); + vlTOPp->__Vm_traceActivity = (4U | vlTOPp->__Vm_traceActivity); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__5(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__6(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__7(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure._sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__8(vlSymsp); + } + vlTOPp->_combo__TOP__5(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure._combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__9(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure._combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__10(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure._combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__11(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure._combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__12(vlSymsp); + vlTOPp->_settle__TOP__3(vlSymsp); + // Final + vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; + vlTOPp->__Vclklast__TOP__reset = vlTOPp->reset; +} + +void Vcache_simX::_eval_initial(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_eval_initial\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +} + +void Vcache_simX::final() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::final\n"); ); + // Variables + Vcache_simX__Syms* __restrict vlSymsp = this->__VlSymsp; + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +} + +void Vcache_simX::_eval_settle(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_eval_settle\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_settle__TOP__2(vlSymsp); + vlTOPp->__Vm_traceActivity = (1U | vlTOPp->__Vm_traceActivity); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure._settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__1(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure._settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__2(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure._settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__3(vlSymsp); + vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure._settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__4(vlSymsp); + vlTOPp->_settle__TOP__3(vlSymsp); +} + +VL_INLINE_OPT QData Vcache_simX::_change_request(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_change_request\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // Change detection + QData __req = false; // Logically a bool + __req |= ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr ^ vlTOPp->__Vchglast__TOP__cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)); + VL_DEBUG_IF( if(__req && ((vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr ^ vlTOPp->__Vchglast__TOP__cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr))) VL_DBG_MSGF(" CHANGE: ../rtl/shared_memory/VX_shared_memory.v:49: cache_simX.dmem_controller.shared_memory.block_addr\n"); ); + // Final + vlTOPp->__Vchglast__TOP__cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr; + return __req; +} + +#ifdef VL_DEBUG +void Vcache_simX::_eval_debug_assertions() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_eval_debug_assertions\n"); ); + // Body + if (VL_UNLIKELY((clk & 0xfeU))) { + Verilated::overWidthError("clk");} + if (VL_UNLIKELY((reset & 0xfeU))) { + Verilated::overWidthError("reset");} + if (VL_UNLIKELY((in_icache_valid_pc_addr & 0xfeU))) { + Verilated::overWidthError("in_icache_valid_pc_addr");} + if (VL_UNLIKELY((in_dcache_mem_read & 0xf8U))) { + Verilated::overWidthError("in_dcache_mem_read");} + if (VL_UNLIKELY((in_dcache_mem_write & 0xf8U))) { + Verilated::overWidthError("in_dcache_mem_write");} +} +#endif // VL_DEBUG + +void Vcache_simX::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX::_ctor_var_reset\n"); ); + // Body + clk = VL_RAND_RESET_I(1); + reset = VL_RAND_RESET_I(1); + in_icache_pc_addr = VL_RAND_RESET_I(32); + in_icache_valid_pc_addr = VL_RAND_RESET_I(1); + out_icache_stall = VL_RAND_RESET_I(1); + in_dcache_mem_read = VL_RAND_RESET_I(3); + in_dcache_mem_write = VL_RAND_RESET_I(3); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + in_dcache_in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + in_dcache_in_address[__Vi0] = VL_RAND_RESET_I(32); + }} + out_dcache_stall = VL_RAND_RESET_I(1); + cache_simX__DOT__icache_i_m_ready = VL_RAND_RESET_I(1); + cache_simX__DOT__dcache_i_m_ready = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__read_or_write = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read = VL_RAND_RESET_I(3); + cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write = VL_RAND_RESET_I(3); + cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read = VL_RAND_RESET_I(3); + cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write = VL_RAND_RESET_I(3); + cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read = VL_RAND_RESET_I(3); + VL_RAND_RESET_W(512,cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid = VL_RAND_RESET_I(4); + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr = VL_RAND_RESET_I(28); + VL_RAND_RESET_W(512,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata); + VL_RAND_RESET_W(512,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we = VL_RAND_RESET_I(8); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid = VL_RAND_RESET_I(4); + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data); + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1 = VL_RAND_RESET_I(7); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2 = VL_RAND_RESET_I(7); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids = VL_RAND_RESET_I(16); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num = VL_RAND_RESET_I(8); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__new_left_requests = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids = VL_RAND_RESET_I(3); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids = VL_RAND_RESET_I(3); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids = VL_RAND_RESET_I(3); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids = VL_RAND_RESET_I(3); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<128; ++__Vi0) { + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory[__Vi0]); + }} + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<128; ++__Vi0) { + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory[__Vi0]); + }} + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<128; ++__Vi0) { + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[__Vi0]); + }} + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<128; ++__Vi0) { + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[__Vi0]); + }} + cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read); + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read); + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank = VL_RAND_RESET_I(8); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank = VL_RAND_RESET_I(16); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb_old = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid = VL_RAND_RESET_I(4); + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks = VL_RAND_RESET_I(16); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual = VL_RAND_RESET_I(4); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[__Vi0] = VL_RAND_RESET_I(4); + }} + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__update_global_way_to_evict = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__init_b = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb_old = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__state = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state = VL_RAND_RESET_I(4); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[__Vi0] = VL_RAND_RESET_I(1); + }} + cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__update_global_way_to_evict = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__init_b = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1 = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use = VL_RAND_RESET_I(23); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way = VL_RAND_RESET_Q(46); + VL_RAND_RESET_W(256,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(256,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way = VL_RAND_RESET_I(2); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = VL_RAND_RESET_I(1); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[__Vi0] = VL_RAND_RESET_I(23); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[__Vi0] = VL_RAND_RESET_I(1); + }} + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + VL_RAND_RESET_W(128,cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[__Vi0] = VL_RAND_RESET_I(23); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[__Vi0] = VL_RAND_RESET_I(1); + }} + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = VL_RAND_RESET_I(32); + cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind = VL_RAND_RESET_I(32); + __Vtableidx1 = VL_RAND_RESET_I(4); + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[0] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[1] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[2] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[3] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[4] = 2U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[5] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[6] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[7] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[8] = 3U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[9] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[10] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[11] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[12] = 2U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[13] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[14] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[15] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[0] = 0U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[1] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[2] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[3] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[4] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[5] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[6] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[7] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[8] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[9] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[10] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[11] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[12] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[13] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[14] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[15] = 1U; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx2 = VL_RAND_RESET_I(4); + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[0] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[1] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[2] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[3] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[4] = 2U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[5] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[6] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[7] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[8] = 3U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[9] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[10] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[11] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[12] = 2U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[13] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[14] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[15] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[0] = 0U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[1] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[2] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[3] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[4] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[5] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[6] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[7] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[8] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[9] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[10] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[11] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[12] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[13] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[14] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[15] = 1U; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx3 = VL_RAND_RESET_I(4); + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[0] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[1] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[2] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[3] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[4] = 2U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[5] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[6] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[7] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[8] = 3U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[9] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[10] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[11] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[12] = 2U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[13] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[14] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[15] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[0] = 0U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[1] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[2] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[3] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[4] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[5] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[6] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[7] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[8] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[9] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[10] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[11] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[12] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[13] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[14] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[15] = 1U; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx4 = VL_RAND_RESET_I(4); + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[0] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[1] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[2] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[3] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[4] = 2U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[5] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[6] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[7] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[8] = 3U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[9] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[10] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[11] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[12] = 2U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[13] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[14] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[15] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[0] = 0U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[1] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[2] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[3] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[4] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[5] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[6] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[7] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[8] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[9] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[10] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[11] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[12] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[13] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[14] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[15] = 1U; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx5 = VL_RAND_RESET_I(4); + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[0] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[1] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[2] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[3] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[4] = 2U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[5] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[6] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[7] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[8] = 3U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[9] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[10] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[11] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[12] = 2U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[13] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[14] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[15] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[0] = 0U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[1] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[2] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[3] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[4] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[5] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[6] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[7] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[8] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[9] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[10] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[11] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[12] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[13] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[14] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[15] = 1U; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[0] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[1] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[2] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[3] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[4] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[5] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[6] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[7] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[8] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[9] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[10] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[11] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[12] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[13] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[14] = 0xffffffffU; + __Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[15] = 0xffffffffU; + __Vtableidx6 = VL_RAND_RESET_I(4); + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[0] = 0U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[1] = 0U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[2] = 1U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[3] = 1U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[4] = 2U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[5] = 2U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[6] = 2U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[7] = 2U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[8] = 3U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[9] = 3U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[10] = 3U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[11] = 3U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[12] = 3U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[13] = 3U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[14] = 3U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[15] = 3U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[0] = 0U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[1] = 1U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[2] = 1U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[3] = 1U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[4] = 1U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[5] = 1U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[6] = 1U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[7] = 1U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[8] = 1U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[9] = 1U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[10] = 1U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[11] = 1U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[12] = 1U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[13] = 1U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[14] = 1U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[15] = 1U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[0] = 4U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[1] = 4U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[2] = 4U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[3] = 4U; + __Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[4] = 4U; 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+ __Vtableidx9 = VL_RAND_RESET_I(4); + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[0] = 0U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[1] = 0U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[2] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[3] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[4] = 2U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[5] = 2U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[6] = 2U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[7] = 2U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[8] = 3U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[9] = 3U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[10] = 3U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[11] = 3U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[12] = 3U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[13] = 3U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[14] = 3U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[15] = 3U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[0] = 0U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[1] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[2] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[3] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[4] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[5] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[6] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[7] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[8] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[9] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[10] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[11] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[12] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[13] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[14] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[15] = 1U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[0] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[1] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[2] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[3] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[4] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[5] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[6] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[7] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[8] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[9] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[10] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[11] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[12] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[13] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[14] = 4U; + __Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[15] = 4U; + __Vclklast__TOP__clk = VL_RAND_RESET_I(1); + __Vclklast__TOP__reset = VL_RAND_RESET_I(1); + __Vchglast__TOP__cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr = VL_RAND_RESET_I(28); + __Vm_traceActivity = VL_RAND_RESET_I(32); +} diff --git a/simX/obj_dir/Vcache_simX.h b/simX/obj_dir/Vcache_simX.h new file mode 100644 index 00000000..ce960e15 --- /dev/null +++ b/simX/obj_dir/Vcache_simX.h @@ -0,0 +1,328 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Primary design header +// +// This header should be included by all source files instantiating the design. +// The class here is then constructed to instantiate the design. +// See the Verilator manual for examples. + +#ifndef _Vcache_simX_H_ +#define _Vcache_simX_H_ + +#include "verilated.h" + +class Vcache_simX__Syms; +class Vcache_simX_VX_dram_req_rsp_inter__N1_NB4; +class Vcache_simX_VX_dcache_request_inter; +class Vcache_simX_VX_dram_req_rsp_inter__N4_NB4; +class Vcache_simX_VX_Cache_Bank__pi8; +class VerilatedVcd; + +//---------- + +VL_MODULE(Vcache_simX) { + public: + // CELLS + // Public to allow access to /*verilator_public*/ items; + // otherwise the application code can consider these internals. + Vcache_simX_VX_dram_req_rsp_inter__N1_NB4* __PVT__cache_simX__DOT__VX_dram_req_rsp_icache; + Vcache_simX_VX_dcache_request_inter* __PVT__cache_simX__DOT__VX_dcache_req; + Vcache_simX_VX_dram_req_rsp_inter__N4_NB4* __PVT__cache_simX__DOT__VX_dram_req_rsp; + Vcache_simX_VX_Cache_Bank__pi8* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure; + Vcache_simX_VX_Cache_Bank__pi8* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure; + Vcache_simX_VX_Cache_Bank__pi8* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure; + Vcache_simX_VX_Cache_Bank__pi8* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure; + + // PORTS + // The application code writes and reads these signals to + // propagate new values into/out from the Verilated model. + VL_IN8(clk,0,0); + VL_IN8(reset,0,0); + VL_IN8(in_icache_valid_pc_addr,0,0); + VL_OUT8(out_icache_stall,0,0); + VL_IN8(in_dcache_mem_read,2,0); + VL_IN8(in_dcache_mem_write,2,0); + VL_OUT8(out_dcache_stall,0,0); + VL_IN(in_icache_pc_addr,31,0); + VL_IN8(in_dcache_in_valid[4],0,0); + VL_IN(in_dcache_in_address[4],31,0); + + // LOCAL SIGNALS + // Internals; generally not touched by application code + VL_SIG8(cache_simX__DOT__icache_i_m_ready,0,0); + VL_SIG8(cache_simX__DOT__dcache_i_m_ready,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__read_or_write,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read,2,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write,2,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read,2,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write,2,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read,2,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid,3,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr,27,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we,7,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num,7,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__new_left_requests,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids,2,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids,2,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids,2,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids,2,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank,7,0); + VL_SIG16(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank,15,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank,3,0); + VL_SIG16(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank,15,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb_old,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index,1,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__update_global_way_to_evict,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb_old,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__state,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state,3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__update_global_way_to_evict,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update,0,0); + VL_SIG16(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we,15,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way,1,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way,1,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way,1,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way,31,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way,1,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty,0,0); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data,127,0,4); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata,511,0,16); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata,511,0,16); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind,31,0); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read,127,0,4); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read,127,0,4); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual,127,0,4); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank,127,0,4); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank,127,0,4); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__init_b,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__init_b,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use,22,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual,31,0); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write,127,0,4); + VL_SIG64(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way,45,0); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way,255,0,8); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way,255,0,8); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f,31,0); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind,31,0); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[4],3,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[1],0,0); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[32],127,0,4); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[32],22,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[32],0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[32],0,0); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[32],127,0,4); + VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[32],22,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[32],0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[32],0,0); + + // LOCAL VARIABLES + // Internals; generally not touched by application code + static VL_ST_SIG8(__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[16],1,0); + static VL_ST_SIG8(__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[16],0,0); + static VL_ST_SIG(__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[16],31,0); + static VL_ST_SIG8(__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[16],1,0); + static VL_ST_SIG8(__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[16],0,0); + static VL_ST_SIG(__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[16],31,0); + static VL_ST_SIG8(__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[16],1,0); + static VL_ST_SIG8(__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[16],0,0); + static VL_ST_SIG(__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[16],31,0); + static VL_ST_SIG8(__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[16],1,0); + static VL_ST_SIG8(__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[16],0,0); + static VL_ST_SIG(__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[16],31,0); + static VL_ST_SIG8(__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[16],1,0); + static VL_ST_SIG8(__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[16],0,0); + static VL_ST_SIG(__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[16],31,0); + static VL_ST_SIG8(__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[16],1,0); + static VL_ST_SIG8(__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[16],0,0); + static VL_ST_SIG(__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[16],31,0); + static VL_ST_SIG8(__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index[16],1,0); + static VL_ST_SIG8(__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found[16],0,0); + static VL_ST_SIG(__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i[16],31,0); + static VL_ST_SIG8(__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index[16],1,0); + static VL_ST_SIG8(__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found[16],0,0); + static VL_ST_SIG(__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[16],31,0); + static VL_ST_SIG8(__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[16],1,0); + static VL_ST_SIG8(__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[16],0,0); + static VL_ST_SIG(__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[16],31,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1,6,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2,6,0); + VL_SIG16(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids,15,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index,1,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index,1,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index,1,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index,1,0); + VL_SIG16(cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks,15,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index,1,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index,1,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index,1,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index,1,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index,0,0); + VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1,0,0); + VL_SIG8(__Vtableidx1,3,0); + VL_SIG8(__Vtableidx2,3,0); + VL_SIG8(__Vtableidx3,3,0); + VL_SIG8(__Vtableidx4,3,0); + VL_SIG8(__Vtableidx5,3,0); + VL_SIG8(__Vtableidx6,3,0); + VL_SIG8(__Vtableidx7,3,0); + VL_SIG8(__Vtableidx8,3,0); + VL_SIG8(__Vtableidx9,3,0); + VL_SIG8(__Vclklast__TOP__clk,0,0); + VL_SIG8(__Vclklast__TOP__reset,0,0); + VL_SIG(__Vchglast__TOP__cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr,27,0); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata,511,0,16); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data,127,0,4); + VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address,127,0,4); + VL_SIG(__Vm_traceActivity,31,0); + + // INTERNAL VARIABLES + // Internals; generally not touched by application code + Vcache_simX__Syms* __VlSymsp; // Symbol table + + // PARAMETERS + // Parameters marked /*verilator public*/ for use by application code + + // CONSTRUCTORS + private: + Vcache_simX& operator= (const Vcache_simX&); ///< Copying not allowed + Vcache_simX(const Vcache_simX&); ///< Copying not allowed + public: + /// Construct the model; called by application code + /// The special name may be used to make a wrapper with a + /// single model invisible WRT DPI scope names. + Vcache_simX(const char* name="TOP"); + /// Destroy the model; called (often implicitly) by application code + ~Vcache_simX(); + /// Trace signals in the model; called by application code + void trace (VerilatedVcdC* tfp, int levels, int options=0); + + // API METHODS + /// Evaluate the model. Application must call when inputs change. + void eval(); + /// Simulation complete, run final blocks. Application must call on completion. + void final(); + + // INTERNAL METHODS + private: + static void _eval_initial_loop(Vcache_simX__Syms* __restrict vlSymsp); + public: + void __Vconfigure(Vcache_simX__Syms* symsp, bool first); + private: + static QData _change_request(Vcache_simX__Syms* __restrict vlSymsp); + public: + static void _combo__TOP__1(Vcache_simX__Syms* __restrict vlSymsp); + static void _combo__TOP__5(Vcache_simX__Syms* __restrict vlSymsp); + private: + void _ctor_var_reset(); + public: + static void _eval(Vcache_simX__Syms* __restrict vlSymsp); + private: +#ifdef VL_DEBUG + void _eval_debug_assertions(); +#endif // VL_DEBUG + public: + static void _eval_initial(Vcache_simX__Syms* __restrict vlSymsp); + static void _eval_settle(Vcache_simX__Syms* __restrict vlSymsp); + static void _sequent__TOP__4(Vcache_simX__Syms* __restrict vlSymsp); + static void _settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp); + static void _settle__TOP__3(Vcache_simX__Syms* __restrict vlSymsp); + static void traceChgThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__3(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__4(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__5(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__6(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceFullThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceInitThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceInitThis__1(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code); +} VL_ATTR_ALIGNED(128); + +#endif // guard diff --git a/simX/obj_dir/Vcache_simX.mk b/simX/obj_dir/Vcache_simX.mk new file mode 100644 index 00000000..7a99697e --- /dev/null +++ b/simX/obj_dir/Vcache_simX.mk @@ -0,0 +1,85 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable +# +# Execute this makefile from the object directory: +# make -f Vcache_simX.mk + +default: Vcache_simX + +### Constants... +# Perl executable (from $PERL) +PERL = perl +# Path to Verilator kit (from $VERILATOR_ROOT) +VERILATOR_ROOT = /usr/share/verilator +# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) +SYSTEMC_INCLUDE ?= +# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) +SYSTEMC_LIBDIR ?= + +### Switches... +# SystemC output mode? 0/1 (from --sc) +VM_SC = 0 +# Legacy or SystemC output mode? 0/1 (from --sc) +VM_SP_OR_SC = $(VM_SC) +# Deprecated +VM_PCLI = 1 +# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH) +VM_SC_TARGET_ARCH = linux + +### Vars... +# Design prefix (from --prefix) +VM_PREFIX = Vcache_simX +# Module prefix (from --prefix) +VM_MODPREFIX = Vcache_simX +# User CFLAGS (from -CFLAGS on Verilator command line) +VM_USER_CFLAGS = \ + -std=c++11 -fPIC -O3 \ + +# User LDLIBS (from -LDFLAGS on Verilator command line) +VM_USER_LDLIBS = \ + +# User .cpp files (from .cpp's on Verilator command line) +VM_USER_CLASSES = \ + args \ + core \ + enc \ + instruction \ + mem \ + simX \ + util \ + +# User .cpp directories (from .cpp's on Verilator command line) +VM_USER_DIR = \ + . \ + + +### Default rules... +# Include list of all generated classes +include Vcache_simX_classes.mk +# Include global rules +include $(VERILATOR_ROOT)/include/verilated.mk + +### Executable rules... (from --exe) +VPATH += $(VM_USER_DIR) + +args.o: args.cpp + $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< +core.o: core.cpp + $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< +enc.o: enc.cpp + $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< +instruction.o: instruction.cpp + $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< +mem.o: mem.cpp + $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< +simX.o: simX.cpp + $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< +util.o: util.cpp + $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< + +### Link rules... (from --exe) +Vcache_simX: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a + $(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS) 2>&1 | c++filt + + +# Verilated -*- Makefile -*- diff --git a/simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp b/simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp new file mode 100644 index 00000000..e8076781 --- /dev/null +++ b/simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp @@ -0,0 +1,7165 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Vcache_simX.h for the primary calling header + +#include "Vcache_simX_VX_Cache_Bank__pi8.h" // For This +#include "Vcache_simX__Syms.h" + + +//-------------------- +// STATIC VARIABLES + + +//-------------------- + +VL_CTOR_IMP(Vcache_simX_VX_Cache_Bank__pi8) { + // Reset internal values + // Reset structure values + _ctor_var_reset(); +} + +void Vcache_simX_VX_Cache_Bank__pi8::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +Vcache_simX_VX_Cache_Bank__pi8::~Vcache_simX_VX_Cache_Bank__pi8() { +} + +//-------------------- +// Internal Methods + +void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__1(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__1\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + VL_SIGW(__Vtemp3,127,0,4); + VL_SIGW(__Vtemp4,127,0,4); + VL_SIGW(__Vtemp5,127,0,4); + VL_SIGW(__Vtemp6,127,0,4); + VL_SIGW(__Vtemp7,127,0,4); + VL_SIGW(__Vtemp8,127,0,4); + VL_SIGW(__Vtemp9,127,0,4); + // Body + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U] << 1U)); + this->__PVT__data_structures__DOT__data_use_per_way[0U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[1U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[2U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[3U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][3U]; + this->__PVT__data_structures__DOT__data_use_per_way[4U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[5U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[6U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[7U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][3U]; + this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [0U]); + this->__PVT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [0U] << 1U)); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [0U]))); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [0U])) << 0x15U)); + this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 2U : ((2U == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 4U + : 8U))); + __Vtemp3[0U] = 0U; + __Vtemp3[1U] = 0U; + __Vtemp3[2U] = 0U; + __Vtemp3[3U] = 0U; + __Vtemp4[0U] = 0U; + __Vtemp4[1U] = 0U; + __Vtemp4[2U] = 0U; + __Vtemp4[3U] = 0U; + __Vtemp5[0U] = 0U; + __Vtemp5[1U] = 0U; + __Vtemp5[2U] = 0U; + __Vtemp5[3U] = 0U; + __Vtemp6[0U] = 0U; + __Vtemp6[1U] = 0U; + __Vtemp6[2U] = 0U; + __Vtemp6[3U] = 0U; + __Vtemp7[0U] = 0U; + __Vtemp7[1U] = 0U; + __Vtemp7[2U] = 0U; + __Vtemp7[3U] = 0U; + __Vtemp8[0U] = 0U; + __Vtemp8[1U] = 0U; + __Vtemp8[2U] = 0U; + __Vtemp8[3U] = 0U; + __Vtemp9[0U] = 0U; + __Vtemp9[1U] = 0U; + __Vtemp9[2U] = 0U; + __Vtemp9[3U] = 0U; + this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff00U + & (__Vtemp3[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 8U)) + : ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff0000U + & (__Vtemp4[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x10U)) + : ((3U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp5[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x18U)) + : __Vtemp6[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]))) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xffff0000U + & (__Vtemp7[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x10U)) + : __Vtemp8[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]) + : __Vtemp9[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + this->__PVT__data_structures__DOT__invalid_index = 0U; + this->__PVT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_index = 1U; + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_index = 0U; + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + this->__PVT__data_structures__DOT__hit_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (1U & (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + & ((0x1fffffU & (IData)(this->__PVT__data_structures__DOT__tag_use_per_way)) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U))); + this->__PVT__data_structures__DOT__hit_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (2U & (((((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x1fffffU & (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> 0x15U))) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U) << 1U))); + this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 4U)); + this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 8U)); + this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 0xcU)); + this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0U] + : this->__PVT__use_write_data); + this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[1U] + : this->__PVT__use_write_data); + this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[2U] + : this->__PVT__use_write_data); + this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[3U] + : this->__PVT__use_write_data); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + this->__PVT__data_structures__DOT__way_index = 0U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 1U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 0U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + this->__PVT__data_structures__DOT__data_write_per_way[0U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[1U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[2U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[3U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__data_write_per_way[4U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[5U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[6U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[7U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index)); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(this->__PVT__write_from_mem) + & (~ (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(this->__PVT__write_from_mem) + & (IData)(this->__PVT__data_structures__DOT__way_use_Qual)) + << 1U)); + this->__Vcellout__data_structures__data_use[0U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[1U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[2U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[3U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__PVT__valid_use = (1U & ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> (IData)(this->__PVT__data_structures__DOT__way_use_Qual))); + this->__PVT__tag_use = (0x1fffffU & ((0x29U >= + (0x3fU & + ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))) + ? (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> + (0x3fU + & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual))))) + : 0U)); + this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))) + ? this->__Vcellout__data_structures__data_use[0U] + : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (this->__Vcellout__data_structures__data_use[0U] + >> 8U) : ((2U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[0U] + >> 0x10U) + : + (this->__Vcellout__data_structures__data_use[0U] + >> 0x18U)))); + this->__PVT__genblk1__BRA__0__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & (IData)(this->__PVT__access)) & (~ (( + (this->__PVT__tag_use + != + (0x1fffffU + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(this->__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)))); + this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) + | ((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U))))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) + | (0xffffU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? 0U : (IData)(this->__PVT__we)))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffffU & this->__PVT__data_structures__DOT__we_per_way) + | (0xffff0000U & (((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? (IData)(this->__PVT__we) + : 0U) << 0x10U))); + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) + | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))); + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))); +} + +VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__5(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__5\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 0U; + // ALWAYS at ../rtl/cache/VX_cache_data.v:79 + if (vlTOPp->reset) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind = 0x20U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 1U; + } else { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = 4U; + if (this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 + = (1U & ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way)))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 + = (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 1U; + } + if ((1U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[0U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 0U; + } + if ((2U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[1U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[0U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 8U; + } + if ((4U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[1U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[0U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 0x10U; + } + if ((8U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[1U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[0U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 0x18U; + } + if ((0x10U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[1U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 0x20U; + } + if ((0x20U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[2U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[1U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 0x28U; + } + if ((0x40U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[2U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[1U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 0x30U; + } + if ((0x80U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[2U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[1U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 0x38U; + } + if ((0x100U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[2U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 0x40U; + } + if ((0x200U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[3U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[2U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 0x48U; + } + if ((0x400U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[3U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[2U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 0x50U; + } + if ((0x800U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[3U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[2U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 0x58U; + } + if ((0x1000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[3U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 0x60U; + } + if ((0x2000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[4U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[3U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 0x68U; + } + if ((0x4000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[4U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[3U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 0x70U; + } + if ((0x8000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[4U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[3U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 0x78U; + } + } + // ALWAYS at ../rtl/cache/VX_cache_data.v:79 + if (vlTOPp->reset) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind = 0x20U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 1U; + } else { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = 4U; + if (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 + = (1U & ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != (0xffffU & + (this->__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 1U; + } + if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 + = (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 1U; + } + if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 1U; + } + if ((0x10000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[4U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U; + } + if ((0x20000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[5U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[4U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 8U; + } + if ((0x40000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[5U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[4U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0x10U; + } + if ((0x80000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[5U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[4U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0x18U; + } + if ((0x100000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[5U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0x20U; + } + if ((0x200000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[6U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[5U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0x28U; + } + if ((0x400000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[6U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[5U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0x30U; + } + if ((0x800000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[6U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[5U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0x38U; + } + if ((0x1000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[6U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0x40U; + } + if ((0x2000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[7U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[6U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0x48U; + } + if ((0x4000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[7U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[6U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0x50U; + } + if ((0x8000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[7U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[6U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0x58U; + } + if ((0x10000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[7U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0x60U; + } + if ((0x20000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 + = (0xffU & (this->__PVT__data_structures__DOT__data_write_per_way[7U] + >> 8U)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0x68U; + } + if ((0x40000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 + = (0xffU & (this->__PVT__data_structures__DOT__data_write_per_way[7U] + >> 0x10U)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0x70U; + } + if ((0x80000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 + = (0xffU & (this->__PVT__data_structures__DOT__data_write_per_way[7U] + >> 0x18U)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 0x78U; + } + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0U] + = this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xfU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xfU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xfU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xfU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x10U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x10U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x10U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x10U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x11U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x11U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x11U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x11U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x12U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x12U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x12U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x12U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x13U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x13U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x13U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x13U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x14U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x14U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x14U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x14U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x15U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x15U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x15U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x15U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x16U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x16U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x16U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x16U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x17U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x17U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x17U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x17U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x18U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x18U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x18U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x18U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x19U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x19U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x19U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x19U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1aU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1aU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1aU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1aU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1bU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1bU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1bU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1bU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1cU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1cU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1cU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1cU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1dU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1dU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1dU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1dU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1eU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1eU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1eU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1eU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1fU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1fU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1fU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0x1fU][3U] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46); + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47), + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47); + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:84 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0U] = 1U; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0U] + = this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0U] + = this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xaU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xaU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xaU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xaU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xbU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xbU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xbU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xbU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xcU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xcU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xcU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xcU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xdU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xdU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xdU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xdU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xeU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xeU][1U] = 0U; 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+ this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0U] = 1U; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0U] + = this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32; + } + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]); + this->__PVT__data_structures__DOT__data_use_per_way[0U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[1U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[2U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[3U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][3U]; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [0U]); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [0U]))); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U] << 1U)); + this->__PVT__data_structures__DOT__data_use_per_way[4U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[5U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[6U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[7U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][3U]; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [0U] << 1U)); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [0U])) << 0x15U)); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + this->__PVT__data_structures__DOT__invalid_index = 0U; + this->__PVT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_index = 1U; + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_index = 0U; + this->__PVT__data_structures__DOT__invalid_found = 1U; + } +} + +VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__9(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__9\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + VL_SIGW(__Vtemp77,127,0,4); + VL_SIGW(__Vtemp78,127,0,4); + VL_SIGW(__Vtemp79,127,0,4); + VL_SIGW(__Vtemp80,127,0,4); + VL_SIGW(__Vtemp81,127,0,4); + VL_SIGW(__Vtemp82,127,0,4); + VL_SIGW(__Vtemp83,127,0,4); + // Body + this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 2U : ((2U == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 4U + : 8U))); + __Vtemp77[0U] = 0U; + __Vtemp77[1U] = 0U; + __Vtemp77[2U] = 0U; + __Vtemp77[3U] = 0U; + __Vtemp78[0U] = 0U; + __Vtemp78[1U] = 0U; + __Vtemp78[2U] = 0U; + __Vtemp78[3U] = 0U; + __Vtemp79[0U] = 0U; + __Vtemp79[1U] = 0U; + __Vtemp79[2U] = 0U; + __Vtemp79[3U] = 0U; + __Vtemp80[0U] = 0U; + __Vtemp80[1U] = 0U; + __Vtemp80[2U] = 0U; + __Vtemp80[3U] = 0U; + __Vtemp81[0U] = 0U; + __Vtemp81[1U] = 0U; + __Vtemp81[2U] = 0U; + __Vtemp81[3U] = 0U; + __Vtemp82[0U] = 0U; + __Vtemp82[1U] = 0U; + __Vtemp82[2U] = 0U; + __Vtemp82[3U] = 0U; + __Vtemp83[0U] = 0U; + __Vtemp83[1U] = 0U; + __Vtemp83[2U] = 0U; + __Vtemp83[3U] = 0U; + this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff00U + & (__Vtemp77[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 8U)) + : ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff0000U + & (__Vtemp78[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x10U)) + : ((3U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp79[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x18U)) + : __Vtemp80[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]))) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xffff0000U + & (__Vtemp81[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x10U)) + : __Vtemp82[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]) + : __Vtemp83[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])); + this->__PVT__data_structures__DOT__hit_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (1U & (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + & ((0x1fffffU & (IData)(this->__PVT__data_structures__DOT__tag_use_per_way)) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U))); + this->__PVT__data_structures__DOT__hit_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (2U & (((((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x1fffffU & (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> 0x15U))) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U) << 1U))); + this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 4U)); + this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 8U)); + this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 0xcU)); + this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0U] + : this->__PVT__use_write_data); + this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[1U] + : this->__PVT__use_write_data); + this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[2U] + : this->__PVT__use_write_data); + this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[3U] + : this->__PVT__use_write_data); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + this->__PVT__data_structures__DOT__way_index = 0U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 1U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 0U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + this->__PVT__data_structures__DOT__data_write_per_way[0U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[1U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[2U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[3U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__data_write_per_way[4U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[5U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[6U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[7U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index)); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(this->__PVT__write_from_mem) + & (~ (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(this->__PVT__write_from_mem) + & (IData)(this->__PVT__data_structures__DOT__way_use_Qual)) + << 1U)); + this->__Vcellout__data_structures__data_use[0U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[1U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[2U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[3U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__PVT__valid_use = (1U & ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> (IData)(this->__PVT__data_structures__DOT__way_use_Qual))); + this->__PVT__tag_use = (0x1fffffU & ((0x29U >= + (0x3fU & + ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))) + ? (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> + (0x3fU + & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual))))) + : 0U)); + this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))) + ? this->__Vcellout__data_structures__data_use[0U] + : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (this->__Vcellout__data_structures__data_use[0U] + >> 8U) : ((2U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[0U] + >> 0x10U) + : + (this->__Vcellout__data_structures__data_use[0U] + >> 0x18U)))); + this->__PVT__genblk1__BRA__0__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & (IData)(this->__PVT__access)) & (~ (( + (this->__PVT__tag_use + != + (0x1fffffU + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(this->__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)))); + this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) + | ((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U))))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) + | (0xffffU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? 0U : (IData)(this->__PVT__we)))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffffU & this->__PVT__data_structures__DOT__we_per_way) + | (0xffff0000U & (((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? (IData)(this->__PVT__we) + : 0U) << 0x10U))); + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) + | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))); + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))); +} + +void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__2(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__2\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + VL_SIGW(__Vtemp87,127,0,4); + VL_SIGW(__Vtemp88,127,0,4); + VL_SIGW(__Vtemp89,127,0,4); + VL_SIGW(__Vtemp90,127,0,4); + VL_SIGW(__Vtemp91,127,0,4); + VL_SIGW(__Vtemp92,127,0,4); + VL_SIGW(__Vtemp93,127,0,4); + // Body + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U] << 1U)); + this->__PVT__data_structures__DOT__data_use_per_way[0U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[1U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[2U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[3U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][3U]; + this->__PVT__data_structures__DOT__data_use_per_way[4U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[5U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[6U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[7U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][3U]; + this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [0U]); + this->__PVT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [0U] << 1U)); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [0U]))); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [0U])) << 0x15U)); + this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in)); + this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in)); + this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 2U : ((2U == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 4U + : 8U))); + __Vtemp87[0U] = 0U; + __Vtemp87[1U] = 0U; + __Vtemp87[2U] = 0U; + __Vtemp87[3U] = 0U; + __Vtemp88[0U] = 0U; + __Vtemp88[1U] = 0U; + __Vtemp88[2U] = 0U; + __Vtemp88[3U] = 0U; + __Vtemp89[0U] = 0U; + __Vtemp89[1U] = 0U; + __Vtemp89[2U] = 0U; + __Vtemp89[3U] = 0U; + __Vtemp90[0U] = 0U; + __Vtemp90[1U] = 0U; + __Vtemp90[2U] = 0U; + __Vtemp90[3U] = 0U; + __Vtemp91[0U] = 0U; + __Vtemp91[1U] = 0U; + __Vtemp91[2U] = 0U; + __Vtemp91[3U] = 0U; + __Vtemp92[0U] = 0U; + __Vtemp92[1U] = 0U; + __Vtemp92[2U] = 0U; + __Vtemp92[3U] = 0U; + __Vtemp93[0U] = 0U; + __Vtemp93[1U] = 0U; + __Vtemp93[2U] = 0U; + __Vtemp93[3U] = 0U; + this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff00U + & (__Vtemp87[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 8U)) + : ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff0000U + & (__Vtemp88[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x10U)) + : ((3U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp89[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x18U)) + : __Vtemp90[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))]))) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xffff0000U + & (__Vtemp91[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x10U)) + : __Vtemp92[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))]) + : __Vtemp93[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))])); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + this->__PVT__data_structures__DOT__invalid_index = 0U; + this->__PVT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_index = 1U; + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_index = 0U; + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + this->__PVT__data_structures__DOT__hit_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (1U & (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + & ((0x1fffffU & (IData)(this->__PVT__data_structures__DOT__tag_use_per_way)) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U))); + this->__PVT__data_structures__DOT__hit_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (2U & (((((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x1fffffU & (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> 0x15U))) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U) << 1U))); + this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 4U)); + this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 8U)); + this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 0xcU)); + this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[4U] + : this->__PVT__use_write_data); + this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[5U] + : this->__PVT__use_write_data); + this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[6U] + : this->__PVT__use_write_data); + this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[7U] + : this->__PVT__use_write_data); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + this->__PVT__data_structures__DOT__way_index = 0U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 1U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 0U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + this->__PVT__data_structures__DOT__data_write_per_way[0U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[1U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[2U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[3U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__data_write_per_way[4U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[5U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[6U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[7U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index)); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(this->__PVT__write_from_mem) + & (~ (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(this->__PVT__write_from_mem) + & (IData)(this->__PVT__data_structures__DOT__way_use_Qual)) + << 1U)); + this->__Vcellout__data_structures__data_use[0U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[1U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[2U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[3U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__PVT__valid_use = (1U & ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> (IData)(this->__PVT__data_structures__DOT__way_use_Qual))); + this->__PVT__tag_use = (0x1fffffU & ((0x29U >= + (0x3fU & + ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))) + ? (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> + (0x3fU + & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual))))) + : 0U)); + this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))) + ? this->__Vcellout__data_structures__data_use[0U] + : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (this->__Vcellout__data_structures__data_use[0U] + >> 8U) : ((2U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[0U] + >> 0x10U) + : + (this->__Vcellout__data_structures__data_use[0U] + >> 0x18U)))); + this->__PVT__genblk1__BRA__0__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & (IData)(this->__PVT__access)) & (~ (( + (this->__PVT__tag_use + != + (0x1fffffU + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(this->__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in)))); + this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) + | ((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U))))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) + | (0xffffU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? 0U : (IData)(this->__PVT__we)))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffffU & this->__PVT__data_structures__DOT__we_per_way) + | (0xffff0000U & (((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? (IData)(this->__PVT__we) + : 0U) << 0x10U))); + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) + | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))); + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))); +} + +VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__6(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__6\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 0U; + // ALWAYS at ../rtl/cache/VX_cache_data.v:79 + if (vlTOPp->reset) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind = 0x20U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 1U; + } else { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = 4U; + if (this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 + = (1U & ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way)))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 + = (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 1U; + } + if ((1U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[0U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 0U; + } + if ((2U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[1U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[0U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 8U; + } + if ((4U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[1U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[0U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 0x10U; + } + if ((8U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[1U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[0U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 0x18U; + } + if ((0x10U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[1U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 0x20U; + } + if ((0x20U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[2U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[1U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 0x28U; + } + if ((0x40U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[2U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[1U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 0x30U; + } + if ((0x80U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[2U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[1U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 0x38U; + } + if ((0x100U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[2U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 0x40U; + } + if ((0x200U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[3U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[2U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 0x48U; + } + if ((0x400U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[3U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[2U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 0x50U; + } + if ((0x800U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[3U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[2U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 0x58U; + } + if ((0x1000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[3U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 0x60U; + } + if ((0x2000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[4U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[3U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 0x68U; + } + if ((0x4000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[4U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[3U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 0x70U; + } + if ((0x8000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[4U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[3U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 0x78U; + } + } + // ALWAYS at ../rtl/cache/VX_cache_data.v:79 + if (vlTOPp->reset) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind = 0x20U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 1U; + } else { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = 4U; + if (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 + = (1U & ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != (0xffffU & + (this->__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 1U; + } + if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 + = (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 1U; + } + if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 1U; + } + if ((0x10000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[4U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U; + } + if ((0x20000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[5U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[4U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 8U; + } + if ((0x40000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[5U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[4U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0x10U; + } + if ((0x80000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[5U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[4U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0x18U; + } + if ((0x100000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[5U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0x20U; + } + if ((0x200000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[6U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[5U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0x28U; + } + if ((0x400000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[6U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[5U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0x30U; + } + if ((0x800000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[6U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[5U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0x38U; + } + if ((0x1000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[6U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0x40U; + } + if ((0x2000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[7U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[6U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0x48U; + } + if ((0x4000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[7U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[6U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0x50U; + } + if ((0x8000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[7U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[6U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0x58U; + } + if ((0x10000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[7U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0x60U; + } + if ((0x20000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 + = (0xffU & (this->__PVT__data_structures__DOT__data_write_per_way[7U] + >> 8U)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0x68U; + } + if ((0x40000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 + = (0xffU & (this->__PVT__data_structures__DOT__data_write_per_way[7U] + >> 0x10U)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0x70U; + } + if ((0x80000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 + = (0xffU & (this->__PVT__data_structures__DOT__data_write_per_way[7U] + >> 0x18U)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 0x78U; + } + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0U] + = this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xfU][0U] = 0U; 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+ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0U] = 1U; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0U] + = this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0U] + = this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xaU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xaU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xaU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xaU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xbU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xbU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xbU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xbU][3U] = 0U; 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+ } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47), + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47); + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:84 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0U] = 1U; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0U] + = this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32; + } + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]); + this->__PVT__data_structures__DOT__data_use_per_way[0U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[1U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[2U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[3U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][3U]; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [0U]); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [0U]))); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U] << 1U)); + this->__PVT__data_structures__DOT__data_use_per_way[4U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[5U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[6U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[7U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][3U]; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [0U] << 1U)); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [0U])) << 0x15U)); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + this->__PVT__data_structures__DOT__invalid_index = 0U; + this->__PVT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_index = 1U; + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_index = 0U; + this->__PVT__data_structures__DOT__invalid_found = 1U; + } +} + +VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__10(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__10\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + VL_SIGW(__Vtemp161,127,0,4); + VL_SIGW(__Vtemp162,127,0,4); + VL_SIGW(__Vtemp163,127,0,4); + VL_SIGW(__Vtemp164,127,0,4); + VL_SIGW(__Vtemp165,127,0,4); + VL_SIGW(__Vtemp166,127,0,4); + VL_SIGW(__Vtemp167,127,0,4); + // Body + this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in)); + this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in)); + this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 2U : ((2U == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 4U + : 8U))); + __Vtemp161[0U] = 0U; + __Vtemp161[1U] = 0U; + __Vtemp161[2U] = 0U; + __Vtemp161[3U] = 0U; + __Vtemp162[0U] = 0U; + __Vtemp162[1U] = 0U; + __Vtemp162[2U] = 0U; + __Vtemp162[3U] = 0U; + __Vtemp163[0U] = 0U; + __Vtemp163[1U] = 0U; + __Vtemp163[2U] = 0U; + __Vtemp163[3U] = 0U; + __Vtemp164[0U] = 0U; + __Vtemp164[1U] = 0U; + __Vtemp164[2U] = 0U; + __Vtemp164[3U] = 0U; + __Vtemp165[0U] = 0U; + __Vtemp165[1U] = 0U; + __Vtemp165[2U] = 0U; + __Vtemp165[3U] = 0U; + __Vtemp166[0U] = 0U; + __Vtemp166[1U] = 0U; + __Vtemp166[2U] = 0U; + __Vtemp166[3U] = 0U; + __Vtemp167[0U] = 0U; + __Vtemp167[1U] = 0U; + __Vtemp167[2U] = 0U; + __Vtemp167[3U] = 0U; + this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff00U + & (__Vtemp161[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 8U)) + : ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff0000U + & (__Vtemp162[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x10U)) + : ((3U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp163[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x18U)) + : __Vtemp164[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))]))) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xffff0000U + & (__Vtemp165[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x10U)) + : __Vtemp166[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))]) + : __Vtemp167[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))])); + this->__PVT__data_structures__DOT__hit_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (1U & (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + & ((0x1fffffU & (IData)(this->__PVT__data_structures__DOT__tag_use_per_way)) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U))); + this->__PVT__data_structures__DOT__hit_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (2U & (((((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x1fffffU & (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> 0x15U))) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U) << 1U))); + this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 4U)); + this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 8U)); + this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 0xcU)); + this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[4U] + : this->__PVT__use_write_data); + this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[5U] + : this->__PVT__use_write_data); + this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[6U] + : this->__PVT__use_write_data); + this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[7U] + : this->__PVT__use_write_data); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + this->__PVT__data_structures__DOT__way_index = 0U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 1U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 0U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + this->__PVT__data_structures__DOT__data_write_per_way[0U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[1U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[2U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[3U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__data_write_per_way[4U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[5U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[6U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[7U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index)); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(this->__PVT__write_from_mem) + & (~ (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(this->__PVT__write_from_mem) + & (IData)(this->__PVT__data_structures__DOT__way_use_Qual)) + << 1U)); + this->__Vcellout__data_structures__data_use[0U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[1U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[2U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[3U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__PVT__valid_use = (1U & ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> (IData)(this->__PVT__data_structures__DOT__way_use_Qual))); + this->__PVT__tag_use = (0x1fffffU & ((0x29U >= + (0x3fU & + ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))) + ? (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> + (0x3fU + & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual))))) + : 0U)); + this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))) + ? this->__Vcellout__data_structures__data_use[0U] + : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (this->__Vcellout__data_structures__data_use[0U] + >> 8U) : ((2U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[0U] + >> 0x10U) + : + (this->__Vcellout__data_structures__data_use[0U] + >> 0x18U)))); + this->__PVT__genblk1__BRA__0__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & (IData)(this->__PVT__access)) & (~ (( + (this->__PVT__tag_use + != + (0x1fffffU + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(this->__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in)))); + this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) + | ((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U))))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) + | (0xffffU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? 0U : (IData)(this->__PVT__we)))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffffU & this->__PVT__data_structures__DOT__we_per_way) + | (0xffff0000U & (((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? (IData)(this->__PVT__we) + : 0U) << 0x10U))); + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) + | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))); + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))); +} + +void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__3(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__3\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + VL_SIGW(__Vtemp171,127,0,4); + VL_SIGW(__Vtemp172,127,0,4); + VL_SIGW(__Vtemp173,127,0,4); + VL_SIGW(__Vtemp174,127,0,4); + VL_SIGW(__Vtemp175,127,0,4); + VL_SIGW(__Vtemp176,127,0,4); + VL_SIGW(__Vtemp177,127,0,4); + // Body + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U] << 1U)); + this->__PVT__data_structures__DOT__data_use_per_way[0U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[1U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[2U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[3U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][3U]; + this->__PVT__data_structures__DOT__data_use_per_way[4U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[5U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[6U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[7U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][3U]; + this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [0U]); + this->__PVT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [0U] << 1U)); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [0U]))); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [0U])) << 0x15U)); + this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in)); + this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in)); + this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 2U : ((2U == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 4U + : 8U))); + __Vtemp171[0U] = 0U; + __Vtemp171[1U] = 0U; + __Vtemp171[2U] = 0U; + __Vtemp171[3U] = 0U; + __Vtemp172[0U] = 0U; + __Vtemp172[1U] = 0U; + __Vtemp172[2U] = 0U; + __Vtemp172[3U] = 0U; + __Vtemp173[0U] = 0U; + __Vtemp173[1U] = 0U; + __Vtemp173[2U] = 0U; + __Vtemp173[3U] = 0U; + __Vtemp174[0U] = 0U; + __Vtemp174[1U] = 0U; + __Vtemp174[2U] = 0U; + __Vtemp174[3U] = 0U; + __Vtemp175[0U] = 0U; + __Vtemp175[1U] = 0U; + __Vtemp175[2U] = 0U; + __Vtemp175[3U] = 0U; + __Vtemp176[0U] = 0U; + __Vtemp176[1U] = 0U; + __Vtemp176[2U] = 0U; + __Vtemp176[3U] = 0U; + __Vtemp177[0U] = 0U; + __Vtemp177[1U] = 0U; + __Vtemp177[2U] = 0U; + __Vtemp177[3U] = 0U; + this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff00U + & (__Vtemp171[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 8U)) + : ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff0000U + & (__Vtemp172[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x10U)) + : ((3U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp173[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x18U)) + : __Vtemp174[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))]))) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xffff0000U + & (__Vtemp175[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x10U)) + : __Vtemp176[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))]) + : __Vtemp177[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))])); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + this->__PVT__data_structures__DOT__invalid_index = 0U; + this->__PVT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_index = 1U; + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_index = 0U; + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + this->__PVT__data_structures__DOT__hit_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (1U & (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + & ((0x1fffffU & (IData)(this->__PVT__data_structures__DOT__tag_use_per_way)) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U))); + this->__PVT__data_structures__DOT__hit_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (2U & (((((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x1fffffU & (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> 0x15U))) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U) << 1U))); + this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 4U)); + this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 8U)); + this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 0xcU)); + this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[8U] + : this->__PVT__use_write_data); + this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[9U] + : this->__PVT__use_write_data); + this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xaU] + : this->__PVT__use_write_data); + this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xbU] + : this->__PVT__use_write_data); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + this->__PVT__data_structures__DOT__way_index = 0U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 1U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 0U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + this->__PVT__data_structures__DOT__data_write_per_way[0U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[1U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[2U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[3U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__data_write_per_way[4U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[5U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[6U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[7U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index)); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(this->__PVT__write_from_mem) + & (~ (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(this->__PVT__write_from_mem) + & (IData)(this->__PVT__data_structures__DOT__way_use_Qual)) + << 1U)); + this->__Vcellout__data_structures__data_use[0U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[1U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[2U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[3U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__PVT__valid_use = (1U & ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> (IData)(this->__PVT__data_structures__DOT__way_use_Qual))); + this->__PVT__tag_use = (0x1fffffU & ((0x29U >= + (0x3fU & + ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))) + ? (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> + (0x3fU + & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual))))) + : 0U)); + this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))) + ? this->__Vcellout__data_structures__data_use[0U] + : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (this->__Vcellout__data_structures__data_use[0U] + >> 8U) : ((2U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[0U] + >> 0x10U) + : + (this->__Vcellout__data_structures__data_use[0U] + >> 0x18U)))); + this->__PVT__genblk1__BRA__0__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & (IData)(this->__PVT__access)) & (~ (( + (this->__PVT__tag_use + != + (0x1fffffU + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(this->__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in)))); + this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) + | ((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U))))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) + | (0xffffU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? 0U : (IData)(this->__PVT__we)))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffffU & this->__PVT__data_structures__DOT__we_per_way) + | (0xffff0000U & (((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? (IData)(this->__PVT__we) + : 0U) << 0x10U))); + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) + | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))); + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))); +} + +VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__7(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__7\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 0U; + // ALWAYS at ../rtl/cache/VX_cache_data.v:79 + if (vlTOPp->reset) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind = 0x20U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 1U; + } else { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = 4U; + if (this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 + = (1U & ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way)))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 + = (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 1U; + } + if ((1U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[0U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 0U; + } + if ((2U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[1U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[0U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 8U; + } + if ((4U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[1U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[0U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 0x10U; + } + if ((8U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[1U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[0U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 0x18U; + } + if ((0x10U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[1U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 0x20U; + } + if ((0x20U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[2U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[1U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 0x28U; + } + if ((0x40U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[2U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[1U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 0x30U; + } + if ((0x80U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[2U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[1U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 0x38U; + } + if ((0x100U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[2U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 0x40U; + } + if ((0x200U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[3U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[2U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 0x48U; + } + if ((0x400U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[3U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[2U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 0x50U; + } + if ((0x800U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[3U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[2U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 0x58U; + } + if ((0x1000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[3U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 0x60U; + } + if ((0x2000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[4U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[3U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 0x68U; + } + if ((0x4000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[4U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[3U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 0x70U; + } + if ((0x8000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[4U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[3U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 0x78U; + } + } + // ALWAYS at ../rtl/cache/VX_cache_data.v:79 + if (vlTOPp->reset) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind = 0x20U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 1U; + } else { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = 4U; + if (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 + = (1U & ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != (0xffffU & + (this->__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 1U; + } + if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 + = (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 1U; + } + if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 1U; + } + if ((0x10000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[4U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U; + } + if ((0x20000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[5U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[4U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 8U; + } + if ((0x40000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[5U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[4U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0x10U; + } + if ((0x80000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[5U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[4U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0x18U; + } + if ((0x100000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[5U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0x20U; + } + if ((0x200000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[6U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[5U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0x28U; + } + if ((0x400000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[6U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[5U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0x30U; + } + if ((0x800000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[6U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[5U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0x38U; + } + if ((0x1000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[6U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0x40U; + } + if ((0x2000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[7U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[6U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0x48U; + } + if ((0x4000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[7U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[6U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0x50U; + } + if ((0x8000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[7U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[6U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0x58U; + } + if ((0x10000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[7U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0x60U; + } + if ((0x20000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 + = (0xffU & (this->__PVT__data_structures__DOT__data_write_per_way[7U] + >> 8U)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0x68U; + } + if ((0x40000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 + = (0xffU & (this->__PVT__data_structures__DOT__data_write_per_way[7U] + >> 0x10U)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0x70U; + } + if ((0x80000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 + = (0xffU & (this->__PVT__data_structures__DOT__data_write_per_way[7U] + >> 0x18U)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 0x78U; + } + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0U] + = this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xfU][0U] = 0U; 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+ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0U] = 1U; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0U] + = this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0U] + = this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xaU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xaU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xaU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xaU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xbU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xbU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xbU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xbU][3U] = 0U; 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+ } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47), + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47); + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:84 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0U] = 1U; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0U] + = this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32; + } + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]); + this->__PVT__data_structures__DOT__data_use_per_way[0U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[1U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[2U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[3U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][3U]; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [0U]); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [0U]))); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U] << 1U)); + this->__PVT__data_structures__DOT__data_use_per_way[4U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[5U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[6U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[7U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][3U]; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [0U] << 1U)); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [0U])) << 0x15U)); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + this->__PVT__data_structures__DOT__invalid_index = 0U; + this->__PVT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_index = 1U; + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_index = 0U; + this->__PVT__data_structures__DOT__invalid_found = 1U; + } +} + +VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__11(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__11\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + VL_SIGW(__Vtemp245,127,0,4); + VL_SIGW(__Vtemp246,127,0,4); + VL_SIGW(__Vtemp247,127,0,4); + VL_SIGW(__Vtemp248,127,0,4); + VL_SIGW(__Vtemp249,127,0,4); + VL_SIGW(__Vtemp250,127,0,4); + VL_SIGW(__Vtemp251,127,0,4); + // Body + this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in)); + this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in)); + this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 2U : ((2U == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 4U + : 8U))); + __Vtemp245[0U] = 0U; + __Vtemp245[1U] = 0U; + __Vtemp245[2U] = 0U; + __Vtemp245[3U] = 0U; + __Vtemp246[0U] = 0U; + __Vtemp246[1U] = 0U; + __Vtemp246[2U] = 0U; + __Vtemp246[3U] = 0U; + __Vtemp247[0U] = 0U; + __Vtemp247[1U] = 0U; + __Vtemp247[2U] = 0U; + __Vtemp247[3U] = 0U; + __Vtemp248[0U] = 0U; + __Vtemp248[1U] = 0U; + __Vtemp248[2U] = 0U; + __Vtemp248[3U] = 0U; + __Vtemp249[0U] = 0U; + __Vtemp249[1U] = 0U; + __Vtemp249[2U] = 0U; + __Vtemp249[3U] = 0U; + __Vtemp250[0U] = 0U; + __Vtemp250[1U] = 0U; + __Vtemp250[2U] = 0U; + __Vtemp250[3U] = 0U; + __Vtemp251[0U] = 0U; + __Vtemp251[1U] = 0U; + __Vtemp251[2U] = 0U; + __Vtemp251[3U] = 0U; + this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff00U + & (__Vtemp245[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 8U)) + : ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff0000U + & (__Vtemp246[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x10U)) + : ((3U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp247[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x18U)) + : __Vtemp248[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))]))) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xffff0000U + & (__Vtemp249[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x10U)) + : __Vtemp250[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))]) + : __Vtemp251[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))])); + this->__PVT__data_structures__DOT__hit_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (1U & (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + & ((0x1fffffU & (IData)(this->__PVT__data_structures__DOT__tag_use_per_way)) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U))); + this->__PVT__data_structures__DOT__hit_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (2U & (((((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x1fffffU & (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> 0x15U))) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U) << 1U))); + this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 4U)); + this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 8U)); + this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 0xcU)); + this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[8U] + : this->__PVT__use_write_data); + this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[9U] + : this->__PVT__use_write_data); + this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xaU] + : this->__PVT__use_write_data); + this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xbU] + : this->__PVT__use_write_data); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + this->__PVT__data_structures__DOT__way_index = 0U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 1U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 0U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + this->__PVT__data_structures__DOT__data_write_per_way[0U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[1U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[2U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[3U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__data_write_per_way[4U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[5U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[6U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[7U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index)); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(this->__PVT__write_from_mem) + & (~ (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(this->__PVT__write_from_mem) + & (IData)(this->__PVT__data_structures__DOT__way_use_Qual)) + << 1U)); + this->__Vcellout__data_structures__data_use[0U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[1U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[2U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[3U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__PVT__valid_use = (1U & ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> (IData)(this->__PVT__data_structures__DOT__way_use_Qual))); + this->__PVT__tag_use = (0x1fffffU & ((0x29U >= + (0x3fU & + ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))) + ? (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> + (0x3fU + & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual))))) + : 0U)); + this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))) + ? this->__Vcellout__data_structures__data_use[0U] + : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (this->__Vcellout__data_structures__data_use[0U] + >> 8U) : ((2U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[0U] + >> 0x10U) + : + (this->__Vcellout__data_structures__data_use[0U] + >> 0x18U)))); + this->__PVT__genblk1__BRA__0__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & (IData)(this->__PVT__access)) & (~ (( + (this->__PVT__tag_use + != + (0x1fffffU + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(this->__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in)))); + this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) + | ((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U))))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) + | (0xffffU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? 0U : (IData)(this->__PVT__we)))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffffU & this->__PVT__data_structures__DOT__we_per_way) + | (0xffff0000U & (((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? (IData)(this->__PVT__we) + : 0U) << 0x10U))); + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) + | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))); + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))); +} + +void Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__4(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi8::_settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__4\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + VL_SIGW(__Vtemp255,127,0,4); + VL_SIGW(__Vtemp256,127,0,4); + VL_SIGW(__Vtemp257,127,0,4); + VL_SIGW(__Vtemp258,127,0,4); + VL_SIGW(__Vtemp259,127,0,4); + VL_SIGW(__Vtemp260,127,0,4); + VL_SIGW(__Vtemp261,127,0,4); + // Body + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U] << 1U)); + this->__PVT__data_structures__DOT__data_use_per_way[0U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[1U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[2U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[3U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][3U]; + this->__PVT__data_structures__DOT__data_use_per_way[4U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[5U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[6U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[7U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][3U]; + this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [0U]); + this->__PVT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [0U] << 1U)); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [0U]))); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [0U])) << 0x15U)); + this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in)); + this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in)); + this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 2U : ((2U == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 4U + : 8U))); + __Vtemp255[0U] = 0U; + __Vtemp255[1U] = 0U; + __Vtemp255[2U] = 0U; + __Vtemp255[3U] = 0U; + __Vtemp256[0U] = 0U; + __Vtemp256[1U] = 0U; + __Vtemp256[2U] = 0U; + __Vtemp256[3U] = 0U; + __Vtemp257[0U] = 0U; + __Vtemp257[1U] = 0U; + __Vtemp257[2U] = 0U; + __Vtemp257[3U] = 0U; + __Vtemp258[0U] = 0U; + __Vtemp258[1U] = 0U; + __Vtemp258[2U] = 0U; + __Vtemp258[3U] = 0U; + __Vtemp259[0U] = 0U; + __Vtemp259[1U] = 0U; + __Vtemp259[2U] = 0U; + __Vtemp259[3U] = 0U; + __Vtemp260[0U] = 0U; + __Vtemp260[1U] = 0U; + __Vtemp260[2U] = 0U; + __Vtemp260[3U] = 0U; + __Vtemp261[0U] = 0U; + __Vtemp261[1U] = 0U; + __Vtemp261[2U] = 0U; + __Vtemp261[3U] = 0U; + this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff00U + & (__Vtemp255[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 8U)) + : ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff0000U + & (__Vtemp256[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x10U)) + : ((3U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp257[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x18U)) + : __Vtemp258[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))]))) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xffff0000U + & (__Vtemp259[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x10U)) + : __Vtemp260[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))]) + : __Vtemp261[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))])); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + this->__PVT__data_structures__DOT__invalid_index = 0U; + this->__PVT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_index = 1U; + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_index = 0U; + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + this->__PVT__data_structures__DOT__hit_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (1U & (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + & ((0x1fffffU & (IData)(this->__PVT__data_structures__DOT__tag_use_per_way)) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U))); + this->__PVT__data_structures__DOT__hit_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (2U & (((((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x1fffffU & (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> 0x15U))) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U) << 1U))); + this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 4U)); + this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 8U)); + this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 0xcU)); + this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xcU] + : this->__PVT__use_write_data); + this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xdU] + : this->__PVT__use_write_data); + this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xeU] + : this->__PVT__use_write_data); + this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xfU] + : this->__PVT__use_write_data); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + this->__PVT__data_structures__DOT__way_index = 0U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 1U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 0U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + this->__PVT__data_structures__DOT__data_write_per_way[0U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[1U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[2U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[3U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__data_write_per_way[4U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[5U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[6U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[7U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index)); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(this->__PVT__write_from_mem) + & (~ (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(this->__PVT__write_from_mem) + & (IData)(this->__PVT__data_structures__DOT__way_use_Qual)) + << 1U)); + this->__Vcellout__data_structures__data_use[0U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[1U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[2U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[3U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__PVT__valid_use = (1U & ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> (IData)(this->__PVT__data_structures__DOT__way_use_Qual))); + this->__PVT__tag_use = (0x1fffffU & ((0x29U >= + (0x3fU & + ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))) + ? (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> + (0x3fU + & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual))))) + : 0U)); + this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))) + ? this->__Vcellout__data_structures__data_use[0U] + : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (this->__Vcellout__data_structures__data_use[0U] + >> 8U) : ((2U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[0U] + >> 0x10U) + : + (this->__Vcellout__data_structures__data_use[0U] + >> 0x18U)))); + this->__PVT__genblk1__BRA__0__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & (IData)(this->__PVT__access)) & (~ (( + (this->__PVT__tag_use + != + (0x1fffffU + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(this->__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in)))); + this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) + | ((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U))))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) + | (0xffffU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? 0U : (IData)(this->__PVT__we)))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffffU & this->__PVT__data_structures__DOT__we_per_way) + | (0xffff0000U & (((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? (IData)(this->__PVT__we) + : 0U) << 0x10U))); + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) + | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))); + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))); +} + +VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__8(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi8::_sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__8\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + this->__PVT__way_to_update = vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 0U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 0U; + // ALWAYS at ../rtl/cache/VX_cache_data.v:79 + if (vlTOPp->reset) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind = 0x20U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = 1U; + } else { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = 4U; + if (this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 + = (1U & ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way)))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 + = (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = 1U; + } + if ((1U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[0U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = 0U; + } + if ((2U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[1U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[0U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = 8U; + } + if ((4U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[1U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[0U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = 0x10U; + } + if ((8U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[1U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[0U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = 0x18U; + } + if ((0x10U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[1U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = 0x20U; + } + if ((0x20U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[2U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[1U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = 0x28U; + } + if ((0x40U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[2U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[1U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = 0x30U; + } + if ((0x80U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[2U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[1U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = 0x38U; + } + if ((0x100U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[2U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = 0x40U; + } + if ((0x200U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[3U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[2U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = 0x48U; + } + if ((0x400U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[3U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[2U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = 0x50U; + } + if ((0x800U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[3U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[2U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = 0x58U; + } + if ((0x1000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[3U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = 0x60U; + } + if ((0x2000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[4U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[3U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = 0x68U; + } + if ((0x4000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[4U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[3U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = 0x70U; + } + if ((0x8000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[4U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[3U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = 0x78U; + } + } + // ALWAYS at ../rtl/cache/VX_cache_data.v:79 + if (vlTOPp->reset) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind = 0x20U; + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = 1U; + } else { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = 4U; + if (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 + = (1U & ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != (0xffffU & + (this->__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = 1U; + } + if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 + = (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = 1U; + } + if ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))) { + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = 1U; + } + if ((0x10000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[4U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = 0U; + } + if ((0x20000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[5U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[4U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = 8U; + } + if ((0x40000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[5U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[4U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = 0x10U; + } + if ((0x80000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[5U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[4U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = 0x18U; + } + if ((0x100000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[5U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = 0x20U; + } + if ((0x200000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[6U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[5U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = 0x28U; + } + if ((0x400000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[6U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[5U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = 0x30U; + } + if ((0x800000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[6U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[5U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = 0x38U; + } + if ((0x1000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[6U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = 0x40U; + } + if ((0x2000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[7U] + << 0x18U) | (this->__PVT__data_structures__DOT__data_write_per_way[6U] + >> 8U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = 0x48U; + } + if ((0x4000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[7U] + << 0x10U) | (this->__PVT__data_structures__DOT__data_write_per_way[6U] + >> 0x10U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = 0x50U; + } + if ((0x8000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 + = (0xffU & ((this->__PVT__data_structures__DOT__data_write_per_way[7U] + << 8U) | (this->__PVT__data_structures__DOT__data_write_per_way[6U] + >> 0x18U))); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = 0x58U; + } + if ((0x10000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 + = (0xffU & this->__PVT__data_structures__DOT__data_write_per_way[7U]); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = 0x60U; + } + if ((0x20000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 + = (0xffU & (this->__PVT__data_structures__DOT__data_write_per_way[7U] + >> 8U)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = 0x68U; + } + if ((0x40000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 + = (0xffU & (this->__PVT__data_structures__DOT__data_write_per_way[7U] + >> 0x10U)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = 0x70U; + } + if ((0x80000000U & this->__PVT__data_structures__DOT__we_per_way)) { + this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 + = (0xffU & (this->__PVT__data_structures__DOT__data_write_per_way[7U] + >> 0x18U)); + this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 1U; + this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = 0x78U; + } + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[0U] + = this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[1U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[2U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[3U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[4U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[5U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[6U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[7U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[8U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[9U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xaU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xbU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xcU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xdU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xeU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[0xfU][0U] = 0U; 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+ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[0U] = 1U; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[0U] + = this->__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:85 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[0U] + = this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:82 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[1U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[2U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[3U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[4U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[5U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[6U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[7U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[8U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[9U][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xaU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xaU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xaU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xaU][3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xbU][0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xbU][1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xbU][2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[0xbU][3U] = 0U; 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+ } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47) { + VL_ASSIGNSEL_WIII(8,(IData)(this->__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47), + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U], this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47); + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:84 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[0U] = 1U; + } + // ALWAYSPOST at ../rtl/cache/VX_cache_data.v:83 + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[1U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[2U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[3U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[4U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[5U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[6U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[7U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[8U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[9U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xaU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xbU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xcU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xdU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xeU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0xfU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x10U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x11U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x12U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x13U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x14U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x15U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x16U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x17U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x18U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x19U] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1aU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1bU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1cU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1dU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1eU] = 0U; + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0x1fU] = 0U; + } + if (this->__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32) { + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[0U] + = this->__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32; + } + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]); + this->__PVT__data_structures__DOT__data_use_per_way[0U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[1U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[2U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[3U] + = this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][3U]; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [0U]); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x3ffffe00000) & this->__PVT__data_structures__DOT__tag_use_per_way) + | (IData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [0U]))); + this->__PVT__data_structures__DOT__dirty_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__dirty_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U] << 1U)); + this->__PVT__data_structures__DOT__data_use_per_way[4U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][0U]; + this->__PVT__data_structures__DOT__data_use_per_way[5U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][1U]; + this->__PVT__data_structures__DOT__data_use_per_way[6U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][2U]; + this->__PVT__data_structures__DOT__data_use_per_way[7U] + = this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data + [0U][3U]; + this->__PVT__data_structures__DOT__valid_use_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)) + | (this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid + [0U] << 1U)); + this->__PVT__data_structures__DOT__tag_use_per_way + = ((VL_ULL(0x1fffff) & this->__PVT__data_structures__DOT__tag_use_per_way) + | ((QData)((IData)(this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag + [0U])) << 0x15U)); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + this->__PVT__data_structures__DOT__invalid_index = 0U; + this->__PVT__data_structures__DOT__invalid_found = 0U; + if ((1U & (~ ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U)))) { + this->__PVT__data_structures__DOT__invalid_index = 1U; + this->__PVT__data_structures__DOT__invalid_found = 1U; + } + if ((1U & (~ (IData)(this->__PVT__data_structures__DOT__valid_use_per_way)))) { + this->__PVT__data_structures__DOT__invalid_index = 0U; + this->__PVT__data_structures__DOT__invalid_found = 1U; + } +} + +VL_INLINE_OPT void Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__12(Vcache_simX__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi8::_combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__12\n"); ); + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + VL_SIGW(__Vtemp329,127,0,4); + VL_SIGW(__Vtemp330,127,0,4); + VL_SIGW(__Vtemp331,127,0,4); + VL_SIGW(__Vtemp332,127,0,4); + VL_SIGW(__Vtemp333,127,0,4); + VL_SIGW(__Vtemp334,127,0,4); + VL_SIGW(__Vtemp335,127,0,4); + // Body + this->__PVT__write_from_mem = ((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in)); + this->__PVT__access = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in)); + this->__PVT__sb_mask = ((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 2U : ((2U == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 4U + : 8U))); + __Vtemp329[0U] = 0U; + __Vtemp329[1U] = 0U; + __Vtemp329[2U] = 0U; + __Vtemp329[3U] = 0U; + __Vtemp330[0U] = 0U; + __Vtemp330[1U] = 0U; + __Vtemp330[2U] = 0U; + __Vtemp330[3U] = 0U; + __Vtemp331[0U] = 0U; + __Vtemp331[1U] = 0U; + __Vtemp331[2U] = 0U; + __Vtemp331[3U] = 0U; + __Vtemp332[0U] = 0U; + __Vtemp332[1U] = 0U; + __Vtemp332[2U] = 0U; + __Vtemp332[3U] = 0U; + __Vtemp333[0U] = 0U; + __Vtemp333[1U] = 0U; + __Vtemp333[2U] = 0U; + __Vtemp333[3U] = 0U; + __Vtemp334[0U] = 0U; + __Vtemp334[1U] = 0U; + __Vtemp334[2U] = 0U; + __Vtemp334[3U] = 0U; + __Vtemp335[0U] = 0U; + __Vtemp335[1U] = 0U; + __Vtemp335[2U] = 0U; + __Vtemp335[3U] = 0U; + this->__PVT__use_write_data = ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff00U + & (__Vtemp329[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 8U)) + : ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff0000U + & (__Vtemp330[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x10U)) + : ((3U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp331[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x18U)) + : __Vtemp332[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))]))) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)) + ? ((2U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xffff0000U + & (__Vtemp333[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x10U)) + : __Vtemp334[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))]) + : __Vtemp335[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))])); + this->__PVT__data_structures__DOT__hit_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (1U & (((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + & ((0x1fffffU & (IData)(this->__PVT__data_structures__DOT__tag_use_per_way)) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U))); + this->__PVT__data_structures__DOT__hit_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way)) + | (2U & (((((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> 1U) & ((0x1fffffU & (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> 0x15U))) + == (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU)))) + ? 1U : 0U) << 1U))); + this->__PVT__we = ((0xff0fU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 4U)); + this->__PVT__we = ((0xf0ffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 8U)); + this->__PVT__we = ((0xfffU & (IData)(this->__PVT__we)) + | (((IData)(this->__PVT__write_from_mem) + ? 0xfU : 0U) << 0xcU)); + this->__PVT__data_write[0U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xcU] + : this->__PVT__use_write_data); + this->__PVT__data_write[1U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xdU] + : this->__PVT__use_write_data); + this->__PVT__data_write[2U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xeU] + : this->__PVT__use_write_data); + this->__PVT__data_write[3U] = ((IData)(this->__PVT__write_from_mem) + ? vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xfU] + : this->__PVT__use_write_data); + // ALWAYS at ../rtl/VX_generic_priority_encoder.v:17 + this->__PVT__data_structures__DOT__way_index = 0U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 0U; + if ((2U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 1U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + if ((1U & (IData)(this->__PVT__data_structures__DOT__hit_per_way))) { + this->__PVT__data_structures__DOT__way_index = 0U; + this->__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = 1U; + } + this->__PVT__data_structures__DOT__data_write_per_way[0U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[1U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[2U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[3U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__data_write_per_way[4U] + = this->__PVT__data_write[0U]; + this->__PVT__data_structures__DOT__data_write_per_way[5U] + = this->__PVT__data_write[1U]; + this->__PVT__data_structures__DOT__data_write_per_way[6U] + = this->__PVT__data_write[2U]; + this->__PVT__data_structures__DOT__data_write_per_way[7U] + = this->__PVT__data_write[3U]; + this->__PVT__data_structures__DOT__way_use_Qual + = ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + ? (IData)(this->__PVT__way_to_update) : (IData)(this->__PVT__data_structures__DOT__way_index)); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((2U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | ((IData)(this->__PVT__write_from_mem) + & (~ (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))); + this->__PVT__data_structures__DOT__write_from_mem_per_way + = ((1U & (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way)) + | (((IData)(this->__PVT__write_from_mem) + & (IData)(this->__PVT__data_structures__DOT__way_use_Qual)) + << 1U)); + this->__Vcellout__data_structures__data_use[0U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[1U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[2U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__Vcellout__data_structures__data_use[3U] + = (((0U == (0x1fU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))) ? 0U : (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (this->__PVT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 2U)))] >> (0x1fU + & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + << 7U)))); + this->__PVT__valid_use = (1U & ((IData)(this->__PVT__data_structures__DOT__valid_use_per_way) + >> (IData)(this->__PVT__data_structures__DOT__way_use_Qual))); + this->__PVT__tag_use = (0x1fffffU & ((0x29U >= + (0x3fU & + ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual)))) + ? (IData)( + (this->__PVT__data_structures__DOT__tag_use_per_way + >> + (0x3fU + & ((IData)(0x15U) + * (IData)(this->__PVT__data_structures__DOT__way_use_Qual))))) + : 0U)); + this->__PVT__data_unQual = (((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + | (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read))) + ? this->__Vcellout__data_structures__data_use[0U] + : ((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (this->__Vcellout__data_structures__data_use[0U] + >> 8U) : ((2U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? + (this->__Vcellout__data_structures__data_use[0U] + >> 0x10U) + : + (this->__Vcellout__data_structures__data_use[0U] + >> 0x18U)))); + this->__PVT__genblk1__BRA__0__KET____DOT__normal_write + = (((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write) + & (IData)(this->__PVT__access)) & (~ (( + (this->__PVT__tag_use + != + (0x1fffffU + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(this->__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in)))); + this->__PVT__we = ((0xfff0U & (IData)(this->__PVT__we)) + | ((IData)(this->__PVT__write_from_mem) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? 0xfU : (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (0U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? (IData)(this->__PVT__sb_mask) + : + (((IData)(this->__PVT__genblk1__BRA__0__KET____DOT__normal_write) + & (1U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write))) + ? + ((0U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 3U + : 0xcU) + : 0U))))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffff0000U & this->__PVT__data_structures__DOT__we_per_way) + | (0xffffU & ((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? 0U : (IData)(this->__PVT__we)))); + this->__PVT__data_structures__DOT__we_per_way = + ((0xffffU & this->__PVT__data_structures__DOT__we_per_way) + | (0xffff0000U & (((IData)(this->__PVT__data_structures__DOT__way_use_Qual) + ? (IData)(this->__PVT__we) + : 0U) << 0x10U))); + this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & this->__PVT__data_structures__DOT__we_per_way))) + | (IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way))); + this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty + = (1U & (((~ this->__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U != (0xffffU & (this->__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(this->__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))); +} + +void Vcache_simX_VX_Cache_Bank__pi8::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_Cache_Bank__pi8::_ctor_var_reset\n"); ); + // Body + rst = VL_RAND_RESET_I(1); + clk = VL_RAND_RESET_I(1); + state = VL_RAND_RESET_I(4); + actual_index = VL_RAND_RESET_I(5); + o_tag = VL_RAND_RESET_I(21); + block_offset = VL_RAND_RESET_I(2); + writedata = VL_RAND_RESET_I(32); + valid_in = VL_RAND_RESET_I(1); + read_or_write = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(128,fetched_writedata); + i_p_mem_read = VL_RAND_RESET_I(3); + i_p_mem_write = VL_RAND_RESET_I(3); + byte_select = VL_RAND_RESET_I(2); + evicted_way = VL_RAND_RESET_I(1); + readdata = VL_RAND_RESET_I(32); + hit = VL_RAND_RESET_I(1); + eviction_wb = VL_RAND_RESET_I(1); + eviction_addr = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(128,data_evicted); + __PVT__tag_use = VL_RAND_RESET_I(21); + __PVT__valid_use = VL_RAND_RESET_I(1); + __PVT__access = VL_RAND_RESET_I(1); + __PVT__write_from_mem = VL_RAND_RESET_I(1); + __PVT__way_to_update = VL_RAND_RESET_I(1); + __PVT__data_unQual = VL_RAND_RESET_I(32); + __PVT__use_write_data = VL_RAND_RESET_I(32); + __PVT__sb_mask = VL_RAND_RESET_I(4); + __PVT__we = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(128,__PVT__data_write); + VL_RAND_RESET_W(128,__Vcellout__data_structures__data_use); + __PVT__genblk1__BRA__0__KET____DOT__normal_write = VL_RAND_RESET_I(1); + __PVT__data_structures__DOT__tag_use_per_way = VL_RAND_RESET_Q(42); + VL_RAND_RESET_W(256,__PVT__data_structures__DOT__data_use_per_way); + __PVT__data_structures__DOT__valid_use_per_way = VL_RAND_RESET_I(2); + __PVT__data_structures__DOT__dirty_use_per_way = VL_RAND_RESET_I(2); + __PVT__data_structures__DOT__hit_per_way = VL_RAND_RESET_I(2); + __PVT__data_structures__DOT__we_per_way = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(256,__PVT__data_structures__DOT__data_write_per_way); + __PVT__data_structures__DOT__write_from_mem_per_way = VL_RAND_RESET_I(2); + __PVT__data_structures__DOT__invalid_found = VL_RAND_RESET_I(1); + __PVT__data_structures__DOT__way_index = VL_RAND_RESET_I(1); + __PVT__data_structures__DOT__invalid_index = VL_RAND_RESET_I(1); + __PVT__data_structures__DOT__way_use_Qual = VL_RAND_RESET_I(1); + __PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found = VL_RAND_RESET_I(1); + __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + VL_RAND_RESET_W(128,__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[__Vi0] = VL_RAND_RESET_I(1); + }} + __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f = VL_RAND_RESET_I(32); + __PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind = VL_RAND_RESET_I(32); + __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + VL_RAND_RESET_W(128,__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[__Vi0] = VL_RAND_RESET_I(1); + }} + __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f = VL_RAND_RESET_I(32); + __PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind = VL_RAND_RESET_I(32); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0 = VL_RAND_RESET_I(1); + __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = VL_RAND_RESET_I(1); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32 = VL_RAND_RESET_I(1); + __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = VL_RAND_RESET_I(21); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32 = VL_RAND_RESET_I(1); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47 = VL_RAND_RESET_I(1); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0 = VL_RAND_RESET_I(1); + __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = VL_RAND_RESET_I(1); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32 = VL_RAND_RESET_I(1); + __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = VL_RAND_RESET_I(21); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32 = VL_RAND_RESET_I(1); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46 = VL_RAND_RESET_I(1); + __Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = VL_RAND_RESET_I(7); + __Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = VL_RAND_RESET_I(8); + __Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47 = VL_RAND_RESET_I(1); +} diff --git a/simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h b/simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h new file mode 100644 index 00000000..adbb3427 --- /dev/null +++ b/simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h @@ -0,0 +1,230 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design internal header +// See Vcache_simX.h for the primary calling header + +#ifndef _Vcache_simX_VX_Cache_Bank__pi8_H_ +#define _Vcache_simX_VX_Cache_Bank__pi8_H_ + +#include "verilated.h" + +class Vcache_simX__Syms; +class VerilatedVcd; + +//---------- + +VL_MODULE(Vcache_simX_VX_Cache_Bank__pi8) { + public: + + // PORTS + VL_IN8(rst,0,0); + VL_IN8(clk,0,0); + VL_IN8(state,3,0); + VL_IN8(actual_index,4,0); + VL_IN8(block_offset,1,0); + VL_IN8(valid_in,0,0); + VL_IN8(read_or_write,0,0); + VL_IN8(i_p_mem_read,2,0); + VL_IN8(i_p_mem_write,2,0); + VL_IN8(byte_select,1,0); + VL_IN8(evicted_way,0,0); + VL_OUT8(hit,0,0); + VL_OUT8(eviction_wb,0,0); + VL_IN(o_tag,20,0); + VL_IN(writedata,31,0); + VL_INW(fetched_writedata,127,0,4); + VL_OUT(readdata,31,0); + VL_OUT(eviction_addr,31,0); + VL_OUTW(data_evicted,127,0,4); + + // LOCAL SIGNALS + VL_SIG8(__PVT__valid_use,0,0); + VL_SIG8(__PVT__access,0,0); + VL_SIG8(__PVT__write_from_mem,0,0); + VL_SIG8(__PVT__way_to_update,0,0); + VL_SIG8(__PVT__sb_mask,3,0); + VL_SIG16(__PVT__we,15,0); + VL_SIG8(__PVT__genblk1__BRA__0__KET____DOT__normal_write,0,0); + VL_SIG8(__PVT__data_structures__DOT__valid_use_per_way,1,0); + VL_SIG8(__PVT__data_structures__DOT__dirty_use_per_way,1,0); + VL_SIG8(__PVT__data_structures__DOT__hit_per_way,1,0); + VL_SIG(__PVT__data_structures__DOT__we_per_way,31,0); + VL_SIG8(__PVT__data_structures__DOT__write_from_mem_per_way,1,0); + VL_SIG8(__PVT__data_structures__DOT__invalid_found,0,0); + VL_SIG8(__PVT__data_structures__DOT__way_index,0,0); + VL_SIG8(__PVT__data_structures__DOT__invalid_index,0,0); + VL_SIG8(__PVT__data_structures__DOT__way_use_Qual,0,0); + VL_SIG8(__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found,0,0); + VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty,0,0); + VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty,0,0); + VL_SIG(__PVT__tag_use,20,0); + VL_SIG(__PVT__data_unQual,31,0); + VL_SIG(__PVT__use_write_data,31,0); + VL_SIGW(__PVT__data_write,127,0,4); + VL_SIG64(__PVT__data_structures__DOT__tag_use_per_way,41,0); + VL_SIGW(__PVT__data_structures__DOT__data_use_per_way,255,0,8); + VL_SIGW(__PVT__data_structures__DOT__data_write_per_way,255,0,8); + VL_SIG(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f,31,0); + VL_SIG(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind,31,0); + VL_SIG(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f,31,0); + VL_SIG(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind,31,0); + VL_SIGW(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[32],127,0,4); + VL_SIG(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[32],20,0); + VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[32],0,0); + VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[32],0,0); + VL_SIGW(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[32],127,0,4); + VL_SIG(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[32],20,0); + VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[32],0,0); + VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[32],0,0); + + // LOCAL VARIABLES + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0,0,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32,0,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32,0,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32,0,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47,0,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0,0,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32,0,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32,0,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32,0,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46,0,0); + VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47,6,0); + VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47,7,0); + VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47,0,0); + VL_SIGW(__Vcellout__data_structures__data_use,127,0,4); + VL_SIG(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32,20,0); + VL_SIG(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32,20,0); + + // INTERNAL VARIABLES + private: + Vcache_simX__Syms* __VlSymsp; // Symbol table + public: + + // PARAMETERS + + // CONSTRUCTORS + private: + Vcache_simX_VX_Cache_Bank__pi8& operator= (const Vcache_simX_VX_Cache_Bank__pi8&); ///< Copying not allowed + Vcache_simX_VX_Cache_Bank__pi8(const Vcache_simX_VX_Cache_Bank__pi8&); ///< Copying not allowed + public: + Vcache_simX_VX_Cache_Bank__pi8(const char* name="TOP"); + ~Vcache_simX_VX_Cache_Bank__pi8(); + void trace (VerilatedVcdC* tfp, int levels, int options=0); + + // API METHODS + + // INTERNAL METHODS + void __Vconfigure(Vcache_simX__Syms* symsp, bool first); + void _combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__9(Vcache_simX__Syms* __restrict vlSymsp); + void _combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__10(Vcache_simX__Syms* __restrict vlSymsp); + void _combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__11(Vcache_simX__Syms* __restrict vlSymsp); + void _combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__12(Vcache_simX__Syms* __restrict vlSymsp); + private: + void _ctor_var_reset(); + public: + void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__5(Vcache_simX__Syms* __restrict vlSymsp); + void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__6(Vcache_simX__Syms* __restrict vlSymsp); + void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__7(Vcache_simX__Syms* __restrict vlSymsp); + void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__8(Vcache_simX__Syms* __restrict vlSymsp); + void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__1(Vcache_simX__Syms* __restrict vlSymsp); + void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__2(Vcache_simX__Syms* __restrict vlSymsp); + void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__3(Vcache_simX__Syms* __restrict vlSymsp); + void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__4(Vcache_simX__Syms* __restrict vlSymsp); + static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code); +} VL_ATTR_ALIGNED(128); + +#endif // guard diff --git a/simX/obj_dir/Vcache_simX_VX_dcache_request_inter.cpp b/simX/obj_dir/Vcache_simX_VX_dcache_request_inter.cpp new file mode 100644 index 00000000..41260eb1 --- /dev/null +++ b/simX/obj_dir/Vcache_simX_VX_dcache_request_inter.cpp @@ -0,0 +1,37 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Vcache_simX.h for the primary calling header + +#include "Vcache_simX_VX_dcache_request_inter.h" // For This +#include "Vcache_simX__Syms.h" + + +//-------------------- +// STATIC VARIABLES + + +//-------------------- + +VL_CTOR_IMP(Vcache_simX_VX_dcache_request_inter) { + // Reset internal values + // Reset structure values + _ctor_var_reset(); +} + +void Vcache_simX_VX_dcache_request_inter::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +Vcache_simX_VX_dcache_request_inter::~Vcache_simX_VX_dcache_request_inter() { +} + +//-------------------- +// Internal Methods + +void Vcache_simX_VX_dcache_request_inter::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_dcache_request_inter::_ctor_var_reset\n"); ); + // Body + VL_RAND_RESET_W(128,out_cache_driver_in_address); + out_cache_driver_in_valid = VL_RAND_RESET_I(4); +} diff --git a/simX/obj_dir/Vcache_simX_VX_dcache_request_inter.h b/simX/obj_dir/Vcache_simX_VX_dcache_request_inter.h new file mode 100644 index 00000000..b1fa3b55 --- /dev/null +++ b/simX/obj_dir/Vcache_simX_VX_dcache_request_inter.h @@ -0,0 +1,54 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design internal header +// See Vcache_simX.h for the primary calling header + +#ifndef _Vcache_simX_VX_dcache_request_inter_H_ +#define _Vcache_simX_VX_dcache_request_inter_H_ + +#include "verilated.h" + +class Vcache_simX__Syms; +class VerilatedVcd; + +//---------- + +VL_MODULE(Vcache_simX_VX_dcache_request_inter) { + public: + + // PORTS + + // LOCAL SIGNALS + VL_SIG8(out_cache_driver_in_valid,3,0); + VL_SIGW(out_cache_driver_in_address,127,0,4); + + // LOCAL VARIABLES + + // INTERNAL VARIABLES + private: + Vcache_simX__Syms* __VlSymsp; // Symbol table + public: + + // PARAMETERS + + // CONSTRUCTORS + private: + Vcache_simX_VX_dcache_request_inter& operator= (const Vcache_simX_VX_dcache_request_inter&); ///< Copying not allowed + Vcache_simX_VX_dcache_request_inter(const Vcache_simX_VX_dcache_request_inter&); ///< Copying not allowed + public: + Vcache_simX_VX_dcache_request_inter(const char* name="TOP"); + ~Vcache_simX_VX_dcache_request_inter(); + void trace (VerilatedVcdC* tfp, int levels, int options=0); + + // API METHODS + + // INTERNAL METHODS + void __Vconfigure(Vcache_simX__Syms* symsp, bool first); + private: + void _ctor_var_reset(); + public: + static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code); +} VL_ATTR_ALIGNED(128); + +#endif // guard diff --git a/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp b/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp new file mode 100644 index 00000000..b9911c9b --- /dev/null +++ b/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp @@ -0,0 +1,36 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Vcache_simX.h for the primary calling header + +#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h" // For This +#include "Vcache_simX__Syms.h" + + +//-------------------- +// STATIC VARIABLES + + +//-------------------- + +VL_CTOR_IMP(Vcache_simX_VX_dram_req_rsp_inter__N1_NB4) { + // Reset internal values + // Reset structure values + _ctor_var_reset(); +} + +void Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::~Vcache_simX_VX_dram_req_rsp_inter__N1_NB4() { +} + +//-------------------- +// Internal Methods + +void Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::_ctor_var_reset\n"); ); + // Body + VL_RAND_RESET_W(128,i_m_readdata); +} diff --git a/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h b/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h new file mode 100644 index 00000000..5af0a97d --- /dev/null +++ b/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h @@ -0,0 +1,53 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design internal header +// See Vcache_simX.h for the primary calling header + +#ifndef _Vcache_simX_VX_dram_req_rsp_inter__N1_NB4_H_ +#define _Vcache_simX_VX_dram_req_rsp_inter__N1_NB4_H_ + +#include "verilated.h" + +class Vcache_simX__Syms; +class VerilatedVcd; + +//---------- + +VL_MODULE(Vcache_simX_VX_dram_req_rsp_inter__N1_NB4) { + public: + + // PORTS + + // LOCAL SIGNALS + VL_SIGW(i_m_readdata,127,0,4); + + // LOCAL VARIABLES + + // INTERNAL VARIABLES + private: + Vcache_simX__Syms* __VlSymsp; // Symbol table + public: + + // PARAMETERS + + // CONSTRUCTORS + private: + Vcache_simX_VX_dram_req_rsp_inter__N1_NB4& operator= (const Vcache_simX_VX_dram_req_rsp_inter__N1_NB4&); ///< Copying not allowed + Vcache_simX_VX_dram_req_rsp_inter__N1_NB4(const Vcache_simX_VX_dram_req_rsp_inter__N1_NB4&); ///< Copying not allowed + public: + Vcache_simX_VX_dram_req_rsp_inter__N1_NB4(const char* name="TOP"); + ~Vcache_simX_VX_dram_req_rsp_inter__N1_NB4(); + void trace (VerilatedVcdC* tfp, int levels, int options=0); + + // API METHODS + + // INTERNAL METHODS + void __Vconfigure(Vcache_simX__Syms* symsp, bool first); + private: + void _ctor_var_reset(); + public: + static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code); +} VL_ATTR_ALIGNED(128); + +#endif // guard diff --git a/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp b/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp new file mode 100644 index 00000000..dc2d2e02 --- /dev/null +++ b/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp @@ -0,0 +1,36 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Vcache_simX.h for the primary calling header + +#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h" // For This +#include "Vcache_simX__Syms.h" + + +//-------------------- +// STATIC VARIABLES + + +//-------------------- + +VL_CTOR_IMP(Vcache_simX_VX_dram_req_rsp_inter__N4_NB4) { + // Reset internal values + // Reset structure values + _ctor_var_reset(); +} + +void Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::~Vcache_simX_VX_dram_req_rsp_inter__N4_NB4() { +} + +//-------------------- +// Internal Methods + +void Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::_ctor_var_reset\n"); ); + // Body + VL_RAND_RESET_W(512,i_m_readdata); +} diff --git a/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h b/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h new file mode 100644 index 00000000..8fcfc057 --- /dev/null +++ b/simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h @@ -0,0 +1,53 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design internal header +// See Vcache_simX.h for the primary calling header + +#ifndef _Vcache_simX_VX_dram_req_rsp_inter__N4_NB4_H_ +#define _Vcache_simX_VX_dram_req_rsp_inter__N4_NB4_H_ + +#include "verilated.h" + +class Vcache_simX__Syms; +class VerilatedVcd; + +//---------- + +VL_MODULE(Vcache_simX_VX_dram_req_rsp_inter__N4_NB4) { + public: + + // PORTS + + // LOCAL SIGNALS + VL_SIGW(i_m_readdata,511,0,16); + + // LOCAL VARIABLES + + // INTERNAL VARIABLES + private: + Vcache_simX__Syms* __VlSymsp; // Symbol table + public: + + // PARAMETERS + + // CONSTRUCTORS + private: + Vcache_simX_VX_dram_req_rsp_inter__N4_NB4& operator= (const Vcache_simX_VX_dram_req_rsp_inter__N4_NB4&); ///< Copying not allowed + Vcache_simX_VX_dram_req_rsp_inter__N4_NB4(const Vcache_simX_VX_dram_req_rsp_inter__N4_NB4&); ///< Copying not allowed + public: + Vcache_simX_VX_dram_req_rsp_inter__N4_NB4(const char* name="TOP"); + ~Vcache_simX_VX_dram_req_rsp_inter__N4_NB4(); + void trace (VerilatedVcdC* tfp, int levels, int options=0); + + // API METHODS + + // INTERNAL METHODS + void __Vconfigure(Vcache_simX__Syms* symsp, bool first); + private: + void _ctor_var_reset(); + public: + static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code); +} VL_ATTR_ALIGNED(128); + +#endif // guard diff --git a/simX/obj_dir/Vcache_simX__ALL.a b/simX/obj_dir/Vcache_simX__ALL.a new file mode 100644 index 00000000..efd7f2e4 Binary files /dev/null and b/simX/obj_dir/Vcache_simX__ALL.a differ diff --git a/simX/obj_dir/Vcache_simX__ALLcls.cpp b/simX/obj_dir/Vcache_simX__ALLcls.cpp new file mode 100644 index 00000000..ac39543f --- /dev/null +++ b/simX/obj_dir/Vcache_simX__ALLcls.cpp @@ -0,0 +1,7 @@ +// DESCRIPTION: Generated by verilator_includer via makefile +#define VL_INCLUDE_OPT include +#include "Vcache_simX.cpp" +#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp" +#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp" +#include "Vcache_simX_VX_dcache_request_inter.cpp" +#include "Vcache_simX_VX_Cache_Bank__pi8.cpp" diff --git a/simX/obj_dir/Vcache_simX__ALLcls.d b/simX/obj_dir/Vcache_simX__ALLcls.d new file mode 100644 index 00000000..0768f6c1 --- /dev/null +++ b/simX/obj_dir/Vcache_simX__ALLcls.d @@ -0,0 +1,11 @@ +Vcache_simX__ALLcls.o: Vcache_simX__ALLcls.cpp Vcache_simX.cpp \ + Vcache_simX.h /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilatedos.h Vcache_simX__Syms.h \ + Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h \ + Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h \ + Vcache_simX_VX_dcache_request_inter.h Vcache_simX_VX_Cache_Bank__pi8.h \ + Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp \ + Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp \ + Vcache_simX_VX_dcache_request_inter.cpp \ + Vcache_simX_VX_Cache_Bank__pi8.cpp diff --git a/simX/obj_dir/Vcache_simX__ALLcls.o b/simX/obj_dir/Vcache_simX__ALLcls.o new file mode 100644 index 00000000..f7a0f234 Binary files /dev/null and b/simX/obj_dir/Vcache_simX__ALLcls.o differ diff --git a/simX/obj_dir/Vcache_simX__ALLsup.cpp b/simX/obj_dir/Vcache_simX__ALLsup.cpp new file mode 100644 index 00000000..e6a8008f --- /dev/null +++ b/simX/obj_dir/Vcache_simX__ALLsup.cpp @@ -0,0 +1,5 @@ +// DESCRIPTION: Generated by verilator_includer via makefile +#define VL_INCLUDE_OPT include +#include "Vcache_simX__Trace.cpp" +#include "Vcache_simX__Syms.cpp" +#include "Vcache_simX__Trace__Slow.cpp" diff --git a/simX/obj_dir/Vcache_simX__ALLsup.d b/simX/obj_dir/Vcache_simX__ALLsup.d new file mode 100644 index 00000000..e8cbf34b --- /dev/null +++ b/simX/obj_dir/Vcache_simX__ALLsup.d @@ -0,0 +1,10 @@ +Vcache_simX__ALLsup.o: Vcache_simX__ALLsup.cpp Vcache_simX__Trace.cpp \ + /usr/share/verilator/include/verilated_vcd_c.h \ + /usr/share/verilator/include/verilatedos.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h Vcache_simX__Syms.h \ + /usr/share/verilator/include/verilated.h Vcache_simX.h \ + Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h \ + Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h \ + Vcache_simX_VX_dcache_request_inter.h Vcache_simX_VX_Cache_Bank__pi8.h \ + Vcache_simX__Syms.cpp Vcache_simX__Trace__Slow.cpp diff --git a/simX/obj_dir/Vcache_simX__ALLsup.o b/simX/obj_dir/Vcache_simX__ALLsup.o new file mode 100644 index 00000000..5a665d64 Binary files /dev/null and b/simX/obj_dir/Vcache_simX__ALLsup.o differ diff --git a/simX/obj_dir/Vcache_simX__Syms.cpp b/simX/obj_dir/Vcache_simX__Syms.cpp new file mode 100644 index 00000000..4d621b00 --- /dev/null +++ b/simX/obj_dir/Vcache_simX__Syms.cpp @@ -0,0 +1,45 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table implementation internals + +#include "Vcache_simX__Syms.h" +#include "Vcache_simX.h" +#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h" +#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h" +#include "Vcache_simX_VX_dcache_request_inter.h" +#include "Vcache_simX_VX_Cache_Bank__pi8.h" + +// FUNCTIONS +Vcache_simX__Syms::Vcache_simX__Syms(Vcache_simX* topp, const char* namep) + // Setup locals + : __Vm_namep(namep) + , __Vm_activity(false) + , __Vm_didInit(false) + // Setup submodule names + , TOP__cache_simX__DOT__VX_dcache_req (Verilated::catName(topp->name(),"cache_simX.VX_dcache_req")) + , TOP__cache_simX__DOT__VX_dram_req_rsp (Verilated::catName(topp->name(),"cache_simX.VX_dram_req_rsp")) + , TOP__cache_simX__DOT__VX_dram_req_rsp_icache (Verilated::catName(topp->name(),"cache_simX.VX_dram_req_rsp_icache")) + , TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[0].bank_structure")) + , TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[1].bank_structure")) + , TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[2].bank_structure")) + , TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[3].bank_structure")) +{ + // Pointer to top level + TOPp = topp; + // Setup each module's pointers to their submodules + TOPp->__PVT__cache_simX__DOT__VX_dcache_req = &TOP__cache_simX__DOT__VX_dcache_req; + TOPp->__PVT__cache_simX__DOT__VX_dram_req_rsp = &TOP__cache_simX__DOT__VX_dram_req_rsp; + TOPp->__PVT__cache_simX__DOT__VX_dram_req_rsp_icache = &TOP__cache_simX__DOT__VX_dram_req_rsp_icache; + TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure; + TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure; + TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure; + TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure; + // Setup each module's pointer back to symbol table (for public functions) + TOPp->__Vconfigure(this, true); + TOP__cache_simX__DOT__VX_dcache_req.__Vconfigure(this, true); + TOP__cache_simX__DOT__VX_dram_req_rsp.__Vconfigure(this, true); + TOP__cache_simX__DOT__VX_dram_req_rsp_icache.__Vconfigure(this, true); + TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vconfigure(this, true); + TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vconfigure(this, false); + TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vconfigure(this, false); + TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vconfigure(this, false); +} diff --git a/simX/obj_dir/Vcache_simX__Syms.h b/simX/obj_dir/Vcache_simX__Syms.h new file mode 100644 index 00000000..50667b34 --- /dev/null +++ b/simX/obj_dir/Vcache_simX__Syms.h @@ -0,0 +1,47 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table internal header +// +// Internal details; most calling programs do not need this header + +#ifndef _Vcache_simX__Syms_H_ +#define _Vcache_simX__Syms_H_ + +#include "verilated.h" + +// INCLUDE MODULE CLASSES +#include "Vcache_simX.h" +#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h" +#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h" +#include "Vcache_simX_VX_dcache_request_inter.h" +#include "Vcache_simX_VX_Cache_Bank__pi8.h" + +// SYMS CLASS +class Vcache_simX__Syms : public VerilatedSyms { + public: + + // LOCAL STATE + const char* __Vm_namep; + bool __Vm_activity; ///< Used by trace routines to determine change occurred + bool __Vm_didInit; + + // SUBCELL STATE + Vcache_simX* TOPp; + Vcache_simX_VX_dcache_request_inter TOP__cache_simX__DOT__VX_dcache_req; + Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 TOP__cache_simX__DOT__VX_dram_req_rsp; + Vcache_simX_VX_dram_req_rsp_inter__N1_NB4 TOP__cache_simX__DOT__VX_dram_req_rsp_icache; + Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure; + Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure; + Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure; + Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure; + + // CREATORS + Vcache_simX__Syms(Vcache_simX* topp, const char* namep); + ~Vcache_simX__Syms() {} + + // METHODS + inline const char* name() { return __Vm_namep; } + inline bool getClearActivity() { bool r=__Vm_activity; __Vm_activity=false; return r; } + +} VL_ATTR_ALIGNED(64); + +#endif // guard diff --git a/simX/obj_dir/Vcache_simX__Trace.cpp b/simX/obj_dir/Vcache_simX__Trace.cpp new file mode 100644 index 00000000..21903a7c --- /dev/null +++ b/simX/obj_dir/Vcache_simX__Trace.cpp @@ -0,0 +1,5893 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Tracing implementation internals +#include "verilated_vcd_c.h" +#include "Vcache_simX__Syms.h" + + +//====================== + +void Vcache_simX::traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code) { + // Callback from vcd->dump() + Vcache_simX* t=(Vcache_simX*)userthis; + Vcache_simX__Syms* __restrict vlSymsp = t->__VlSymsp; // Setup global symbol table + if (vlSymsp->getClearActivity()) { + t->traceChgThis (vlSymsp, vcdp, code); + } +} + +//====================== + + +void Vcache_simX::traceChgThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c=code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + if (VL_UNLIKELY((1U & (vlTOPp->__Vm_traceActivity + | (vlTOPp->__Vm_traceActivity + >> 1U))))) { + vlTOPp->traceChgThis__2(vlSymsp, vcdp, code); + } + if (VL_UNLIKELY((1U & ((vlTOPp->__Vm_traceActivity + | (vlTOPp->__Vm_traceActivity + >> 1U)) | (vlTOPp->__Vm_traceActivity + >> 2U))))) { + vlTOPp->traceChgThis__3(vlSymsp, vcdp, code); + } + if (VL_UNLIKELY((1U & (vlTOPp->__Vm_traceActivity + | (vlTOPp->__Vm_traceActivity + >> 2U))))) { + vlTOPp->traceChgThis__4(vlSymsp, vcdp, code); + } + if (VL_UNLIKELY((4U & vlTOPp->__Vm_traceActivity))) { + vlTOPp->traceChgThis__5(vlSymsp, vcdp, code); + } + vlTOPp->traceChgThis__6(vlSymsp, vcdp, code); + } + // Final + vlTOPp->__Vm_traceActivity = 0U; +} + +void Vcache_simX::traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c=code; + if (0 && vcdp && c) {} // Prevent unused + // Variables + VL_SIGW(__Vtemp544,127,0,4); + VL_SIGW(__Vtemp545,127,0,4); + VL_SIGW(__Vtemp546,127,0,4); + VL_SIGW(__Vtemp547,127,0,4); + VL_SIGW(__Vtemp548,127,0,4); + VL_SIGW(__Vtemp549,127,0,4); + VL_SIGW(__Vtemp550,127,0,4); + VL_SIGW(__Vtemp555,127,0,4); + VL_SIGW(__Vtemp556,127,0,4); + VL_SIGW(__Vtemp557,127,0,4); + VL_SIGW(__Vtemp558,127,0,4); + VL_SIGW(__Vtemp559,127,0,4); + VL_SIGW(__Vtemp560,127,0,4); + VL_SIGW(__Vtemp561,127,0,4); + VL_SIGW(__Vtemp562,127,0,4); + VL_SIGW(__Vtemp563,127,0,4); + VL_SIGW(__Vtemp564,127,0,4); + VL_SIGW(__Vtemp565,127,0,4); + VL_SIGW(__Vtemp566,127,0,4); + VL_SIGW(__Vtemp567,127,0,4); + VL_SIGW(__Vtemp568,127,0,4); + VL_SIGW(__Vtemp569,127,0,4); + VL_SIGW(__Vtemp570,127,0,4); + VL_SIGW(__Vtemp571,127,0,4); + VL_SIGW(__Vtemp572,127,0,4); + VL_SIGW(__Vtemp573,127,0,4); + VL_SIGW(__Vtemp574,127,0,4); + VL_SIGW(__Vtemp575,127,0,4); + VL_SIGW(__Vtemp576,127,0,4); + VL_SIGW(__Vtemp577,127,0,4); + VL_SIGW(__Vtemp578,127,0,4); + VL_SIGW(__Vtemp579,127,0,4); + VL_SIGW(__Vtemp580,127,0,4); + VL_SIGW(__Vtemp581,127,0,4); + VL_SIGW(__Vtemp582,127,0,4); + VL_SIGW(__Vtemp583,127,0,4); + VL_SIGW(__Vtemp584,127,0,4); + VL_SIGW(__Vtemp585,127,0,4); + VL_SIGW(__Vtemp586,127,0,4); + VL_SIGW(__Vtemp587,127,0,4); + VL_SIGW(__Vtemp588,127,0,4); + VL_SIGW(__Vtemp589,127,0,4); + VL_SIGW(__Vtemp590,127,0,4); + VL_SIGW(__Vtemp591,127,0,4); + // Body + { + vcdp->chgBit (c+1,((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))))); + vcdp->chgBus (c+2,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid),4); + vcdp->chgBus (c+3,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid),4); + vcdp->chgBit (c+4,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write)); + vcdp->chgArray(c+5,(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address),128); + vcdp->chgBus (c+9,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read),3); + vcdp->chgBus (c+10,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write),3); + vcdp->chgBus (c+11,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read),3); + vcdp->chgBus (c+12,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write),3); + vcdp->chgArray(c+13,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual),128); + __Vtemp544[0U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[0U] + : 0U); + __Vtemp544[1U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[1U] + : 0U); + __Vtemp544[2U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[2U] + : 0U); + __Vtemp544[3U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[3U] + : 0U); + vcdp->chgArray(c+17,(__Vtemp544),128); + vcdp->chgBus (c+21,((0xfU & (((~ (IData)((0U + != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) + : 0U))),4); + vcdp->chgBit (c+22,((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))); + vcdp->chgBus (c+23,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read),3); + vcdp->chgArray(c+24,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address),128); + vcdp->chgArray(c+28,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data),128); + vcdp->chgBus (c+32,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid),4); + vcdp->chgBus (c+33,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid),4); + vcdp->chgArray(c+34,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data),128); + vcdp->chgBus (c+38,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr),28); + vcdp->chgArray(c+39,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata),512); + vcdp->chgArray(c+55,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata),512); + vcdp->chgBus (c+71,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we),8); + vcdp->chgBit (c+72,(((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))))); + vcdp->chgBus (c+73,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num),12); + vcdp->chgBus (c+74,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid),4); + vcdp->chgBit (c+75,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)); + vcdp->chgBit (c+76,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)); + vcdp->chgBit (c+77,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)); + vcdp->chgBit (c+78,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)); + vcdp->chgBus (c+79,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced),4); + vcdp->chgBus (c+80,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid),4); + vcdp->chgBus (c+81,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids),16); + vcdp->chgBus (c+82,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid),4); + vcdp->chgBus (c+83,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num),8); + vcdp->chgBus (c+84,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual),4); + vcdp->chgBus (c+85,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids),3); + vcdp->chgBus (c+86,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids),3); + vcdp->chgBus (c+87,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids),3); + vcdp->chgBus (c+88,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids),3); + vcdp->chgBus (c+89,((0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))),4); + vcdp->chgBus (c+90,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 4U))),4); + vcdp->chgBus (c+91,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 8U))),4); + vcdp->chgBus (c+92,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 0xcU))),4); + vcdp->chgBus (c+93,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index),2); + vcdp->chgBit (c+94,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found)); + vcdp->chgBus (c+95,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i),32); + vcdp->chgBus (c+96,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index),2); + vcdp->chgBit (c+97,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found)); + vcdp->chgBus (c+98,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i),32); + vcdp->chgBus (c+99,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index),2); + vcdp->chgBit (c+100,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found)); + vcdp->chgBus (c+101,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i),32); + vcdp->chgBus (c+102,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index),2); + vcdp->chgBit (c+103,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found)); + vcdp->chgBus (c+104,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i),32); + vcdp->chgBus (c+105,((0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)),7); + __Vtemp545[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0U]; + __Vtemp545[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[1U]; + __Vtemp545[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[2U]; + __Vtemp545[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[3U]; + vcdp->chgArray(c+106,(__Vtemp545),128); + vcdp->chgBus (c+110,((3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we))),2); + vcdp->chgBus (c+111,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))),7); + __Vtemp546[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[4U]; + __Vtemp546[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[5U]; + __Vtemp546[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[6U]; + __Vtemp546[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[7U]; + vcdp->chgArray(c+112,(__Vtemp546),128); + vcdp->chgBus (c+116,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 2U))),2); + vcdp->chgBus (c+117,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))),7); + __Vtemp547[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[8U]; + __Vtemp547[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[9U]; + __Vtemp547[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xaU]; + __Vtemp547[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xbU]; + vcdp->chgArray(c+118,(__Vtemp547),128); + vcdp->chgBus (c+122,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 4U))),2); + vcdp->chgBus (c+123,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))),7); + __Vtemp548[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xcU]; + __Vtemp548[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xdU]; + __Vtemp548[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xeU]; + __Vtemp548[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xfU]; + vcdp->chgArray(c+124,(__Vtemp548),128); + vcdp->chgBus (c+128,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 6U))),2); + vcdp->chgBus (c+129,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[0U])),32); + vcdp->chgArray(c+130,(vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata),512); + vcdp->chgArray(c+146,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read),128); + vcdp->chgBus (c+150,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks),16); + vcdp->chgBus (c+151,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank),8); + vcdp->chgBus (c+152,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank),16); + vcdp->chgBus (c+153,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank),4); + vcdp->chgBus (c+154,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank),16); + vcdp->chgArray(c+155,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank),128); + vcdp->chgBus (c+159,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank),4); + vcdp->chgBus (c+160,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb),4); + vcdp->chgBus (c+161,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state),4); + vcdp->chgBus (c+162,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid),4); + vcdp->chgBus (c+163,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid),4); + vcdp->chgArray(c+164,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank),128); + vcdp->chgBit (c+168,((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)))); + vcdp->chgBus (c+169,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual),4); + vcdp->chgBus (c+170,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[0]),4); + vcdp->chgBus (c+171,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[1]),4); + vcdp->chgBus (c+172,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[2]),4); + vcdp->chgBus (c+173,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[3]),4); + vcdp->chgBus (c+174,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss),4); + vcdp->chgBus (c+175,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index),2); + vcdp->chgBit (c+176,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found)); + vcdp->chgBus (c+177,((0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks))),4); + vcdp->chgBus (c+178,((3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))),2); + vcdp->chgBit (c+179,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)))); + vcdp->chgBus (c+180,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[0U]),32); + vcdp->chgBus (c+181,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 4U))),4); + vcdp->chgBus (c+182,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))),2); + vcdp->chgBit (c+183,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) + >> 1U)))); + vcdp->chgBus (c+184,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[1U]),32); + vcdp->chgBus (c+185,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 8U))),4); + vcdp->chgBus (c+186,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))),2); + vcdp->chgBit (c+187,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) + >> 2U)))); + vcdp->chgBus (c+188,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[2U]),32); + vcdp->chgBus (c+189,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 0xcU))),4); + vcdp->chgBus (c+190,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))),2); + vcdp->chgBit (c+191,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) + >> 3U)))); + vcdp->chgBus (c+192,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[3U]),32); + vcdp->chgBus (c+193,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr),32); + vcdp->chgBus (c+194,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)),2); + vcdp->chgBus (c+195,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU))),21); + vcdp->chgBit (c+196,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)))); + vcdp->chgBit (c+197,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + vcdp->chgBus (c+198,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr),32); + vcdp->chgBus (c+199,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)),2); + vcdp->chgBus (c+200,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU))),21); + vcdp->chgBit (c+201,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 1U)))); + vcdp->chgBit (c+202,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in)); + vcdp->chgBus (c+203,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr),32); + vcdp->chgBus (c+204,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)),2); + vcdp->chgBus (c+205,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU))),21); + vcdp->chgBit (c+206,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 2U)))); + vcdp->chgBit (c+207,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in)); + vcdp->chgBus (c+208,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr),32); + vcdp->chgBus (c+209,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)),2); + vcdp->chgBus (c+210,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU))),21); + vcdp->chgBit (c+211,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 3U)))); + vcdp->chgBit (c+212,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in)); + vcdp->chgBus (c+213,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i),32); + vcdp->chgBus (c+214,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found) + ? ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index)) + : 0U))),4); + vcdp->chgBus (c+215,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index),2); + vcdp->chgBit (c+216,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found)); + vcdp->chgBus (c+217,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i),32); + vcdp->chgBus (c+218,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found) + ? ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index)) + : 0U))),4); + vcdp->chgBus (c+219,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index),2); + vcdp->chgBit (c+220,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found)); + vcdp->chgBus (c+221,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i),32); + vcdp->chgBus (c+222,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found) + ? ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index)) + : 0U))),4); + vcdp->chgBus (c+223,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index),2); + vcdp->chgBit (c+224,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found)); + vcdp->chgBus (c+225,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i),32); + vcdp->chgBus (c+226,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found) + ? ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index)) + : 0U))),4); + vcdp->chgBus (c+227,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index),2); + vcdp->chgBit (c+228,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found)); + vcdp->chgBus (c+229,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i),32); + vcdp->chgBus (c+230,((0xfffffff0U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + << 9U))),32); + vcdp->chgBus (c+231,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read),32); + vcdp->chgBus (c+232,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks),1); + vcdp->chgBus (c+233,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index),1); + vcdp->chgBus (c+234,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) + ? ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index)) + : 0U))),1); + vcdp->chgBus (c+235,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank),1); + vcdp->chgBus (c+236,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank),1); + vcdp->chgBus (c+237,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffffff00U + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x8000U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffff0000U + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : ((4U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)))) + : 0U)),32); + vcdp->chgBus (c+238,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank),1); + vcdp->chgBus (c+239,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state),4); + vcdp->chgBus (c+240,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid),1); + vcdp->chgBus (c+241,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid),1); + vcdp->chgBus (c+242,((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + << 9U)),32); + vcdp->chgBus (c+243,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank),1); + vcdp->chgBus (c+244,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[0]),1); + vcdp->chgBus (c+245,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss),1); + vcdp->chgBus (c+246,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index),1); + vcdp->chgBit (c+247,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found)); + vcdp->chgBit (c+248,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank)); + vcdp->chgBus (c+249,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr),32); + vcdp->chgBus (c+250,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)),2); + vcdp->chgBus (c+251,((0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U))),23); + vcdp->chgBit (c+252,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)); + vcdp->chgBit (c+253,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + vcdp->chgBus (c+254,(0U),32); + vcdp->chgBus (c+255,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use),23); + vcdp->chgBit (c+256,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use)); + vcdp->chgBit (c+257,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access)); + vcdp->chgBit (c+258,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)); + vcdp->chgBit (c+259,((((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + != (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)))); + vcdp->chgBit (c+260,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->chgBit (c+261,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->chgBit (c+262,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->chgBit (c+263,((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->chgBit (c+264,((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->chgBit (c+265,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->chgBit (c+266,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->chgBit (c+267,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->chgBit (c+268,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->chgBus (c+269,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual),32); + vcdp->chgBus (c+270,(((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffffff00U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))),32); + vcdp->chgBus (c+271,(((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffff0000U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))),32); + vcdp->chgBus (c+272,((0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)),32); + vcdp->chgBus (c+273,((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)),32); + vcdp->chgBus (c+274,(0U),32); + vcdp->chgBus (c+275,(0U),32); + vcdp->chgBus (c+276,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffffff00U + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffff0000U + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))))),32); + vcdp->chgBus (c+277,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 2U : ((2U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 4U + : 8U)))),4); + vcdp->chgBus (c+278,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->chgBus (c+279,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we),16); + vcdp->chgArray(c+280,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write),128); + vcdp->chgBus (c+284,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way),2); + vcdp->chgBus (c+285,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way),32); + vcdp->chgArray(c+286,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way),256); + vcdp->chgBus (c+294,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->chgBus (c+295,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index),1); + vcdp->chgBus (c+296,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual),1); + vcdp->chgBit (c+297,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->chgBus (c+298,((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)),16); + vcdp->chgBit (c+299,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp549[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp549[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp549[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp549[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U]; + vcdp->chgArray(c+300,(__Vtemp549),128); + vcdp->chgBit (c+304,((0U != (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)))); + vcdp->chgBit (c+305,((1U & ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)))))); + vcdp->chgBus (c+306,((0xffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->chgBit (c+307,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp550[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp550[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp550[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp550[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U]; + vcdp->chgArray(c+308,(__Vtemp550),128); + vcdp->chgBit (c+312,((0U != (0xffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->chgBit (c+313,((1U & ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U))))))); + vcdp->chgBus (c+314,(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid),4); + __Vtemp555[0U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))) + ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[0U] + : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[0U]); + __Vtemp555[1U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))) + ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[1U] + : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[1U]); + __Vtemp555[2U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))) + ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[2U] + : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[2U]); + __Vtemp555[3U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))) + ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[3U] + : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[3U]); + vcdp->chgArray(c+315,(__Vtemp555),128); + __Vtemp556[0U] = 0U; + __Vtemp556[1U] = 0U; + __Vtemp556[2U] = 0U; + __Vtemp556[3U] = 0U; + vcdp->chgBus (c+319,(__Vtemp556[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]),32); + vcdp->chgBus (c+320,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U)),32); + vcdp->chgBit (c+321,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU)))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use)))); + vcdp->chgBus (c+322,((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU)),32); + vcdp->chgArray(c+323,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128); + vcdp->chgBus (c+327,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use),21); + vcdp->chgBit (c+328,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use)); + vcdp->chgBit (c+329,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access)); + vcdp->chgBit (c+330,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__write_from_mem)); + vcdp->chgBit (c+331,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use + != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)))); + vcdp->chgBit (c+332,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->chgBit (c+333,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->chgBit (c+334,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->chgBit (c+335,((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->chgBit (c+336,((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->chgBit (c+337,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))); + vcdp->chgBit (c+338,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))); + vcdp->chgBit (c+339,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))); + vcdp->chgBit (c+340,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->chgBit (c+341,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->chgBit (c+342,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->chgBit (c+343,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->chgBus (c+344,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual),32); + vcdp->chgBus (c+345,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->chgBus (c+346,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->chgBus (c+347,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32); + vcdp->chgBus (c+348,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32); + __Vtemp557[0U] = 0U; + __Vtemp557[1U] = 0U; + __Vtemp557[2U] = 0U; + __Vtemp557[3U] = 0U; + __Vtemp558[0U] = 0U; + __Vtemp558[1U] = 0U; + __Vtemp558[2U] = 0U; + __Vtemp558[3U] = 0U; + __Vtemp559[0U] = 0U; + __Vtemp559[1U] = 0U; + __Vtemp559[2U] = 0U; + __Vtemp559[3U] = 0U; + __Vtemp560[0U] = 0U; + __Vtemp560[1U] = 0U; + __Vtemp560[2U] = 0U; + __Vtemp560[3U] = 0U; + vcdp->chgBus (c+349,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff00U & (__Vtemp557[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 8U)) + : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff0000U & + (__Vtemp558[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x10U)) : + ((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp559[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x18U)) + : __Vtemp560[(3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])))),32); + __Vtemp561[0U] = 0U; + __Vtemp561[1U] = 0U; + __Vtemp561[2U] = 0U; + __Vtemp561[3U] = 0U; + __Vtemp562[0U] = 0U; + __Vtemp562[1U] = 0U; + __Vtemp562[2U] = 0U; + __Vtemp562[3U] = 0U; + vcdp->chgBus (c+350,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xffff0000U & (__Vtemp561[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x10U)) + : __Vtemp562[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])),32); + vcdp->chgBus (c+351,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__use_write_data),32); + vcdp->chgBus (c+352,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))))),32); + vcdp->chgBus (c+353,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__sb_mask),4); + vcdp->chgBus (c+354,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->chgBus (c+355,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__we),16); + vcdp->chgArray(c+356,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_write),128); + vcdp->chgBit (c+360,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write)); + vcdp->chgBus (c+361,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2); + vcdp->chgBus (c+362,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32); + vcdp->chgArray(c+363,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256); + vcdp->chgBus (c+371,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->chgBus (c+372,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1); + vcdp->chgBus (c+373,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1); + vcdp->chgBit (c+374,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->chgBus (c+375,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16); + vcdp->chgBit (c+376,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp563[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp563[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp563[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp563[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U]; + vcdp->chgArray(c+377,(__Vtemp563),128); + vcdp->chgBit (c+381,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))); + vcdp->chgBit (c+382,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))))); + vcdp->chgBus (c+383,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->chgBit (c+384,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp564[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp564[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp564[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp564[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U]; + vcdp->chgArray(c+385,(__Vtemp564),128); + vcdp->chgBit (c+389,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->chgBit (c+390,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))))); + __Vtemp565[0U] = 0U; + __Vtemp565[1U] = 0U; + __Vtemp565[2U] = 0U; + __Vtemp565[3U] = 0U; + vcdp->chgBus (c+391,(__Vtemp565[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))]),32); + vcdp->chgBus (c+392,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U)),32); + vcdp->chgBit (c+393,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU)))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use)))); + vcdp->chgBus (c+394,((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU)),32); + vcdp->chgArray(c+395,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128); + vcdp->chgBus (c+399,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use),21); + vcdp->chgBit (c+400,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use)); + vcdp->chgBit (c+401,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access)); + vcdp->chgBit (c+402,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__write_from_mem)); + vcdp->chgBit (c+403,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use + != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in)))); + vcdp->chgBit (c+404,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)))); + vcdp->chgBit (c+405,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)))); + vcdp->chgBit (c+406,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)))); + vcdp->chgBit (c+407,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)))); + vcdp->chgBus (c+408,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual),32); + vcdp->chgBus (c+409,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->chgBus (c+410,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->chgBus (c+411,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32); + vcdp->chgBus (c+412,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32); + __Vtemp566[0U] = 0U; + __Vtemp566[1U] = 0U; + __Vtemp566[2U] = 0U; + __Vtemp566[3U] = 0U; + __Vtemp567[0U] = 0U; + __Vtemp567[1U] = 0U; + __Vtemp567[2U] = 0U; + __Vtemp567[3U] = 0U; + __Vtemp568[0U] = 0U; + __Vtemp568[1U] = 0U; + __Vtemp568[2U] = 0U; + __Vtemp568[3U] = 0U; + __Vtemp569[0U] = 0U; + __Vtemp569[1U] = 0U; + __Vtemp569[2U] = 0U; + __Vtemp569[3U] = 0U; + vcdp->chgBus (c+413,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff00U & (__Vtemp566[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 8U)) + : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff0000U & + (__Vtemp567[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x10U)) : + ((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp568[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x18U)) + : __Vtemp569[(3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))])))),32); + __Vtemp570[0U] = 0U; + __Vtemp570[1U] = 0U; + __Vtemp570[2U] = 0U; + __Vtemp570[3U] = 0U; + __Vtemp571[0U] = 0U; + __Vtemp571[1U] = 0U; + __Vtemp571[2U] = 0U; + __Vtemp571[3U] = 0U; + vcdp->chgBus (c+414,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xffff0000U & (__Vtemp570[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x10U)) + : __Vtemp571[(3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))])),32); + vcdp->chgBus (c+415,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__use_write_data),32); + vcdp->chgBus (c+416,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))))),32); + vcdp->chgBus (c+417,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__sb_mask),4); + vcdp->chgBus (c+418,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->chgBus (c+419,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__we),16); + vcdp->chgArray(c+420,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_write),128); + vcdp->chgBit (c+424,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write)); + vcdp->chgBus (c+425,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2); + vcdp->chgBus (c+426,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32); + vcdp->chgArray(c+427,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256); + vcdp->chgBus (c+435,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->chgBus (c+436,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1); + vcdp->chgBus (c+437,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1); + vcdp->chgBit (c+438,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->chgBus (c+439,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16); + vcdp->chgBit (c+440,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp572[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp572[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp572[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp572[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U]; + vcdp->chgArray(c+441,(__Vtemp572),128); + vcdp->chgBit (c+445,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))); + vcdp->chgBit (c+446,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))))); + vcdp->chgBus (c+447,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->chgBit (c+448,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp573[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp573[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp573[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp573[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U]; + vcdp->chgArray(c+449,(__Vtemp573),128); + vcdp->chgBit (c+453,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->chgBit (c+454,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))))); + __Vtemp574[0U] = 0U; + __Vtemp574[1U] = 0U; + __Vtemp574[2U] = 0U; + __Vtemp574[3U] = 0U; + vcdp->chgBus (c+455,(__Vtemp574[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))]),32); + vcdp->chgBus (c+456,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U)),32); + vcdp->chgBit (c+457,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU)))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use)))); + vcdp->chgBus (c+458,((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU)),32); + vcdp->chgArray(c+459,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128); + vcdp->chgBus (c+463,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use),21); + vcdp->chgBit (c+464,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use)); + vcdp->chgBit (c+465,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access)); + vcdp->chgBit (c+466,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__write_from_mem)); + vcdp->chgBit (c+467,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use + != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in)))); + vcdp->chgBit (c+468,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)))); + vcdp->chgBit (c+469,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)))); + vcdp->chgBit (c+470,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)))); + vcdp->chgBit (c+471,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)))); + vcdp->chgBus (c+472,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual),32); + vcdp->chgBus (c+473,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->chgBus (c+474,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->chgBus (c+475,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32); + vcdp->chgBus (c+476,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32); + __Vtemp575[0U] = 0U; + __Vtemp575[1U] = 0U; + __Vtemp575[2U] = 0U; + __Vtemp575[3U] = 0U; + __Vtemp576[0U] = 0U; + __Vtemp576[1U] = 0U; + __Vtemp576[2U] = 0U; + __Vtemp576[3U] = 0U; + __Vtemp577[0U] = 0U; + __Vtemp577[1U] = 0U; + __Vtemp577[2U] = 0U; + __Vtemp577[3U] = 0U; + __Vtemp578[0U] = 0U; + __Vtemp578[1U] = 0U; + __Vtemp578[2U] = 0U; + __Vtemp578[3U] = 0U; + vcdp->chgBus (c+477,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff00U & (__Vtemp575[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 8U)) + : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff0000U & + (__Vtemp576[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x10U)) : + ((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp577[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x18U)) + : __Vtemp578[(3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))])))),32); + __Vtemp579[0U] = 0U; + __Vtemp579[1U] = 0U; + __Vtemp579[2U] = 0U; + __Vtemp579[3U] = 0U; + __Vtemp580[0U] = 0U; + __Vtemp580[1U] = 0U; + __Vtemp580[2U] = 0U; + __Vtemp580[3U] = 0U; + vcdp->chgBus (c+478,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xffff0000U & (__Vtemp579[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x10U)) + : __Vtemp580[(3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))])),32); + vcdp->chgBus (c+479,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__use_write_data),32); + vcdp->chgBus (c+480,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))))),32); + vcdp->chgBus (c+481,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__sb_mask),4); + vcdp->chgBus (c+482,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->chgBus (c+483,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__we),16); + vcdp->chgArray(c+484,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_write),128); + vcdp->chgBit (c+488,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write)); + vcdp->chgBus (c+489,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2); + vcdp->chgBus (c+490,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32); + vcdp->chgArray(c+491,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256); + vcdp->chgBus (c+499,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->chgBus (c+500,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1); + vcdp->chgBus (c+501,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1); + vcdp->chgBit (c+502,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->chgBus (c+503,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16); + vcdp->chgBit (c+504,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp581[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp581[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp581[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp581[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U]; + vcdp->chgArray(c+505,(__Vtemp581),128); + vcdp->chgBit (c+509,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))); + vcdp->chgBit (c+510,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))))); + vcdp->chgBus (c+511,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->chgBit (c+512,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp582[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp582[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp582[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp582[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U]; + vcdp->chgArray(c+513,(__Vtemp582),128); + vcdp->chgBit (c+517,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->chgBit (c+518,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))))); + __Vtemp583[0U] = 0U; + __Vtemp583[1U] = 0U; + __Vtemp583[2U] = 0U; + __Vtemp583[3U] = 0U; + vcdp->chgBus (c+519,(__Vtemp583[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))]),32); + vcdp->chgBus (c+520,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U)),32); + vcdp->chgBit (c+521,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU)))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use)))); + vcdp->chgBus (c+522,((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU)),32); + vcdp->chgArray(c+523,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128); + vcdp->chgBus (c+527,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use),21); + vcdp->chgBit (c+528,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use)); + vcdp->chgBit (c+529,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access)); + vcdp->chgBit (c+530,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__write_from_mem)); + vcdp->chgBit (c+531,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use + != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in)))); + vcdp->chgBit (c+532,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)))); + vcdp->chgBit (c+533,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)))); + vcdp->chgBit (c+534,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)))); + vcdp->chgBit (c+535,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)))); + vcdp->chgBus (c+536,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual),32); + vcdp->chgBus (c+537,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->chgBus (c+538,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->chgBus (c+539,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32); + vcdp->chgBus (c+540,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32); + __Vtemp584[0U] = 0U; + __Vtemp584[1U] = 0U; + __Vtemp584[2U] = 0U; + __Vtemp584[3U] = 0U; + __Vtemp585[0U] = 0U; + __Vtemp585[1U] = 0U; + __Vtemp585[2U] = 0U; + __Vtemp585[3U] = 0U; + __Vtemp586[0U] = 0U; + __Vtemp586[1U] = 0U; + __Vtemp586[2U] = 0U; + __Vtemp586[3U] = 0U; + __Vtemp587[0U] = 0U; + __Vtemp587[1U] = 0U; + __Vtemp587[2U] = 0U; + __Vtemp587[3U] = 0U; + vcdp->chgBus (c+541,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff00U & (__Vtemp584[ + (3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 8U)) + : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff0000U & + (__Vtemp585[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x10U)) : + ((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp586[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x18U)) + : __Vtemp587[(3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))])))),32); + __Vtemp588[0U] = 0U; + __Vtemp588[1U] = 0U; + __Vtemp588[2U] = 0U; + __Vtemp588[3U] = 0U; + __Vtemp589[0U] = 0U; + __Vtemp589[1U] = 0U; + __Vtemp589[2U] = 0U; + __Vtemp589[3U] = 0U; + vcdp->chgBus (c+542,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xffff0000U & (__Vtemp588[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x10U)) + : __Vtemp589[(3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))])),32); + vcdp->chgBus (c+543,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__use_write_data),32); + vcdp->chgBus (c+544,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))))),32); + vcdp->chgBus (c+545,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__sb_mask),4); + vcdp->chgBus (c+546,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->chgBus (c+547,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__we),16); + vcdp->chgArray(c+548,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_write),128); + vcdp->chgBit (c+552,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write)); + vcdp->chgBus (c+553,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2); + vcdp->chgBus (c+554,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32); + vcdp->chgArray(c+555,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256); + vcdp->chgBus (c+563,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->chgBus (c+564,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1); + vcdp->chgBus (c+565,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1); + vcdp->chgBit (c+566,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->chgBus (c+567,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16); + vcdp->chgBit (c+568,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp590[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp590[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp590[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp590[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U]; + vcdp->chgArray(c+569,(__Vtemp590),128); + vcdp->chgBit (c+573,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))); + vcdp->chgBit (c+574,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))))); + vcdp->chgBus (c+575,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->chgBit (c+576,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp591[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp591[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp591[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp591[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U]; + vcdp->chgArray(c+577,(__Vtemp591),128); + vcdp->chgBit (c+581,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->chgBit (c+582,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))))); + } +} + +void Vcache_simX::traceChgThis__3(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c=code; + if (0 && vcdp && c) {} // Prevent unused + // Variables + VL_SIGW(__Vtemp594,127,0,4); + VL_SIGW(__Vtemp597,127,0,4); + VL_SIGW(__Vtemp600,127,0,4); + VL_SIGW(__Vtemp603,127,0,4); + VL_SIGW(__Vtemp604,127,0,4); + // Body + { + vcdp->chgBit (c+583,(((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))))); + vcdp->chgBus (c+584,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read)),32); + vcdp->chgBit (c+585,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))))); + vcdp->chgBit (c+586,((1U & ((~ ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid))))); + vcdp->chgBus (c+587,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests)) + ? ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))) + : ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))))),4); + __Vtemp594[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][0U]); + __Vtemp594[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][1U]); + __Vtemp594[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][2U]); + __Vtemp594[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][3U]); + vcdp->chgArray(c+588,(__Vtemp594),128); + __Vtemp597[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][0U]); + __Vtemp597[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][1U]); + __Vtemp597[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][2U]); + __Vtemp597[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][3U]); + vcdp->chgArray(c+592,(__Vtemp597),128); + __Vtemp600[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][0U]); + __Vtemp600[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][1U]); + __Vtemp600[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][2U]); + __Vtemp600[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][3U]); + vcdp->chgArray(c+596,(__Vtemp600),128); + __Vtemp603[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][0U]); + __Vtemp603[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][1U]); + __Vtemp603[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][2U]); + __Vtemp603[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][3U]); + vcdp->chgArray(c+600,(__Vtemp603),128); + vcdp->chgBit (c+604,(((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb))))); + vcdp->chgBit (c+605,(((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state))))); + __Vtemp604[0U] = (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))); + __Vtemp604[1U] = (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))); + __Vtemp604[2U] = (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))); + __Vtemp604[3U] = (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))); + vcdp->chgArray(c+606,(__Vtemp604),128); + vcdp->chgBit (c+610,(((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))))); + vcdp->chgBus (c+611,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))),1); + vcdp->chgBit (c+612,(((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state))))); + vcdp->chgBit (c+613,((1U & (((~ vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U + != + (0xffffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way))) + | (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way))))); + vcdp->chgBit (c+614,((1U & (((~ vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U + != + (0xffffU + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) + >> 1U))))); + vcdp->chgBit (c+615,(((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)) + | ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))))); + vcdp->chgBit (c+616,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual))))); + vcdp->chgBit (c+617,((1U & (((~ vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U + != + (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) + | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))))); + vcdp->chgBit (c+618,((1U & (((~ vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U + != + (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))))); + vcdp->chgBit (c+619,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual))))); + vcdp->chgBit (c+620,((1U & (((~ vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U + != + (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) + | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))))); + vcdp->chgBit (c+621,((1U & (((~ vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U + != + (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))))); + vcdp->chgBit (c+622,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual))))); + vcdp->chgBit (c+623,((1U & (((~ vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U + != + (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) + | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))))); + vcdp->chgBit (c+624,((1U & (((~ vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U + != + (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))))); + vcdp->chgBit (c+625,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual))))); + vcdp->chgBit (c+626,((1U & (((~ vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U + != + (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way))) + | (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way))))); + vcdp->chgBit (c+627,((1U & (((~ vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty + [0U]) & (0U + != + (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U)))) + | ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U))))); + } +} + +void Vcache_simX::traceChgThis__4(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c=code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + vcdp->chgBus (c+628,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update),1); + vcdp->chgQuad (c+629,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way),46); + vcdp->chgArray(c+631,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way),256); + vcdp->chgBus (c+639,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way),2); + vcdp->chgBus (c+640,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way),2); + vcdp->chgBit (c+641,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found)); + vcdp->chgBus (c+642,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index),1); + vcdp->chgBus (c+643,((3U & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way)))),2); + vcdp->chgBus (c+644,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__way_to_update),1); + vcdp->chgQuad (c+645,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42); + vcdp->chgArray(c+647,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256); + vcdp->chgBus (c+655,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2); + vcdp->chgBus (c+656,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2); + vcdp->chgBit (c+657,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found)); + vcdp->chgBus (c+658,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1); + vcdp->chgBus (c+659,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2); + vcdp->chgBus (c+660,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__way_to_update),1); + vcdp->chgQuad (c+661,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42); + vcdp->chgArray(c+663,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256); + vcdp->chgBus (c+671,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2); + vcdp->chgBus (c+672,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2); + vcdp->chgBit (c+673,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found)); + vcdp->chgBus (c+674,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1); + vcdp->chgBus (c+675,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2); + vcdp->chgBus (c+676,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__way_to_update),1); + vcdp->chgQuad (c+677,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42); + vcdp->chgArray(c+679,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256); + vcdp->chgBus (c+687,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2); + vcdp->chgBus (c+688,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2); + vcdp->chgBit (c+689,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found)); + vcdp->chgBus (c+690,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1); + vcdp->chgBus (c+691,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2); + vcdp->chgBus (c+692,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__way_to_update),1); + vcdp->chgQuad (c+693,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__tag_use_per_way),42); + vcdp->chgArray(c+695,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_use_per_way),256); + vcdp->chgBus (c+703,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way),2); + vcdp->chgBus (c+704,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__dirty_use_per_way),2); + vcdp->chgBit (c+705,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_found)); + vcdp->chgBus (c+706,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__invalid_index),1); + vcdp->chgBus (c+707,((3U & (~ (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__valid_use_per_way)))),2); + } +} + +void Vcache_simX::traceChgThis__5(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c=code; + if (0 && vcdp && c) {} // Prevent unused + // Variables + VL_SIGW(__Vtemp605,127,0,4); + VL_SIGW(__Vtemp606,127,0,4); + VL_SIGW(__Vtemp607,127,0,4); + VL_SIGW(__Vtemp608,127,0,4); + VL_SIGW(__Vtemp609,127,0,4); + VL_SIGW(__Vtemp610,127,0,4); + VL_SIGW(__Vtemp611,127,0,4); + VL_SIGW(__Vtemp612,127,0,4); + VL_SIGW(__Vtemp613,127,0,4); + VL_SIGW(__Vtemp614,127,0,4); + VL_SIGW(__Vtemp615,127,0,4); + VL_SIGW(__Vtemp616,127,0,4); + VL_SIGW(__Vtemp617,127,0,4); + VL_SIGW(__Vtemp618,127,0,4); + VL_SIGW(__Vtemp619,127,0,4); + VL_SIGW(__Vtemp620,127,0,4); + VL_SIGW(__Vtemp621,127,0,4); + VL_SIGW(__Vtemp622,127,0,4); + VL_SIGW(__Vtemp623,127,0,4); + VL_SIGW(__Vtemp624,127,0,4); + VL_SIGW(__Vtemp625,127,0,4); + VL_SIGW(__Vtemp626,127,0,4); + VL_SIGW(__Vtemp627,127,0,4); + VL_SIGW(__Vtemp628,127,0,4); + VL_SIGW(__Vtemp629,127,0,4); + VL_SIGW(__Vtemp630,127,0,4); + VL_SIGW(__Vtemp631,127,0,4); + VL_SIGW(__Vtemp632,127,0,4); + VL_SIGW(__Vtemp633,127,0,4); + VL_SIGW(__Vtemp634,127,0,4); + VL_SIGW(__Vtemp635,127,0,4); + VL_SIGW(__Vtemp636,127,0,4); + VL_SIGW(__Vtemp637,127,0,4); + VL_SIGW(__Vtemp638,127,0,4); + VL_SIGW(__Vtemp639,127,0,4); + VL_SIGW(__Vtemp640,127,0,4); + VL_SIGW(__Vtemp641,127,0,4); + VL_SIGW(__Vtemp642,127,0,4); + VL_SIGW(__Vtemp643,127,0,4); + VL_SIGW(__Vtemp644,127,0,4); + VL_SIGW(__Vtemp645,127,0,4); + VL_SIGW(__Vtemp646,127,0,4); + VL_SIGW(__Vtemp647,127,0,4); + VL_SIGW(__Vtemp648,127,0,4); + VL_SIGW(__Vtemp649,127,0,4); + VL_SIGW(__Vtemp650,127,0,4); + VL_SIGW(__Vtemp651,127,0,4); + VL_SIGW(__Vtemp652,127,0,4); + VL_SIGW(__Vtemp653,127,0,4); + VL_SIGW(__Vtemp654,127,0,4); + VL_SIGW(__Vtemp655,127,0,4); + VL_SIGW(__Vtemp656,127,0,4); + VL_SIGW(__Vtemp657,127,0,4); + VL_SIGW(__Vtemp658,127,0,4); + VL_SIGW(__Vtemp659,127,0,4); + VL_SIGW(__Vtemp660,127,0,4); + VL_SIGW(__Vtemp661,127,0,4); + VL_SIGW(__Vtemp662,127,0,4); + VL_SIGW(__Vtemp663,127,0,4); + VL_SIGW(__Vtemp664,127,0,4); + VL_SIGW(__Vtemp665,127,0,4); + VL_SIGW(__Vtemp666,127,0,4); + VL_SIGW(__Vtemp667,127,0,4); + VL_SIGW(__Vtemp668,127,0,4); + VL_SIGW(__Vtemp669,127,0,4); + VL_SIGW(__Vtemp670,127,0,4); + VL_SIGW(__Vtemp671,127,0,4); + VL_SIGW(__Vtemp672,127,0,4); + VL_SIGW(__Vtemp673,127,0,4); + VL_SIGW(__Vtemp674,127,0,4); + VL_SIGW(__Vtemp675,127,0,4); + VL_SIGW(__Vtemp676,127,0,4); + VL_SIGW(__Vtemp677,127,0,4); + VL_SIGW(__Vtemp678,127,0,4); + VL_SIGW(__Vtemp679,127,0,4); + VL_SIGW(__Vtemp680,127,0,4); + VL_SIGW(__Vtemp681,127,0,4); + VL_SIGW(__Vtemp682,127,0,4); + VL_SIGW(__Vtemp683,127,0,4); + VL_SIGW(__Vtemp684,127,0,4); + VL_SIGW(__Vtemp685,127,0,4); + VL_SIGW(__Vtemp686,127,0,4); + VL_SIGW(__Vtemp687,127,0,4); + VL_SIGW(__Vtemp688,127,0,4); + VL_SIGW(__Vtemp689,127,0,4); + VL_SIGW(__Vtemp690,127,0,4); + VL_SIGW(__Vtemp691,127,0,4); + VL_SIGW(__Vtemp692,127,0,4); + VL_SIGW(__Vtemp693,127,0,4); + VL_SIGW(__Vtemp694,127,0,4); + VL_SIGW(__Vtemp695,127,0,4); + VL_SIGW(__Vtemp696,127,0,4); + VL_SIGW(__Vtemp697,127,0,4); + VL_SIGW(__Vtemp698,127,0,4); + VL_SIGW(__Vtemp699,127,0,4); + VL_SIGW(__Vtemp700,127,0,4); + VL_SIGW(__Vtemp701,127,0,4); + VL_SIGW(__Vtemp702,127,0,4); + VL_SIGW(__Vtemp703,127,0,4); + VL_SIGW(__Vtemp704,127,0,4); + VL_SIGW(__Vtemp705,127,0,4); + VL_SIGW(__Vtemp706,127,0,4); + VL_SIGW(__Vtemp707,127,0,4); + VL_SIGW(__Vtemp708,127,0,4); + VL_SIGW(__Vtemp709,127,0,4); + VL_SIGW(__Vtemp710,127,0,4); + VL_SIGW(__Vtemp711,127,0,4); + VL_SIGW(__Vtemp712,127,0,4); + VL_SIGW(__Vtemp713,127,0,4); + VL_SIGW(__Vtemp714,127,0,4); + VL_SIGW(__Vtemp715,127,0,4); + VL_SIGW(__Vtemp716,127,0,4); + VL_SIGW(__Vtemp717,127,0,4); + VL_SIGW(__Vtemp718,127,0,4); + VL_SIGW(__Vtemp719,127,0,4); + VL_SIGW(__Vtemp720,127,0,4); + VL_SIGW(__Vtemp721,127,0,4); + VL_SIGW(__Vtemp722,127,0,4); + VL_SIGW(__Vtemp723,127,0,4); + VL_SIGW(__Vtemp724,127,0,4); + VL_SIGW(__Vtemp725,127,0,4); + VL_SIGW(__Vtemp726,127,0,4); + VL_SIGW(__Vtemp727,127,0,4); + VL_SIGW(__Vtemp728,127,0,4); + VL_SIGW(__Vtemp729,127,0,4); + VL_SIGW(__Vtemp730,127,0,4); + VL_SIGW(__Vtemp731,127,0,4); + VL_SIGW(__Vtemp732,127,0,4); + VL_SIGW(__Vtemp733,127,0,4); + VL_SIGW(__Vtemp734,127,0,4); + VL_SIGW(__Vtemp735,127,0,4); + VL_SIGW(__Vtemp736,127,0,4); + VL_SIGW(__Vtemp737,127,0,4); + VL_SIGW(__Vtemp738,127,0,4); + VL_SIGW(__Vtemp739,127,0,4); + VL_SIGW(__Vtemp740,127,0,4); + VL_SIGW(__Vtemp741,127,0,4); + VL_SIGW(__Vtemp742,127,0,4); + VL_SIGW(__Vtemp743,127,0,4); + VL_SIGW(__Vtemp744,127,0,4); + VL_SIGW(__Vtemp745,127,0,4); + VL_SIGW(__Vtemp746,127,0,4); + VL_SIGW(__Vtemp747,127,0,4); + VL_SIGW(__Vtemp748,127,0,4); + VL_SIGW(__Vtemp749,127,0,4); + VL_SIGW(__Vtemp750,127,0,4); + VL_SIGW(__Vtemp751,127,0,4); + VL_SIGW(__Vtemp752,127,0,4); + VL_SIGW(__Vtemp753,127,0,4); + VL_SIGW(__Vtemp754,127,0,4); + VL_SIGW(__Vtemp755,127,0,4); + VL_SIGW(__Vtemp756,127,0,4); + VL_SIGW(__Vtemp757,127,0,4); + VL_SIGW(__Vtemp758,127,0,4); + VL_SIGW(__Vtemp759,127,0,4); + VL_SIGW(__Vtemp760,127,0,4); + VL_SIGW(__Vtemp761,127,0,4); + VL_SIGW(__Vtemp762,127,0,4); + VL_SIGW(__Vtemp763,127,0,4); + VL_SIGW(__Vtemp764,127,0,4); + VL_SIGW(__Vtemp765,127,0,4); + VL_SIGW(__Vtemp766,127,0,4); + VL_SIGW(__Vtemp767,127,0,4); + VL_SIGW(__Vtemp768,127,0,4); + VL_SIGW(__Vtemp769,127,0,4); + VL_SIGW(__Vtemp770,127,0,4); + VL_SIGW(__Vtemp771,127,0,4); + VL_SIGW(__Vtemp772,127,0,4); + VL_SIGW(__Vtemp773,127,0,4); + VL_SIGW(__Vtemp774,127,0,4); + VL_SIGW(__Vtemp775,127,0,4); + VL_SIGW(__Vtemp776,127,0,4); + VL_SIGW(__Vtemp777,127,0,4); + VL_SIGW(__Vtemp778,127,0,4); + VL_SIGW(__Vtemp779,127,0,4); + VL_SIGW(__Vtemp780,127,0,4); + VL_SIGW(__Vtemp781,127,0,4); + VL_SIGW(__Vtemp782,127,0,4); + VL_SIGW(__Vtemp783,127,0,4); + VL_SIGW(__Vtemp784,127,0,4); + VL_SIGW(__Vtemp785,127,0,4); + VL_SIGW(__Vtemp786,127,0,4); + VL_SIGW(__Vtemp787,127,0,4); + VL_SIGW(__Vtemp788,127,0,4); + VL_SIGW(__Vtemp789,127,0,4); + VL_SIGW(__Vtemp790,127,0,4); + VL_SIGW(__Vtemp791,127,0,4); + VL_SIGW(__Vtemp792,127,0,4); + VL_SIGW(__Vtemp793,127,0,4); + VL_SIGW(__Vtemp794,127,0,4); + VL_SIGW(__Vtemp795,127,0,4); + VL_SIGW(__Vtemp796,127,0,4); + VL_SIGW(__Vtemp797,127,0,4); + VL_SIGW(__Vtemp798,127,0,4); + VL_SIGW(__Vtemp799,127,0,4); + VL_SIGW(__Vtemp800,127,0,4); + VL_SIGW(__Vtemp801,127,0,4); + VL_SIGW(__Vtemp802,127,0,4); + VL_SIGW(__Vtemp803,127,0,4); + VL_SIGW(__Vtemp804,127,0,4); + VL_SIGW(__Vtemp805,127,0,4); + VL_SIGW(__Vtemp806,127,0,4); + VL_SIGW(__Vtemp807,127,0,4); + VL_SIGW(__Vtemp808,127,0,4); + VL_SIGW(__Vtemp809,127,0,4); + VL_SIGW(__Vtemp810,127,0,4); + VL_SIGW(__Vtemp811,127,0,4); + VL_SIGW(__Vtemp812,127,0,4); + VL_SIGW(__Vtemp813,127,0,4); + VL_SIGW(__Vtemp814,127,0,4); + VL_SIGW(__Vtemp815,127,0,4); + VL_SIGW(__Vtemp816,127,0,4); + VL_SIGW(__Vtemp817,127,0,4); + VL_SIGW(__Vtemp818,127,0,4); + VL_SIGW(__Vtemp819,127,0,4); + VL_SIGW(__Vtemp820,127,0,4); + VL_SIGW(__Vtemp821,127,0,4); + VL_SIGW(__Vtemp822,127,0,4); + VL_SIGW(__Vtemp823,127,0,4); + VL_SIGW(__Vtemp824,127,0,4); + VL_SIGW(__Vtemp825,127,0,4); + VL_SIGW(__Vtemp826,127,0,4); + VL_SIGW(__Vtemp827,127,0,4); + VL_SIGW(__Vtemp828,127,0,4); + VL_SIGW(__Vtemp829,127,0,4); + VL_SIGW(__Vtemp830,127,0,4); + VL_SIGW(__Vtemp831,127,0,4); + VL_SIGW(__Vtemp832,127,0,4); + VL_SIGW(__Vtemp833,127,0,4); + VL_SIGW(__Vtemp834,127,0,4); + VL_SIGW(__Vtemp835,127,0,4); + VL_SIGW(__Vtemp836,127,0,4); + VL_SIGW(__Vtemp837,127,0,4); + VL_SIGW(__Vtemp838,127,0,4); + VL_SIGW(__Vtemp839,127,0,4); + VL_SIGW(__Vtemp840,127,0,4); + VL_SIGW(__Vtemp841,127,0,4); + VL_SIGW(__Vtemp842,127,0,4); + VL_SIGW(__Vtemp843,127,0,4); + VL_SIGW(__Vtemp844,127,0,4); + VL_SIGW(__Vtemp845,127,0,4); + VL_SIGW(__Vtemp846,127,0,4); + VL_SIGW(__Vtemp847,127,0,4); + VL_SIGW(__Vtemp848,127,0,4); + VL_SIGW(__Vtemp849,127,0,4); + VL_SIGW(__Vtemp850,127,0,4); + VL_SIGW(__Vtemp851,127,0,4); + VL_SIGW(__Vtemp852,127,0,4); + VL_SIGW(__Vtemp853,127,0,4); + VL_SIGW(__Vtemp854,127,0,4); + VL_SIGW(__Vtemp855,127,0,4); + VL_SIGW(__Vtemp856,127,0,4); + VL_SIGW(__Vtemp857,127,0,4); + VL_SIGW(__Vtemp858,127,0,4); + VL_SIGW(__Vtemp859,127,0,4); + VL_SIGW(__Vtemp860,127,0,4); + VL_SIGW(__Vtemp861,127,0,4); + VL_SIGW(__Vtemp862,127,0,4); + VL_SIGW(__Vtemp863,127,0,4); + VL_SIGW(__Vtemp864,127,0,4); + VL_SIGW(__Vtemp865,127,0,4); + VL_SIGW(__Vtemp866,127,0,4); + VL_SIGW(__Vtemp867,127,0,4); + VL_SIGW(__Vtemp868,127,0,4); + VL_SIGW(__Vtemp869,127,0,4); + VL_SIGW(__Vtemp870,127,0,4); + VL_SIGW(__Vtemp871,127,0,4); + VL_SIGW(__Vtemp872,127,0,4); + VL_SIGW(__Vtemp873,127,0,4); + VL_SIGW(__Vtemp874,127,0,4); + VL_SIGW(__Vtemp875,127,0,4); + VL_SIGW(__Vtemp876,127,0,4); + VL_SIGW(__Vtemp877,127,0,4); + VL_SIGW(__Vtemp878,127,0,4); + VL_SIGW(__Vtemp879,127,0,4); + VL_SIGW(__Vtemp880,127,0,4); + VL_SIGW(__Vtemp881,127,0,4); + VL_SIGW(__Vtemp882,127,0,4); + VL_SIGW(__Vtemp883,127,0,4); + VL_SIGW(__Vtemp884,127,0,4); + VL_SIGW(__Vtemp885,127,0,4); + VL_SIGW(__Vtemp886,127,0,4); + VL_SIGW(__Vtemp887,127,0,4); + VL_SIGW(__Vtemp888,127,0,4); + VL_SIGW(__Vtemp889,127,0,4); + VL_SIGW(__Vtemp890,127,0,4); + VL_SIGW(__Vtemp891,127,0,4); + VL_SIGW(__Vtemp892,127,0,4); + VL_SIGW(__Vtemp893,127,0,4); + VL_SIGW(__Vtemp894,127,0,4); + VL_SIGW(__Vtemp895,127,0,4); + VL_SIGW(__Vtemp896,127,0,4); + VL_SIGW(__Vtemp897,127,0,4); + VL_SIGW(__Vtemp898,127,0,4); + VL_SIGW(__Vtemp899,127,0,4); + VL_SIGW(__Vtemp900,127,0,4); + VL_SIGW(__Vtemp901,127,0,4); + VL_SIGW(__Vtemp902,127,0,4); + VL_SIGW(__Vtemp903,127,0,4); + VL_SIGW(__Vtemp904,127,0,4); + VL_SIGW(__Vtemp905,127,0,4); + VL_SIGW(__Vtemp906,127,0,4); + VL_SIGW(__Vtemp907,127,0,4); + VL_SIGW(__Vtemp908,127,0,4); + VL_SIGW(__Vtemp909,127,0,4); + VL_SIGW(__Vtemp910,127,0,4); + VL_SIGW(__Vtemp911,127,0,4); + VL_SIGW(__Vtemp912,127,0,4); + VL_SIGW(__Vtemp913,127,0,4); + VL_SIGW(__Vtemp914,127,0,4); + VL_SIGW(__Vtemp915,127,0,4); + VL_SIGW(__Vtemp916,127,0,4); + VL_SIGW(__Vtemp917,127,0,4); + VL_SIGW(__Vtemp918,127,0,4); + VL_SIGW(__Vtemp919,127,0,4); + VL_SIGW(__Vtemp920,127,0,4); + VL_SIGW(__Vtemp921,127,0,4); + VL_SIGW(__Vtemp922,127,0,4); + VL_SIGW(__Vtemp923,127,0,4); + VL_SIGW(__Vtemp924,127,0,4); + VL_SIGW(__Vtemp925,127,0,4); + VL_SIGW(__Vtemp926,127,0,4); + VL_SIGW(__Vtemp927,127,0,4); + VL_SIGW(__Vtemp928,127,0,4); + VL_SIGW(__Vtemp929,127,0,4); + VL_SIGW(__Vtemp930,127,0,4); + VL_SIGW(__Vtemp931,127,0,4); + VL_SIGW(__Vtemp932,127,0,4); + VL_SIGW(__Vtemp933,127,0,4); + VL_SIGW(__Vtemp934,127,0,4); + // Body + { + vcdp->chgBit (c+708,(vlTOPp->cache_simX__DOT__icache_i_m_ready)); + vcdp->chgBit (c+709,(vlTOPp->cache_simX__DOT__dcache_i_m_ready)); + vcdp->chgBus (c+710,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests),4); + vcdp->chgBit (c+711,((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests)))); + vcdp->chgBus (c+712,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32); + vcdp->chgBus (c+713,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32); + vcdp->chgBus (c+714,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32); + vcdp->chgBus (c+715,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind),32); + vcdp->chgBus (c+716,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr)),32); + vcdp->chgBit (c+717,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))); + vcdp->chgArray(c+718,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read),128); + vcdp->chgBus (c+722,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict),1); + vcdp->chgBus (c+723,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state),4); + vcdp->chgBus (c+724,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid),4); + vcdp->chgBus (c+725,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr),32); + vcdp->chgBus (c+726,((0xfffffff0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr)),32); + vcdp->chgBit (c+727,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)))); + vcdp->chgBus (c+728,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read),32); + vcdp->chgBus (c+729,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict),1); + vcdp->chgBus (c+730,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state),4); + vcdp->chgBus (c+731,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid),1); + vcdp->chgBus (c+732,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr),32); + vcdp->chgBus (c+733,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag + [0U]),23); + __Vtemp605[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][0U]; + __Vtemp605[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][1U]; + __Vtemp605[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][2U]; + __Vtemp605[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][3U]; + vcdp->chgArray(c+734,(__Vtemp605),128); + vcdp->chgBit (c+738,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid + [0U])); + vcdp->chgBit (c+739,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty + [0U])); + __Vtemp606[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][0U]; + __Vtemp606[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][1U]; + __Vtemp606[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][2U]; + __Vtemp606[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [0U][3U]; + vcdp->chgArray(c+740,(__Vtemp606),128); + __Vtemp607[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [1U][0U]; + __Vtemp607[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [1U][1U]; + __Vtemp607[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [1U][2U]; + __Vtemp607[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [1U][3U]; + vcdp->chgArray(c+744,(__Vtemp607),128); + __Vtemp608[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [2U][0U]; + __Vtemp608[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [2U][1U]; + __Vtemp608[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [2U][2U]; + __Vtemp608[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [2U][3U]; + vcdp->chgArray(c+748,(__Vtemp608),128); + __Vtemp609[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [3U][0U]; + __Vtemp609[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [3U][1U]; + __Vtemp609[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [3U][2U]; + __Vtemp609[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [3U][3U]; + vcdp->chgArray(c+752,(__Vtemp609),128); + __Vtemp610[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [4U][0U]; + __Vtemp610[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [4U][1U]; + __Vtemp610[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [4U][2U]; + __Vtemp610[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [4U][3U]; + vcdp->chgArray(c+756,(__Vtemp610),128); + __Vtemp611[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [5U][0U]; + __Vtemp611[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [5U][1U]; + __Vtemp611[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [5U][2U]; + __Vtemp611[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [5U][3U]; + vcdp->chgArray(c+760,(__Vtemp611),128); + __Vtemp612[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [6U][0U]; + __Vtemp612[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [6U][1U]; + __Vtemp612[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [6U][2U]; + __Vtemp612[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [6U][3U]; + vcdp->chgArray(c+764,(__Vtemp612),128); + __Vtemp613[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [7U][0U]; + __Vtemp613[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [7U][1U]; + __Vtemp613[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [7U][2U]; + __Vtemp613[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data + [7U][3U]; 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+ vcdp->chgBit (c+3043,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[14])); + vcdp->chgBit (c+3044,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[15])); + vcdp->chgBit (c+3045,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[16])); + vcdp->chgBit (c+3046,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[17])); + vcdp->chgBit (c+3047,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[18])); + vcdp->chgBit (c+3048,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[19])); + vcdp->chgBit (c+3049,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[20])); + vcdp->chgBit (c+3050,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[21])); + vcdp->chgBit (c+3051,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[22])); + vcdp->chgBit (c+3052,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[23])); + vcdp->chgBit (c+3053,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[24])); + vcdp->chgBit (c+3054,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[25])); + vcdp->chgBit (c+3055,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[26])); + vcdp->chgBit (c+3056,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[27])); + vcdp->chgBit (c+3057,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[28])); + vcdp->chgBit (c+3058,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[29])); + vcdp->chgBit (c+3059,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[30])); + vcdp->chgBit (c+3060,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[31])); + vcdp->chgBus (c+3061,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f),32); + vcdp->chgBus (c+3062,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind),32); + } +} + +void Vcache_simX::traceChgThis__6(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c=code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + vcdp->chgBit (c+3063,(vlTOPp->clk)); + vcdp->chgBit (c+3064,(vlTOPp->reset)); + vcdp->chgBus (c+3065,(vlTOPp->in_icache_pc_addr),32); + vcdp->chgBit (c+3066,(vlTOPp->in_icache_valid_pc_addr)); + vcdp->chgBit (c+3067,(vlTOPp->out_icache_stall)); + vcdp->chgBus (c+3068,(vlTOPp->in_dcache_mem_read),3); + vcdp->chgBus (c+3069,(vlTOPp->in_dcache_mem_write),3); + vcdp->chgBit (c+3070,(vlTOPp->in_dcache_in_valid[0])); + vcdp->chgBit (c+3071,(vlTOPp->in_dcache_in_valid[1])); + vcdp->chgBit (c+3072,(vlTOPp->in_dcache_in_valid[2])); + vcdp->chgBit (c+3073,(vlTOPp->in_dcache_in_valid[3])); + vcdp->chgBus (c+3074,(vlTOPp->in_dcache_in_address[0]),32); + vcdp->chgBus (c+3075,(vlTOPp->in_dcache_in_address[1]),32); + vcdp->chgBus (c+3076,(vlTOPp->in_dcache_in_address[2]),32); + vcdp->chgBus (c+3077,(vlTOPp->in_dcache_in_address[3]),32); + vcdp->chgBit (c+3078,(vlTOPp->out_dcache_stall)); + vcdp->chgBus (c+3079,(((IData)(vlTOPp->in_icache_valid_pc_addr) + ? 2U : 7U)),3); + } +} diff --git a/simX/obj_dir/Vcache_simX__Trace__Slow.cpp b/simX/obj_dir/Vcache_simX__Trace__Slow.cpp new file mode 100644 index 00000000..7b113aa4 --- /dev/null +++ b/simX/obj_dir/Vcache_simX__Trace__Slow.cpp @@ -0,0 +1,7765 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Tracing implementation internals +#include "verilated_vcd_c.h" +#include "Vcache_simX__Syms.h" + + +//====================== + +void Vcache_simX::trace (VerilatedVcdC* tfp, int, int) { + tfp->spTrace()->addCallback (&Vcache_simX::traceInit, &Vcache_simX::traceFull, &Vcache_simX::traceChg, this); +} +void Vcache_simX::traceInit(VerilatedVcd* vcdp, void* userthis, uint32_t code) { + // Callback from vcd->open() + Vcache_simX* t=(Vcache_simX*)userthis; + Vcache_simX__Syms* __restrict vlSymsp = t->__VlSymsp; // Setup global symbol table + if (!Verilated::calcUnusedSigs()) VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Turning on wave traces requires Verilated::traceEverOn(true) call before time 0."); + vcdp->scopeEscape(' '); + t->traceInitThis (vlSymsp, vcdp, code); + vcdp->scopeEscape('.'); +} +void Vcache_simX::traceFull(VerilatedVcd* vcdp, void* userthis, uint32_t code) { + // Callback from vcd->dump() + Vcache_simX* t=(Vcache_simX*)userthis; + Vcache_simX__Syms* __restrict vlSymsp = t->__VlSymsp; // Setup global symbol table + t->traceFullThis (vlSymsp, vcdp, code); +} + +//====================== + + +void Vcache_simX::traceInitThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c=code; + if (0 && vcdp && c) {} // Prevent unused + vcdp->module(vlSymsp->name()); // Setup signal names + // Body + { + vlTOPp->traceInitThis__1(vlSymsp, vcdp, code); + } +} + +void Vcache_simX::traceFullThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c=code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + vlTOPp->traceFullThis__1(vlSymsp, vcdp, code); + } + // Final + vlTOPp->__Vm_traceActivity = 0U; +} + +void Vcache_simX::traceInitThis__1(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c=code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + vcdp->declBit (c+3063,"clk",-1); + vcdp->declBit (c+3064,"reset",-1); + vcdp->declBus (c+3065,"in_icache_pc_addr",-1,31,0); + vcdp->declBit (c+3066,"in_icache_valid_pc_addr",-1); + vcdp->declBit (c+3067,"out_icache_stall",-1); + vcdp->declBus (c+3068,"in_dcache_mem_read",-1,2,0); + vcdp->declBus (c+3069,"in_dcache_mem_write",-1,2,0); + {int i; for (i=0; i<4; i++) { + vcdp->declBit (c+3070+i*1,"in_dcache_in_valid",(i+0));}} + {int i; for (i=0; i<4; i++) { + vcdp->declBus (c+3074+i*1,"in_dcache_in_address",(i+0),31,0);}} + vcdp->declBit (c+3078,"out_dcache_stall",-1); + vcdp->declBit (c+3063,"cache_simX clk",-1); + vcdp->declBit (c+3064,"cache_simX reset",-1); + vcdp->declBus (c+3065,"cache_simX in_icache_pc_addr",-1,31,0); + vcdp->declBit (c+3066,"cache_simX in_icache_valid_pc_addr",-1); + vcdp->declBit (c+3067,"cache_simX out_icache_stall",-1); + vcdp->declBus (c+3068,"cache_simX in_dcache_mem_read",-1,2,0); + vcdp->declBus (c+3069,"cache_simX in_dcache_mem_write",-1,2,0); + {int i; for (i=0; i<4; i++) { + vcdp->declBit (c+3070+i*1,"cache_simX in_dcache_in_valid",(i+0));}} + {int i; for (i=0; i<4; i++) { + vcdp->declBus (c+3074+i*1,"cache_simX in_dcache_in_address",(i+0),31,0);}} + vcdp->declBit (c+3078,"cache_simX out_dcache_stall",-1); + // Tracing: cache_simX VX_icache_req__Viftop // Ignored: Verilator trace_off at cache_simX.v:28 + // Tracing: cache_simX VX_icache_rsp__Viftop // Ignored: Verilator trace_off at cache_simX.v:36 + // Tracing: cache_simX VX_dram_req_rsp_icache__Viftop // Ignored: Verilator trace_off at cache_simX.v:45 + vcdp->declBit (c+708,"cache_simX icache_i_m_ready",-1); + // Tracing: cache_simX VX_dcache_req__Viftop // Ignored: Verilator trace_off at cache_simX.v:55 + // Tracing: cache_simX curr_t // Ignored: Verilator trace_off at cache_simX.v:60 + // Tracing: cache_simX VX_dcache_rsp__Viftop // Ignored: Verilator trace_off at cache_simX.v:67 + // Tracing: cache_simX VX_dram_req_rsp__Viftop // Ignored: Verilator trace_off at cache_simX.v:76 + vcdp->declBit (c+709,"cache_simX dcache_i_m_ready",-1); + vcdp->declBit (c+3063,"cache_simX dmem_controller clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller reset",-1); + // Tracing: cache_simX dmem_controller VX_dram_req_rsp // Ignored: Unsupported: data type at ../rtl/VX_dmem_controller.v:8 + // Tracing: cache_simX dmem_controller VX_dram_req_rsp_icache // Ignored: Unsupported: data type at ../rtl/VX_dmem_controller.v:9 + // Tracing: cache_simX dmem_controller VX_icache_req // Ignored: Unsupported: data type at ../rtl/VX_dmem_controller.v:11 + // Tracing: cache_simX dmem_controller VX_icache_rsp // Ignored: Unsupported: data type at ../rtl/VX_dmem_controller.v:12 + // Tracing: cache_simX dmem_controller VX_dcache_req // Ignored: Unsupported: data type at ../rtl/VX_dmem_controller.v:13 + // Tracing: cache_simX dmem_controller VX_dcache_rsp // Ignored: Unsupported: data type at ../rtl/VX_dmem_controller.v:14 + vcdp->declBit (c+1,"cache_simX dmem_controller to_shm",-1); + vcdp->declBus (c+2,"cache_simX dmem_controller sm_driver_in_valid",-1,3,0); + vcdp->declBus (c+3,"cache_simX dmem_controller cache_driver_in_valid",-1,3,0); + vcdp->declBit (c+4,"cache_simX dmem_controller read_or_write",-1); + vcdp->declArray(c+5,"cache_simX dmem_controller cache_driver_in_address",-1,127,0); + vcdp->declBus (c+9,"cache_simX dmem_controller cache_driver_in_mem_read",-1,2,0); + vcdp->declBus (c+10,"cache_simX dmem_controller cache_driver_in_mem_write",-1,2,0); + vcdp->declArray(c+3080,"cache_simX dmem_controller cache_driver_in_data",-1,127,0); + vcdp->declBus (c+11,"cache_simX dmem_controller sm_driver_in_mem_read",-1,2,0); + vcdp->declBus (c+12,"cache_simX dmem_controller sm_driver_in_mem_write",-1,2,0); + vcdp->declArray(c+13,"cache_simX dmem_controller cache_driver_out_data",-1,127,0); + vcdp->declArray(c+17,"cache_simX dmem_controller sm_driver_out_data",-1,127,0); + vcdp->declBus (c+21,"cache_simX dmem_controller cache_driver_out_valid",-1,3,0); + vcdp->declBit (c+22,"cache_simX dmem_controller sm_delay",-1); + vcdp->declBit (c+583,"cache_simX dmem_controller cache_delay",-1); + vcdp->declBus (c+584,"cache_simX dmem_controller icache_instruction_out",-1,31,0); + vcdp->declBit (c+585,"cache_simX dmem_controller icache_delay",-1); + vcdp->declBit (c+3066,"cache_simX dmem_controller icache_driver_in_valid",-1); + vcdp->declBus (c+3065,"cache_simX dmem_controller icache_driver_in_address",-1,31,0); + vcdp->declBus (c+23,"cache_simX dmem_controller icache_driver_in_mem_read",-1,2,0); + vcdp->declBus (c+3084,"cache_simX dmem_controller icache_driver_in_mem_write",-1,2,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller icache_driver_in_data",-1,31,0); + vcdp->declBit (c+3086,"cache_simX dmem_controller read_or_write_ic",-1); + vcdp->declBit (c+586,"cache_simX dmem_controller valid_read_cache",-1); + vcdp->declBus (c+3087,"cache_simX dmem_controller shared_memory SM_SIZE",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller shared_memory SM_BANKS",-1,31,0); + vcdp->declBus (c+3089,"cache_simX dmem_controller shared_memory SM_BYTES_PER_READ",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller shared_memory SM_WORDS_PER_READ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller shared_memory SM_LOG_WORDS_PER_READ",-1,31,0); + vcdp->declBus (c+3091,"cache_simX dmem_controller shared_memory SM_HEIGHT",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller shared_memory SM_BANK_OFFSET_START",-1,31,0); + vcdp->declBus (c+3092,"cache_simX dmem_controller shared_memory SM_BANK_OFFSET_END",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller shared_memory SM_BLOCK_OFFSET_START",-1,31,0); + vcdp->declBus (c+3093,"cache_simX dmem_controller shared_memory SM_BLOCK_OFFSET_END",-1,31,0); + vcdp->declBus (c+3094,"cache_simX dmem_controller shared_memory SM_INDEX_START",-1,31,0); + vcdp->declBus (c+3095,"cache_simX dmem_controller shared_memory SM_INDEX_END",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller shared_memory NUM_REQ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller shared_memory BITS_PER_BANK",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller shared_memory clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller shared_memory reset",-1); + vcdp->declBus (c+2,"cache_simX dmem_controller shared_memory in_valid",-1,3,0); + vcdp->declArray(c+5,"cache_simX dmem_controller shared_memory in_address",-1,127,0); + vcdp->declArray(c+3080,"cache_simX dmem_controller shared_memory in_data",-1,127,0); + vcdp->declBus (c+11,"cache_simX dmem_controller shared_memory mem_read",-1,2,0); + vcdp->declBus (c+12,"cache_simX dmem_controller shared_memory mem_write",-1,2,0); + vcdp->declBus (c+21,"cache_simX dmem_controller shared_memory out_valid",-1,3,0); + vcdp->declArray(c+17,"cache_simX dmem_controller shared_memory out_data",-1,127,0); + vcdp->declBit (c+22,"cache_simX dmem_controller shared_memory stall",-1); + vcdp->declArray(c+24,"cache_simX dmem_controller shared_memory temp_address",-1,127,0); + vcdp->declArray(c+28,"cache_simX dmem_controller shared_memory temp_in_data",-1,127,0); + vcdp->declBus (c+32,"cache_simX dmem_controller shared_memory temp_in_valid",-1,3,0); + vcdp->declBus (c+33,"cache_simX dmem_controller shared_memory temp_out_valid",-1,3,0); + vcdp->declArray(c+34,"cache_simX dmem_controller shared_memory temp_out_data",-1,127,0); + vcdp->declBus (c+38,"cache_simX dmem_controller shared_memory block_addr",-1,27,0); + vcdp->declArray(c+39,"cache_simX dmem_controller shared_memory block_wdata",-1,511,0); + vcdp->declArray(c+55,"cache_simX dmem_controller shared_memory block_rdata",-1,511,0); + vcdp->declBus (c+71,"cache_simX dmem_controller shared_memory block_we",-1,7,0); + vcdp->declBit (c+72,"cache_simX dmem_controller shared_memory send_data",-1); + vcdp->declBus (c+73,"cache_simX dmem_controller shared_memory req_num",-1,11,0); + vcdp->declBus (c+74,"cache_simX dmem_controller shared_memory orig_in_valid",-1,3,0); + // Tracing: cache_simX dmem_controller shared_memory f // Ignored: Verilator trace_off at ../rtl/shared_memory/VX_shared_memory.v:62 + // Tracing: cache_simX dmem_controller shared_memory j // Ignored: Verilator trace_off at ../rtl/shared_memory/VX_shared_memory.v:91 + vcdp->declBus (c+3096,"cache_simX dmem_controller shared_memory i",-1,31,0); + vcdp->declBit (c+75,"cache_simX dmem_controller shared_memory genblk2[0] shm_write",-1); + vcdp->declBit (c+76,"cache_simX dmem_controller shared_memory genblk2[1] shm_write",-1); + vcdp->declBit (c+77,"cache_simX dmem_controller shared_memory genblk2[2] shm_write",-1); + vcdp->declBit (c+78,"cache_simX dmem_controller shared_memory genblk2[3] shm_write",-1); + vcdp->declBus (c+3092,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm NB",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm BITS_PER_BANK",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm NUM_REQ",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm reset",-1); + vcdp->declBus (c+74,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm in_valid",-1,3,0); + vcdp->declArray(c+5,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm in_address",-1,127,0); + vcdp->declArray(c+3080,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm in_data",-1,127,0); + vcdp->declBus (c+32,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm out_valid",-1,3,0); + vcdp->declArray(c+24,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm out_address",-1,127,0); + vcdp->declArray(c+28,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm out_data",-1,127,0); + vcdp->declBus (c+73,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm req_num",-1,11,0); + vcdp->declBit (c+22,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm stall",-1); + vcdp->declBit (c+72,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm send_data",-1); + vcdp->declBus (c+710,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm left_requests",-1,3,0); + vcdp->declBus (c+79,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm serviced",-1,3,0); + vcdp->declBus (c+80,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm use_valid",-1,3,0); + vcdp->declBit (c+711,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm requests_left",-1); + vcdp->declBus (c+81,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm bank_valids",-1,15,0); + vcdp->declBus (c+82,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm more_than_one_valid",-1,3,0); + // Tracing: cache_simX dmem_controller shared_memory vx_priority_encoder_sm curr_bank // Ignored: Verilator trace_off at ../rtl/shared_memory/VX_priority_encoder_sm.v:49 + vcdp->declBus (c+83,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm internal_req_num",-1,7,0); + vcdp->declBus (c+32,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm internal_out_valid",-1,3,0); + // Tracing: cache_simX dmem_controller shared_memory vx_priority_encoder_sm curr_bank_o // Ignored: Verilator trace_off at ../rtl/shared_memory/VX_priority_encoder_sm.v:73 + vcdp->declBus (c+3096,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm curr_b",-1,31,0); + vcdp->declBus (c+84,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm serviced_qual",-1,3,0); + vcdp->declBus (c+587,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm new_left_requests",-1,3,0); + vcdp->declBus (c+85,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[0] num_valids",-1,2,0); + vcdp->declBus (c+86,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[1] num_valids",-1,2,0); + vcdp->declBus (c+87,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[2] num_valids",-1,2,0); + vcdp->declBus (c+88,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[3] num_valids",-1,2,0); + vcdp->declBus (c+3092,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid NB",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid BITS_PER_BANK",-1,31,0); + vcdp->declBus (c+80,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid in_valids",-1,3,0); + vcdp->declArray(c+5,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid in_addr",-1,127,0); + vcdp->declBus (c+81,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid bank_valids",-1,15,0); + vcdp->declBus (c+3096,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid i",-1,31,0); + vcdp->declBus (c+3096,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm vx_bank_valid j",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[0] valids_counter N",-1,31,0); + vcdp->declBus (c+89,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[0] valids_counter valids",-1,3,0); + vcdp->declBus (c+85,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[0] valids_counter count",-1,2,0); + vcdp->declBus (c+3097,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[0] valids_counter i",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[1] valids_counter N",-1,31,0); + vcdp->declBus (c+90,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[1] valids_counter valids",-1,3,0); + vcdp->declBus (c+86,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[1] valids_counter count",-1,2,0); + vcdp->declBus (c+3097,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[1] valids_counter i",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[2] valids_counter N",-1,31,0); + vcdp->declBus (c+91,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[2] valids_counter valids",-1,3,0); + vcdp->declBus (c+87,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[2] valids_counter count",-1,2,0); + vcdp->declBus (c+3097,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[2] valids_counter i",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[3] valids_counter N",-1,31,0); + vcdp->declBus (c+92,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[3] valids_counter valids",-1,3,0); + vcdp->declBus (c+88,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[3] valids_counter count",-1,2,0); + vcdp->declBus (c+3097,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk1[3] valids_counter i",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[0] vx_priority_encoder N",-1,31,0); + vcdp->declBus (c+89,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[0] vx_priority_encoder valids",-1,3,0); + vcdp->declBus (c+93,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[0] vx_priority_encoder index",-1,1,0); + vcdp->declBit (c+94,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[0] vx_priority_encoder found",-1); + vcdp->declBus (c+95,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[0] vx_priority_encoder i",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[1] vx_priority_encoder N",-1,31,0); + vcdp->declBus (c+90,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[1] vx_priority_encoder valids",-1,3,0); + vcdp->declBus (c+96,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[1] vx_priority_encoder index",-1,1,0); + vcdp->declBit (c+97,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[1] vx_priority_encoder found",-1); + vcdp->declBus (c+98,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[1] vx_priority_encoder i",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[2] vx_priority_encoder N",-1,31,0); + vcdp->declBus (c+91,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[2] vx_priority_encoder valids",-1,3,0); + vcdp->declBus (c+99,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[2] vx_priority_encoder index",-1,1,0); + vcdp->declBit (c+100,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[2] vx_priority_encoder found",-1); + vcdp->declBus (c+101,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[2] vx_priority_encoder i",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[3] vx_priority_encoder N",-1,31,0); + vcdp->declBus (c+92,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[3] vx_priority_encoder valids",-1,3,0); + vcdp->declBus (c+102,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[3] vx_priority_encoder index",-1,1,0); + vcdp->declBit (c+103,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[3] vx_priority_encoder found",-1); + vcdp->declBus (c+104,"cache_simX dmem_controller shared_memory vx_priority_encoder_sm genblk2[3] vx_priority_encoder i",-1,31,0); + vcdp->declBus (c+3098,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_SIZE",-1,31,0); + vcdp->declBus (c+3089,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_BYTES_PER_READ",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_WORDS_PER_READ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_LOG_WORDS_PER_READ",-1,31,0); + vcdp->declBus (c+3091,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block SMB_HEIGHT",-1,31,0); + vcdp->declBus (c+3092,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block BITS_PER_BANK",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block reset",-1); + vcdp->declBus (c+105,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block addr",-1,6,0); + vcdp->declArray(c+106,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block wdata",-1,127,0); + vcdp->declBus (c+110,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block we",-1,1,0); + vcdp->declBit (c+75,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block shm_write",-1); + vcdp->declArray(c+588,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block data_out",-1,127,0); + // Tracing: cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block shared_memory // Ignored: Wide memory > --trace-max-array ents at ../rtl/shared_memory/VX_shared_memory_block.v:32 + vcdp->declBus (c+712,"cache_simX dmem_controller shared_memory genblk2[0] vx_shared_memory_block curr_ind",-1,31,0); + vcdp->declBus (c+3098,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_SIZE",-1,31,0); + vcdp->declBus (c+3089,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_BYTES_PER_READ",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_WORDS_PER_READ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_LOG_WORDS_PER_READ",-1,31,0); + vcdp->declBus (c+3091,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block SMB_HEIGHT",-1,31,0); + vcdp->declBus (c+3092,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block BITS_PER_BANK",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block reset",-1); + vcdp->declBus (c+111,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block addr",-1,6,0); + vcdp->declArray(c+112,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block wdata",-1,127,0); + vcdp->declBus (c+116,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block we",-1,1,0); + vcdp->declBit (c+76,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block shm_write",-1); + vcdp->declArray(c+592,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block data_out",-1,127,0); + // Tracing: cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block shared_memory // Ignored: Wide memory > --trace-max-array ents at ../rtl/shared_memory/VX_shared_memory_block.v:32 + vcdp->declBus (c+713,"cache_simX dmem_controller shared_memory genblk2[1] vx_shared_memory_block curr_ind",-1,31,0); + vcdp->declBus (c+3098,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_SIZE",-1,31,0); + vcdp->declBus (c+3089,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_BYTES_PER_READ",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_WORDS_PER_READ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_LOG_WORDS_PER_READ",-1,31,0); + vcdp->declBus (c+3091,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block SMB_HEIGHT",-1,31,0); + vcdp->declBus (c+3092,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block BITS_PER_BANK",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block reset",-1); + vcdp->declBus (c+117,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block addr",-1,6,0); + vcdp->declArray(c+118,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block wdata",-1,127,0); + vcdp->declBus (c+122,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block we",-1,1,0); + vcdp->declBit (c+77,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block shm_write",-1); + vcdp->declArray(c+596,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block data_out",-1,127,0); + // Tracing: cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block shared_memory // Ignored: Wide memory > --trace-max-array ents at ../rtl/shared_memory/VX_shared_memory_block.v:32 + vcdp->declBus (c+714,"cache_simX dmem_controller shared_memory genblk2[2] vx_shared_memory_block curr_ind",-1,31,0); + vcdp->declBus (c+3098,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_SIZE",-1,31,0); + vcdp->declBus (c+3089,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_BYTES_PER_READ",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_WORDS_PER_READ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_LOG_WORDS_PER_READ",-1,31,0); + vcdp->declBus (c+3091,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block SMB_HEIGHT",-1,31,0); + vcdp->declBus (c+3092,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block BITS_PER_BANK",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block reset",-1); + vcdp->declBus (c+123,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block addr",-1,6,0); + vcdp->declArray(c+124,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block wdata",-1,127,0); + vcdp->declBus (c+128,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block we",-1,1,0); + vcdp->declBit (c+78,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block shm_write",-1); + vcdp->declArray(c+600,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block data_out",-1,127,0); + // Tracing: cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block shared_memory // Ignored: Wide memory > --trace-max-array ents at ../rtl/shared_memory/VX_shared_memory_block.v:32 + vcdp->declBus (c+715,"cache_simX dmem_controller shared_memory genblk2[3] vx_shared_memory_block curr_ind",-1,31,0); + vcdp->declBus (c+3098,"cache_simX dmem_controller dcache CACHE_SIZE",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache CACHE_WAYS",-1,31,0); + vcdp->declBus (c+3099,"cache_simX dmem_controller dcache CACHE_BLOCK",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache CACHE_BANKS",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache LOG_NUM_BANKS",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache NUM_REQ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache LOG_NUM_REQ",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller dcache NUM_IND",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache OFFSET_SIZE_START",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache OFFSET_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3102,"cache_simX dmem_controller dcache TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache IND_SIZE_END",-1,31,0); + vcdp->declBus (c+3103,"cache_simX dmem_controller dcache ADDR_TAG_START",-1,31,0); + vcdp->declBus (c+3104,"cache_simX dmem_controller dcache ADDR_TAG_END",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache ADDR_OFFSET_START",-1,31,0); + vcdp->declBus (c+3093,"cache_simX dmem_controller dcache ADDR_OFFSET_END",-1,31,0); + vcdp->declBus (c+3094,"cache_simX dmem_controller dcache ADDR_IND_START",-1,31,0); + vcdp->declBus (c+3105,"cache_simX dmem_controller dcache ADDR_IND_END",-1,31,0); + vcdp->declBus (c+3106,"cache_simX dmem_controller dcache MEM_ADDR_REQ_MASK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache CACHE_IDLE",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache SEND_MEM_REQ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache RECIV_MEM_RSP",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller dcache clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller dcache rst",-1); + vcdp->declBus (c+3,"cache_simX dmem_controller dcache i_p_valid",-1,3,0); + vcdp->declArray(c+5,"cache_simX dmem_controller dcache i_p_addr",-1,127,0); + vcdp->declArray(c+3080,"cache_simX dmem_controller dcache i_p_writedata",-1,127,0); + vcdp->declBit (c+4,"cache_simX dmem_controller dcache i_p_read_or_write",-1); + vcdp->declArray(c+13,"cache_simX dmem_controller dcache o_p_readdata",-1,127,0); + vcdp->declBit (c+583,"cache_simX dmem_controller dcache o_p_delay",-1); + vcdp->declBus (c+129,"cache_simX dmem_controller dcache o_m_evict_addr",-1,31,0); + vcdp->declBus (c+716,"cache_simX dmem_controller dcache o_m_read_addr",-1,31,0); + vcdp->declBit (c+717,"cache_simX dmem_controller dcache o_m_valid",-1); + vcdp->declArray(c+130,"cache_simX dmem_controller dcache o_m_writedata",-1,511,0); + vcdp->declBit (c+604,"cache_simX dmem_controller dcache o_m_read_or_write",-1); + vcdp->declArray(c+3107,"cache_simX dmem_controller dcache i_m_readdata",-1,511,0); + vcdp->declBit (c+709,"cache_simX dmem_controller dcache i_m_ready",-1); + vcdp->declBus (c+9,"cache_simX dmem_controller dcache i_p_mem_read",-1,2,0); + vcdp->declBus (c+10,"cache_simX dmem_controller dcache i_p_mem_write",-1,2,0); + vcdp->declArray(c+718,"cache_simX dmem_controller dcache final_data_read",-1,127,0); + vcdp->declArray(c+146,"cache_simX dmem_controller dcache new_final_data_read",-1,127,0); + vcdp->declArray(c+13,"cache_simX dmem_controller dcache new_final_data_read_Qual",-1,127,0); + vcdp->declBus (c+722,"cache_simX dmem_controller dcache global_way_to_evict",-1,0,0); + vcdp->declBus (c+150,"cache_simX dmem_controller dcache thread_track_banks",-1,15,0); + vcdp->declBus (c+151,"cache_simX dmem_controller dcache index_per_bank",-1,7,0); + vcdp->declBus (c+152,"cache_simX dmem_controller dcache use_mask_per_bank",-1,15,0); + vcdp->declBus (c+153,"cache_simX dmem_controller dcache valid_per_bank",-1,3,0); + vcdp->declBus (c+154,"cache_simX dmem_controller dcache threads_serviced_per_bank",-1,15,0); + vcdp->declArray(c+155,"cache_simX dmem_controller dcache readdata_per_bank",-1,127,0); + vcdp->declBus (c+159,"cache_simX dmem_controller dcache hit_per_bank",-1,3,0); + vcdp->declBus (c+160,"cache_simX dmem_controller dcache eviction_wb",-1,3,0); + vcdp->declBus (c+3123,"cache_simX dmem_controller dcache eviction_wb_old",-1,3,0); + vcdp->declBus (c+723,"cache_simX dmem_controller dcache state",-1,3,0); + vcdp->declBus (c+161,"cache_simX dmem_controller dcache new_state",-1,3,0); + vcdp->declBus (c+162,"cache_simX dmem_controller dcache use_valid",-1,3,0); + vcdp->declBus (c+724,"cache_simX dmem_controller dcache stored_valid",-1,3,0); + vcdp->declBus (c+163,"cache_simX dmem_controller dcache new_stored_valid",-1,3,0); + vcdp->declArray(c+164,"cache_simX dmem_controller dcache eviction_addr_per_bank",-1,127,0); + vcdp->declBus (c+725,"cache_simX dmem_controller dcache miss_addr",-1,31,0); + vcdp->declBit (c+168,"cache_simX dmem_controller dcache curr_processor_request_valid",-1); + vcdp->declBus (c+169,"cache_simX dmem_controller dcache threads_serviced_Qual",-1,3,0); + {int i; for (i=0; i<4; i++) { + vcdp->declBus (c+170+i*1,"cache_simX dmem_controller dcache debug_hit_per_bank_mask",(i+0),3,0);}} + // Tracing: cache_simX dmem_controller dcache bid // Ignored: Verilator trace_off at ../rtl/cache/VX_d_cache.v:163 + vcdp->declBus (c+3096,"cache_simX dmem_controller dcache test_bid",-1,31,0); + vcdp->declBus (c+174,"cache_simX dmem_controller dcache detect_bank_miss",-1,3,0); + vcdp->declBus (c+3096,"cache_simX dmem_controller dcache bbid",-1,31,0); + // Tracing: cache_simX dmem_controller dcache tid // Ignored: Verilator trace_off at ../rtl/cache/VX_d_cache.v:209 + vcdp->declBit (c+583,"cache_simX dmem_controller dcache delay",-1); + vcdp->declBus (c+151,"cache_simX dmem_controller dcache send_index_to_bank",-1,7,0); + vcdp->declBus (c+175,"cache_simX dmem_controller dcache miss_bank_index",-1,1,0); + vcdp->declBit (c+176,"cache_simX dmem_controller dcache miss_found",-1); + vcdp->declBit (c+605,"cache_simX dmem_controller dcache update_global_way_to_evict",-1); + // Tracing: cache_simX dmem_controller dcache cur_t // Ignored: Verilator trace_off at ../rtl/cache/VX_d_cache.v:249 + vcdp->declBus (c+3124,"cache_simX dmem_controller dcache init_b",-1,31,0); + // Tracing: cache_simX dmem_controller dcache bank_id // Ignored: Verilator trace_off at ../rtl/cache/VX_d_cache.v:294 + vcdp->declBus (c+177,"cache_simX dmem_controller dcache genblk1[0] use_threads_track_banks",-1,3,0); + vcdp->declBus (c+178,"cache_simX dmem_controller dcache genblk1[0] use_thread_index",-1,1,0); + vcdp->declBit (c+179,"cache_simX dmem_controller dcache genblk1[0] use_write_final_data",-1); + vcdp->declBus (c+180,"cache_simX dmem_controller dcache genblk1[0] use_data_final_data",-1,31,0); + vcdp->declBus (c+181,"cache_simX dmem_controller dcache genblk1[1] use_threads_track_banks",-1,3,0); + vcdp->declBus (c+182,"cache_simX dmem_controller dcache genblk1[1] use_thread_index",-1,1,0); + vcdp->declBit (c+183,"cache_simX dmem_controller dcache genblk1[1] use_write_final_data",-1); + vcdp->declBus (c+184,"cache_simX dmem_controller dcache genblk1[1] use_data_final_data",-1,31,0); + vcdp->declBus (c+185,"cache_simX dmem_controller dcache genblk1[2] use_threads_track_banks",-1,3,0); + vcdp->declBus (c+186,"cache_simX dmem_controller dcache genblk1[2] use_thread_index",-1,1,0); + vcdp->declBit (c+187,"cache_simX dmem_controller dcache genblk1[2] use_write_final_data",-1); + vcdp->declBus (c+188,"cache_simX dmem_controller dcache genblk1[2] use_data_final_data",-1,31,0); + vcdp->declBus (c+189,"cache_simX dmem_controller dcache genblk1[3] use_threads_track_banks",-1,3,0); + vcdp->declBus (c+190,"cache_simX dmem_controller dcache genblk1[3] use_thread_index",-1,1,0); + vcdp->declBit (c+191,"cache_simX dmem_controller dcache genblk1[3] use_write_final_data",-1); + vcdp->declBus (c+192,"cache_simX dmem_controller dcache genblk1[3] use_data_final_data",-1,31,0); + vcdp->declBus (c+193,"cache_simX dmem_controller dcache genblk3[0] bank_addr",-1,31,0); + vcdp->declBus (c+194,"cache_simX dmem_controller dcache genblk3[0] byte_select",-1,1,0); + vcdp->declBus (c+195,"cache_simX dmem_controller dcache genblk3[0] cache_tag",-1,20,0); + vcdp->declBus (c+3125,"cache_simX dmem_controller dcache genblk3[0] cache_offset",-1,1,0); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[0] cache_index",-1,4,0); + vcdp->declBit (c+196,"cache_simX dmem_controller dcache genblk3[0] normal_valid_in",-1); + vcdp->declBit (c+197,"cache_simX dmem_controller dcache genblk3[0] use_valid_in",-1); + vcdp->declBus (c+198,"cache_simX dmem_controller dcache genblk3[1] bank_addr",-1,31,0); + vcdp->declBus (c+199,"cache_simX dmem_controller dcache genblk3[1] byte_select",-1,1,0); + vcdp->declBus (c+200,"cache_simX dmem_controller dcache genblk3[1] cache_tag",-1,20,0); + vcdp->declBus (c+3125,"cache_simX dmem_controller dcache genblk3[1] cache_offset",-1,1,0); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[1] cache_index",-1,4,0); + vcdp->declBit (c+201,"cache_simX dmem_controller dcache genblk3[1] normal_valid_in",-1); + vcdp->declBit (c+202,"cache_simX dmem_controller dcache genblk3[1] use_valid_in",-1); + vcdp->declBus (c+203,"cache_simX dmem_controller dcache genblk3[2] bank_addr",-1,31,0); + vcdp->declBus (c+204,"cache_simX dmem_controller dcache genblk3[2] byte_select",-1,1,0); + vcdp->declBus (c+205,"cache_simX dmem_controller dcache genblk3[2] cache_tag",-1,20,0); + vcdp->declBus (c+3125,"cache_simX dmem_controller dcache genblk3[2] cache_offset",-1,1,0); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[2] cache_index",-1,4,0); + vcdp->declBit (c+206,"cache_simX dmem_controller dcache genblk3[2] normal_valid_in",-1); + vcdp->declBit (c+207,"cache_simX dmem_controller dcache genblk3[2] use_valid_in",-1); + vcdp->declBus (c+208,"cache_simX dmem_controller dcache genblk3[3] bank_addr",-1,31,0); + vcdp->declBus (c+209,"cache_simX dmem_controller dcache genblk3[3] byte_select",-1,1,0); + vcdp->declBus (c+210,"cache_simX dmem_controller dcache genblk3[3] cache_tag",-1,20,0); + vcdp->declBus (c+3125,"cache_simX dmem_controller dcache genblk3[3] cache_offset",-1,1,0); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[3] cache_index",-1,4,0); + vcdp->declBit (c+211,"cache_simX dmem_controller dcache genblk3[3] normal_valid_in",-1); + vcdp->declBit (c+212,"cache_simX dmem_controller dcache genblk3[3] use_valid_in",-1); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache multip_banks NUMBER_BANKS",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache multip_banks LOG_NUM_BANKS",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache multip_banks NUM_REQ",-1,31,0); + vcdp->declBus (c+162,"cache_simX dmem_controller dcache multip_banks i_p_valid",-1,3,0); + vcdp->declArray(c+5,"cache_simX dmem_controller dcache multip_banks i_p_addr",-1,127,0); + vcdp->declBus (c+150,"cache_simX dmem_controller dcache multip_banks thread_track_banks",-1,15,0); + vcdp->declBus (c+3096,"cache_simX dmem_controller dcache multip_banks t_id",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache get_miss_index N",-1,31,0); + vcdp->declBus (c+174,"cache_simX dmem_controller dcache get_miss_index valids",-1,3,0); + vcdp->declBus (c+175,"cache_simX dmem_controller dcache get_miss_index index",-1,1,0); + vcdp->declBit (c+176,"cache_simX dmem_controller dcache get_miss_index found",-1); + vcdp->declBus (c+213,"cache_simX dmem_controller dcache get_miss_index i",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk1[0] choose_thread N",-1,31,0); + vcdp->declBus (c+177,"cache_simX dmem_controller dcache genblk1[0] choose_thread valids",-1,3,0); + vcdp->declBus (c+214,"cache_simX dmem_controller dcache genblk1[0] choose_thread mask",-1,3,0); + vcdp->declBus (c+215,"cache_simX dmem_controller dcache genblk1[0] choose_thread index",-1,1,0); + vcdp->declBit (c+216,"cache_simX dmem_controller dcache genblk1[0] choose_thread found",-1); + vcdp->declBus (c+217,"cache_simX dmem_controller dcache genblk1[0] choose_thread i",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk1[1] choose_thread N",-1,31,0); + vcdp->declBus (c+181,"cache_simX dmem_controller dcache genblk1[1] choose_thread valids",-1,3,0); + vcdp->declBus (c+218,"cache_simX dmem_controller dcache genblk1[1] choose_thread mask",-1,3,0); + vcdp->declBus (c+219,"cache_simX dmem_controller dcache genblk1[1] choose_thread index",-1,1,0); + vcdp->declBit (c+220,"cache_simX dmem_controller dcache genblk1[1] choose_thread found",-1); + vcdp->declBus (c+221,"cache_simX dmem_controller dcache genblk1[1] choose_thread i",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk1[2] choose_thread N",-1,31,0); + vcdp->declBus (c+185,"cache_simX dmem_controller dcache genblk1[2] choose_thread valids",-1,3,0); + vcdp->declBus (c+222,"cache_simX dmem_controller dcache genblk1[2] choose_thread mask",-1,3,0); + vcdp->declBus (c+223,"cache_simX dmem_controller dcache genblk1[2] choose_thread index",-1,1,0); + vcdp->declBit (c+224,"cache_simX dmem_controller dcache genblk1[2] choose_thread found",-1); + vcdp->declBus (c+225,"cache_simX dmem_controller dcache genblk1[2] choose_thread i",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk1[3] choose_thread N",-1,31,0); + vcdp->declBus (c+189,"cache_simX dmem_controller dcache genblk1[3] choose_thread valids",-1,3,0); + vcdp->declBus (c+226,"cache_simX dmem_controller dcache genblk1[3] choose_thread mask",-1,3,0); + vcdp->declBus (c+227,"cache_simX dmem_controller dcache genblk1[3] choose_thread index",-1,1,0); + vcdp->declBit (c+228,"cache_simX dmem_controller dcache genblk1[3] choose_thread found",-1); + vcdp->declBus (c+229,"cache_simX dmem_controller dcache genblk1[3] choose_thread i",-1,31,0); + vcdp->declBus (c+3127,"cache_simX dmem_controller icache CACHE_SIZE",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller icache CACHE_WAYS",-1,31,0); + vcdp->declBus (c+3089,"cache_simX dmem_controller icache CACHE_BLOCK",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache CACHE_BANKS",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache LOG_NUM_BANKS",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache NUM_REQ",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache LOG_NUM_REQ",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller icache NUM_IND",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller icache NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller icache OFFSET_SIZE_START",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache OFFSET_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller icache TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3128,"cache_simX dmem_controller icache TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller icache IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller icache IND_SIZE_END",-1,31,0); + vcdp->declBus (c+3129,"cache_simX dmem_controller icache ADDR_TAG_START",-1,31,0); + vcdp->declBus (c+3104,"cache_simX dmem_controller icache ADDR_TAG_END",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller icache ADDR_OFFSET_START",-1,31,0); + vcdp->declBus (c+3092,"cache_simX dmem_controller icache ADDR_OFFSET_END",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller icache ADDR_IND_START",-1,31,0); + vcdp->declBus (c+3130,"cache_simX dmem_controller icache ADDR_IND_END",-1,31,0); + vcdp->declBus (c+3131,"cache_simX dmem_controller icache MEM_ADDR_REQ_MASK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller icache CACHE_IDLE",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache SEND_MEM_REQ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller icache RECIV_MEM_RSP",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller icache clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller icache rst",-1); + vcdp->declBus (c+3066,"cache_simX dmem_controller icache i_p_valid",-1,0,0); + vcdp->declBus (c+3065,"cache_simX dmem_controller icache i_p_addr",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller icache i_p_writedata",-1,31,0); + vcdp->declBit (c+3086,"cache_simX dmem_controller icache i_p_read_or_write",-1); + vcdp->declBus (c+584,"cache_simX dmem_controller icache o_p_readdata",-1,31,0); + vcdp->declBit (c+585,"cache_simX dmem_controller icache o_p_delay",-1); + vcdp->declBus (c+230,"cache_simX dmem_controller icache o_m_evict_addr",-1,31,0); + vcdp->declBus (c+726,"cache_simX dmem_controller icache o_m_read_addr",-1,31,0); + vcdp->declBit (c+727,"cache_simX dmem_controller icache o_m_valid",-1); + vcdp->declArray(c+606,"cache_simX dmem_controller icache o_m_writedata",-1,127,0); + vcdp->declBit (c+610,"cache_simX dmem_controller icache o_m_read_or_write",-1); + vcdp->declArray(c+3132,"cache_simX dmem_controller icache i_m_readdata",-1,127,0); + vcdp->declBit (c+708,"cache_simX dmem_controller icache i_m_ready",-1); + vcdp->declBus (c+23,"cache_simX dmem_controller icache i_p_mem_read",-1,2,0); + vcdp->declBus (c+3084,"cache_simX dmem_controller icache i_p_mem_write",-1,2,0); + vcdp->declBus (c+728,"cache_simX dmem_controller icache final_data_read",-1,31,0); + vcdp->declBus (c+231,"cache_simX dmem_controller icache new_final_data_read",-1,31,0); + vcdp->declBus (c+584,"cache_simX dmem_controller icache new_final_data_read_Qual",-1,31,0); + vcdp->declBus (c+729,"cache_simX dmem_controller icache global_way_to_evict",-1,0,0); + vcdp->declBus (c+232,"cache_simX dmem_controller icache thread_track_banks",-1,0,0); + vcdp->declBus (c+233,"cache_simX dmem_controller icache index_per_bank",-1,0,0); + vcdp->declBus (c+234,"cache_simX dmem_controller icache use_mask_per_bank",-1,0,0); + vcdp->declBus (c+235,"cache_simX dmem_controller icache valid_per_bank",-1,0,0); + vcdp->declBus (c+236,"cache_simX dmem_controller icache threads_serviced_per_bank",-1,0,0); + vcdp->declBus (c+237,"cache_simX dmem_controller icache readdata_per_bank",-1,31,0); + vcdp->declBus (c+238,"cache_simX dmem_controller icache hit_per_bank",-1,0,0); + vcdp->declBus (c+611,"cache_simX dmem_controller icache eviction_wb",-1,0,0); + vcdp->declBus (c+3136,"cache_simX dmem_controller icache eviction_wb_old",-1,0,0); + vcdp->declBus (c+730,"cache_simX dmem_controller icache state",-1,3,0); + vcdp->declBus (c+239,"cache_simX dmem_controller icache new_state",-1,3,0); + vcdp->declBus (c+240,"cache_simX dmem_controller icache use_valid",-1,0,0); + vcdp->declBus (c+731,"cache_simX dmem_controller icache stored_valid",-1,0,0); + vcdp->declBus (c+241,"cache_simX dmem_controller icache new_stored_valid",-1,0,0); + vcdp->declBus (c+242,"cache_simX dmem_controller icache eviction_addr_per_bank",-1,31,0); + vcdp->declBus (c+732,"cache_simX dmem_controller icache miss_addr",-1,31,0); + vcdp->declBit (c+3066,"cache_simX dmem_controller icache curr_processor_request_valid",-1); + vcdp->declBus (c+243,"cache_simX dmem_controller icache threads_serviced_Qual",-1,0,0); + {int i; for (i=0; i<1; i++) { + vcdp->declBus (c+244+i*1,"cache_simX dmem_controller icache debug_hit_per_bank_mask",(i+0),0,0);}} + // Tracing: cache_simX dmem_controller icache bid // Ignored: Verilator trace_off at ../rtl/cache/VX_d_cache.v:163 + vcdp->declBus (c+3137,"cache_simX dmem_controller icache test_bid",-1,31,0); + vcdp->declBus (c+245,"cache_simX dmem_controller icache detect_bank_miss",-1,0,0); + vcdp->declBus (c+3137,"cache_simX dmem_controller icache bbid",-1,31,0); + // Tracing: cache_simX dmem_controller icache tid // Ignored: Verilator trace_off at ../rtl/cache/VX_d_cache.v:209 + vcdp->declBit (c+585,"cache_simX dmem_controller icache delay",-1); + vcdp->declBus (c+233,"cache_simX dmem_controller icache send_index_to_bank",-1,0,0); + vcdp->declBus (c+246,"cache_simX dmem_controller icache miss_bank_index",-1,0,0); + vcdp->declBit (c+247,"cache_simX dmem_controller icache miss_found",-1); + vcdp->declBit (c+612,"cache_simX dmem_controller icache update_global_way_to_evict",-1); + // Tracing: cache_simX dmem_controller icache cur_t // Ignored: Verilator trace_off at ../rtl/cache/VX_d_cache.v:249 + vcdp->declBus (c+3138,"cache_simX dmem_controller icache init_b",-1,31,0); + // Tracing: cache_simX dmem_controller icache bank_id // Ignored: Verilator trace_off at ../rtl/cache/VX_d_cache.v:294 + vcdp->declBus (c+232,"cache_simX dmem_controller icache genblk1[0] use_threads_track_banks",-1,0,0); + vcdp->declBus (c+233,"cache_simX dmem_controller icache genblk1[0] use_thread_index",-1,0,0); + vcdp->declBit (c+248,"cache_simX dmem_controller icache genblk1[0] use_write_final_data",-1); + vcdp->declBus (c+237,"cache_simX dmem_controller icache genblk1[0] use_data_final_data",-1,31,0); + vcdp->declBus (c+249,"cache_simX dmem_controller icache genblk3[0] bank_addr",-1,31,0); + vcdp->declBus (c+250,"cache_simX dmem_controller icache genblk3[0] byte_select",-1,1,0); + vcdp->declBus (c+251,"cache_simX dmem_controller icache genblk3[0] cache_tag",-1,22,0); + vcdp->declBus (c+3125,"cache_simX dmem_controller icache genblk3[0] cache_offset",-1,1,0); + vcdp->declBus (c+3126,"cache_simX dmem_controller icache genblk3[0] cache_index",-1,4,0); + vcdp->declBit (c+252,"cache_simX dmem_controller icache genblk3[0] normal_valid_in",-1); + vcdp->declBit (c+253,"cache_simX dmem_controller icache genblk3[0] use_valid_in",-1); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache multip_banks NUMBER_BANKS",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache multip_banks LOG_NUM_BANKS",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache multip_banks NUM_REQ",-1,31,0); + vcdp->declBus (c+240,"cache_simX dmem_controller icache multip_banks i_p_valid",-1,0,0); + vcdp->declBus (c+3065,"cache_simX dmem_controller icache multip_banks i_p_addr",-1,31,0); + vcdp->declBus (c+232,"cache_simX dmem_controller icache multip_banks thread_track_banks",-1,0,0); + vcdp->declBus (c+3137,"cache_simX dmem_controller icache multip_banks t_id",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache get_miss_index N",-1,31,0); + vcdp->declBus (c+245,"cache_simX dmem_controller icache get_miss_index valids",-1,0,0); + vcdp->declBus (c+246,"cache_simX dmem_controller icache get_miss_index index",-1,0,0); + vcdp->declBit (c+247,"cache_simX dmem_controller icache get_miss_index found",-1); + vcdp->declBus (c+3097,"cache_simX dmem_controller icache get_miss_index i",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache genblk1[0] choose_thread N",-1,31,0); + vcdp->declBus (c+232,"cache_simX dmem_controller icache genblk1[0] choose_thread valids",-1,0,0); + vcdp->declBus (c+234,"cache_simX dmem_controller icache genblk1[0] choose_thread mask",-1,0,0); + vcdp->declBus (c+233,"cache_simX dmem_controller icache genblk1[0] choose_thread index",-1,0,0); + vcdp->declBit (c+235,"cache_simX dmem_controller icache genblk1[0] choose_thread found",-1); + vcdp->declBus (c+3137,"cache_simX dmem_controller icache genblk1[0] choose_thread i",-1,31,0); + vcdp->declBus (c+3127,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_SIZE",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_WAYS",-1,31,0); + vcdp->declBus (c+3089,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_BLOCK",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_BANKS",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache genblk3[0] bank_structure LOG_NUM_BANKS",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache genblk3[0] bank_structure NUM_REQ",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache genblk3[0] bank_structure LOG_NUM_REQ",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller icache genblk3[0] bank_structure NUM_IND",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure OFFSET_SIZE_START",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache genblk3[0] bank_structure OFFSET_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3128,"cache_simX dmem_controller icache genblk3[0] bank_structure TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure IND_SIZE_END",-1,31,0); + vcdp->declBus (c+3129,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_TAG_START",-1,31,0); + vcdp->declBus (c+3104,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_TAG_END",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_OFFSET_START",-1,31,0); + vcdp->declBus (c+3092,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_OFFSET_END",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_IND_START",-1,31,0); + vcdp->declBus (c+3130,"cache_simX dmem_controller icache genblk3[0] bank_structure ADDR_IND_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure CACHE_IDLE",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache genblk3[0] bank_structure SEND_MEM_REQ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller icache genblk3[0] bank_structure RECIV_MEM_RSP",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure BLOCK_NUM_BITS",-1,31,0); + vcdp->declBit (c+3064,"cache_simX dmem_controller icache genblk3[0] bank_structure rst",-1); + vcdp->declBit (c+3063,"cache_simX dmem_controller icache genblk3[0] bank_structure clk",-1); + vcdp->declBus (c+730,"cache_simX dmem_controller icache genblk3[0] bank_structure state",-1,3,0); + vcdp->declBus (c+3126,"cache_simX dmem_controller icache genblk3[0] bank_structure actual_index",-1,4,0); + vcdp->declBus (c+251,"cache_simX dmem_controller icache genblk3[0] bank_structure o_tag",-1,22,0); + vcdp->declBus (c+3125,"cache_simX dmem_controller icache genblk3[0] bank_structure block_offset",-1,1,0); + vcdp->declBus (c+254,"cache_simX dmem_controller icache genblk3[0] bank_structure writedata",-1,31,0); + vcdp->declBit (c+253,"cache_simX dmem_controller icache genblk3[0] bank_structure valid_in",-1); + vcdp->declBit (c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure read_or_write",-1); + vcdp->declArray(c+3132,"cache_simX dmem_controller icache genblk3[0] bank_structure fetched_writedata",-1,127,0); + vcdp->declBus (c+23,"cache_simX dmem_controller icache genblk3[0] bank_structure i_p_mem_read",-1,2,0); + vcdp->declBus (c+3084,"cache_simX dmem_controller icache genblk3[0] bank_structure i_p_mem_write",-1,2,0); + vcdp->declBus (c+250,"cache_simX dmem_controller icache genblk3[0] bank_structure byte_select",-1,1,0); + vcdp->declBus (c+729,"cache_simX dmem_controller icache genblk3[0] bank_structure evicted_way",-1,0,0); + vcdp->declBus (c+237,"cache_simX dmem_controller icache genblk3[0] bank_structure readdata",-1,31,0); + vcdp->declBit (c+238,"cache_simX dmem_controller icache genblk3[0] bank_structure hit",-1); + vcdp->declBit (c+611,"cache_simX dmem_controller icache genblk3[0] bank_structure eviction_wb",-1); + vcdp->declBus (c+242,"cache_simX dmem_controller icache genblk3[0] bank_structure eviction_addr",-1,31,0); + vcdp->declArray(c+606,"cache_simX dmem_controller icache genblk3[0] bank_structure data_evicted",-1,127,0); + vcdp->declArray(c+606,"cache_simX dmem_controller icache genblk3[0] bank_structure data_use",-1,127,0); + vcdp->declBus (c+255,"cache_simX dmem_controller icache genblk3[0] bank_structure tag_use",-1,22,0); + vcdp->declBus (c+255,"cache_simX dmem_controller icache genblk3[0] bank_structure eviction_tag",-1,22,0); + vcdp->declBit (c+256,"cache_simX dmem_controller icache genblk3[0] bank_structure valid_use",-1); + vcdp->declBit (c+611,"cache_simX dmem_controller icache genblk3[0] bank_structure dirty_use",-1); + vcdp->declBit (c+257,"cache_simX dmem_controller icache genblk3[0] bank_structure access",-1); + vcdp->declBit (c+258,"cache_simX dmem_controller icache genblk3[0] bank_structure write_from_mem",-1); + vcdp->declBit (c+259,"cache_simX dmem_controller icache genblk3[0] bank_structure miss",-1); + vcdp->declBus (c+628,"cache_simX dmem_controller icache genblk3[0] bank_structure way_to_update",-1,0,0); + vcdp->declBit (c+260,"cache_simX dmem_controller icache genblk3[0] bank_structure lw",-1); + vcdp->declBit (c+261,"cache_simX dmem_controller icache genblk3[0] bank_structure lb",-1); + vcdp->declBit (c+262,"cache_simX dmem_controller icache genblk3[0] bank_structure lh",-1); + vcdp->declBit (c+263,"cache_simX dmem_controller icache genblk3[0] bank_structure lhu",-1); + vcdp->declBit (c+264,"cache_simX dmem_controller icache genblk3[0] bank_structure lbu",-1); + vcdp->declBit (c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure sw",-1); + vcdp->declBit (c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure sb",-1); + vcdp->declBit (c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure sh",-1); + vcdp->declBit (c+265,"cache_simX dmem_controller icache genblk3[0] bank_structure b0",-1); + vcdp->declBit (c+266,"cache_simX dmem_controller icache genblk3[0] bank_structure b1",-1); + vcdp->declBit (c+267,"cache_simX dmem_controller icache genblk3[0] bank_structure b2",-1); + vcdp->declBit (c+268,"cache_simX dmem_controller icache genblk3[0] bank_structure b3",-1); + vcdp->declBus (c+269,"cache_simX dmem_controller icache genblk3[0] bank_structure data_unQual",-1,31,0); + vcdp->declBus (c+270,"cache_simX dmem_controller icache genblk3[0] bank_structure lb_data",-1,31,0); + vcdp->declBus (c+271,"cache_simX dmem_controller icache genblk3[0] bank_structure lh_data",-1,31,0); + vcdp->declBus (c+272,"cache_simX dmem_controller icache genblk3[0] bank_structure lbu_data",-1,31,0); + vcdp->declBus (c+273,"cache_simX dmem_controller icache genblk3[0] bank_structure lhu_data",-1,31,0); + vcdp->declBus (c+269,"cache_simX dmem_controller icache genblk3[0] bank_structure lw_data",-1,31,0); + vcdp->declBus (c+254,"cache_simX dmem_controller icache genblk3[0] bank_structure sw_data",-1,31,0); + vcdp->declBus (c+274,"cache_simX dmem_controller icache genblk3[0] bank_structure sb_data",-1,31,0); + vcdp->declBus (c+275,"cache_simX dmem_controller icache genblk3[0] bank_structure sh_data",-1,31,0); + vcdp->declBus (c+254,"cache_simX dmem_controller icache genblk3[0] bank_structure use_write_data",-1,31,0); + vcdp->declBus (c+276,"cache_simX dmem_controller icache genblk3[0] bank_structure data_Qual",-1,31,0); + vcdp->declBus (c+277,"cache_simX dmem_controller icache genblk3[0] bank_structure sb_mask",-1,3,0); + vcdp->declBus (c+278,"cache_simX dmem_controller icache genblk3[0] bank_structure sh_mask",-1,3,0); + vcdp->declBus (c+279,"cache_simX dmem_controller icache genblk3[0] bank_structure we",-1,15,0); + vcdp->declArray(c+280,"cache_simX dmem_controller icache genblk3[0] bank_structure data_write",-1,127,0); + // Tracing: cache_simX dmem_controller icache genblk3[0] bank_structure g // Ignored: Verilator trace_off at ../rtl/cache/VX_Cache_Bank.v:203 + vcdp->declBit (c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure genblk1[0] normal_write",-1); + vcdp->declBit (c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure genblk1[1] normal_write",-1); + vcdp->declBit (c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure genblk1[2] normal_write",-1); + vcdp->declBit (c+3086,"cache_simX dmem_controller icache genblk3[0] bank_structure genblk1[3] normal_write",-1); + vcdp->declBus (c+3090,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures CACHE_WAYS",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures NUM_IND",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3128,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures rst",-1); + vcdp->declBit (c+253,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures valid_in",-1); + vcdp->declBus (c+730,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures state",-1,3,0); + vcdp->declBus (c+3126,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures addr",-1,4,0); + vcdp->declBus (c+279,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures we",-1,15,0); + vcdp->declBit (c+258,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures evict",-1); + vcdp->declBus (c+628,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures way_to_update",-1,0,0); + vcdp->declArray(c+280,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures data_write",-1,127,0); + vcdp->declBus (c+251,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures tag_write",-1,22,0); + vcdp->declBus (c+255,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures tag_use",-1,22,0); + vcdp->declArray(c+606,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures data_use",-1,127,0); + vcdp->declBit (c+256,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures valid_use",-1); + vcdp->declBit (c+611,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures dirty_use",-1); + vcdp->declQuad (c+629,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures tag_use_per_way",-1,45,0); + vcdp->declArray(c+631,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures data_use_per_way",-1,255,0); + vcdp->declBus (c+639,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures valid_use_per_way",-1,1,0); + vcdp->declBus (c+640,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures dirty_use_per_way",-1,1,0); + vcdp->declBus (c+284,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures hit_per_way",-1,1,0); + vcdp->declBus (c+285,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures we_per_way",-1,31,0); + vcdp->declArray(c+286,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures data_write_per_way",-1,255,0); + vcdp->declBus (c+294,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures write_from_mem_per_way",-1,1,0); + vcdp->declBit (c+641,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures invalid_found",-1); + vcdp->declBus (c+295,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures way_index",-1,0,0); + vcdp->declBus (c+642,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures invalid_index",-1,0,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures CACHE_IDLE",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures SEND_MEM_REQ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures RECIV_MEM_RSP",-1,31,0); + vcdp->declBus (c+296,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures way_use_Qual",-1,0,0); + // Tracing: cache_simX dmem_controller icache genblk3[0] bank_structure data_structures ways // Ignored: Verilator trace_off at ../rtl/cache/VX_cache_data_per_index.v:107 + vcdp->declBus (c+3090,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index N",-1,31,0); + vcdp->declBus (c+643,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index valids",-1,1,0); + vcdp->declBus (c+642,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index index",-1,0,0); + vcdp->declBit (c+641,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index found",-1); + vcdp->declBus (c+3097,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 valid_index i",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing N",-1,31,0); + vcdp->declBus (c+284,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing valids",-1,1,0); + vcdp->declBus (c+295,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing index",-1,0,0); + vcdp->declBit (c+297,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing found",-1); + vcdp->declBus (c+3097,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures genblk1 way_indexing i",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3128,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures rst",-1); + vcdp->declBus (c+3126,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures addr",-1,4,0); + vcdp->declBus (c+298,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures we",-1,15,0); + vcdp->declBit (c+299,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures evict",-1); + vcdp->declArray(c+300,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0); + vcdp->declBus (c+251,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures tag_write",-1,22,0); + vcdp->declBus (c+733,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures tag_use",-1,22,0); + vcdp->declArray(c+734,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0); + vcdp->declBit (c+738,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures valid_use",-1); + vcdp->declBit (c+739,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures dirty_use",-1); + vcdp->declBit (c+304,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures currently_writing",-1); + vcdp->declBit (c+613,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures update_dirty",-1); + vcdp->declBit (c+305,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures dirt_new",-1); + vcdp->declArray(c+740,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0); + vcdp->declArray(c+744,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0); + vcdp->declArray(c+748,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0); + vcdp->declArray(c+752,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0); + vcdp->declArray(c+756,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0); + vcdp->declArray(c+760,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0); + vcdp->declArray(c+764,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0); + vcdp->declArray(c+768,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0); + vcdp->declArray(c+772,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0); + vcdp->declArray(c+776,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0); + vcdp->declArray(c+780,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0); + vcdp->declArray(c+784,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0); + vcdp->declArray(c+788,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0); + vcdp->declArray(c+792,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0); + vcdp->declArray(c+796,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0); + vcdp->declArray(c+800,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0); + vcdp->declArray(c+804,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0); + vcdp->declArray(c+808,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0); + vcdp->declArray(c+812,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0); + vcdp->declArray(c+816,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0); + vcdp->declArray(c+820,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0); + vcdp->declArray(c+824,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0); + vcdp->declArray(c+828,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0); + vcdp->declArray(c+832,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0); + vcdp->declArray(c+836,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0); + vcdp->declArray(c+840,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0); + vcdp->declArray(c+844,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0); + vcdp->declArray(c+848,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0); + vcdp->declArray(c+852,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0); + vcdp->declArray(c+856,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0); + vcdp->declArray(c+860,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0); + vcdp->declArray(c+864,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus (c+868+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures tag",(i+0),22,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+900+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+932+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}} + vcdp->declBus (c+964,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures f",-1,31,0); + vcdp->declBus (c+965,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3128,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures rst",-1); + vcdp->declBus (c+3126,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures addr",-1,4,0); + vcdp->declBus (c+306,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures we",-1,15,0); + vcdp->declBit (c+307,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures evict",-1); + vcdp->declArray(c+308,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0); + vcdp->declBus (c+251,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures tag_write",-1,22,0); + vcdp->declBus (c+966,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures tag_use",-1,22,0); + vcdp->declArray(c+967,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0); + vcdp->declBit (c+971,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures valid_use",-1); + vcdp->declBit (c+972,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures dirty_use",-1); + vcdp->declBit (c+312,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures currently_writing",-1); + vcdp->declBit (c+614,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures update_dirty",-1); + vcdp->declBit (c+313,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures dirt_new",-1); + vcdp->declArray(c+973,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0); + vcdp->declArray(c+977,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0); + vcdp->declArray(c+981,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0); + vcdp->declArray(c+985,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0); + vcdp->declArray(c+989,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0); + vcdp->declArray(c+993,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0); + vcdp->declArray(c+997,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0); + vcdp->declArray(c+1001,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0); + vcdp->declArray(c+1005,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0); + vcdp->declArray(c+1009,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0); + vcdp->declArray(c+1013,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0); + vcdp->declArray(c+1017,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0); + vcdp->declArray(c+1021,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0); + vcdp->declArray(c+1025,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0); + vcdp->declArray(c+1029,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0); + vcdp->declArray(c+1033,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0); + vcdp->declArray(c+1037,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0); + vcdp->declArray(c+1041,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0); + vcdp->declArray(c+1045,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0); + vcdp->declArray(c+1049,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0); + vcdp->declArray(c+1053,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0); + vcdp->declArray(c+1057,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0); + vcdp->declArray(c+1061,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0); + vcdp->declArray(c+1065,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0); + vcdp->declArray(c+1069,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0); + vcdp->declArray(c+1073,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0); + vcdp->declArray(c+1077,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0); + vcdp->declArray(c+1081,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0); + vcdp->declArray(c+1085,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0); + vcdp->declArray(c+1089,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0); + vcdp->declArray(c+1093,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0); + vcdp->declArray(c+1097,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus (c+1101+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures tag",(i+0),22,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+1133+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+1165+i*1,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}} + vcdp->declBus (c+1197,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures f",-1,31,0); + vcdp->declBus (c+1198,"cache_simX dmem_controller icache genblk3[0] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0); + vcdp->declBus (c+3065,"cache_simX VX_icache_req pc_address",-1,31,0); + vcdp->declBus (c+3079,"cache_simX VX_icache_req out_cache_driver_in_mem_read",-1,2,0); + vcdp->declBus (c+3084,"cache_simX VX_icache_req out_cache_driver_in_mem_write",-1,2,0); + vcdp->declBit (c+3066,"cache_simX VX_icache_req out_cache_driver_in_valid",-1); + vcdp->declBus (c+3085,"cache_simX VX_icache_req out_cache_driver_in_data",-1,31,0); + vcdp->declBus (c+584,"cache_simX VX_icache_rsp instruction",-1,31,0); + vcdp->declBit (c+585,"cache_simX VX_icache_rsp delay",-1); + vcdp->declBus (c+3088,"cache_simX VX_dram_req_rsp NUMBER_BANKS",-1,31,0); + vcdp->declBus (c+3088,"cache_simX VX_dram_req_rsp NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+129,"cache_simX VX_dram_req_rsp o_m_evict_addr",-1,31,0); + vcdp->declBus (c+716,"cache_simX VX_dram_req_rsp o_m_read_addr",-1,31,0); + vcdp->declBit (c+717,"cache_simX VX_dram_req_rsp o_m_valid",-1); + vcdp->declArray(c+130,"cache_simX VX_dram_req_rsp o_m_writedata",-1,511,0); + vcdp->declBit (c+604,"cache_simX VX_dram_req_rsp o_m_read_or_write",-1); + vcdp->declArray(c+3107,"cache_simX VX_dram_req_rsp i_m_readdata",-1,511,0); + vcdp->declBit (c+709,"cache_simX VX_dram_req_rsp i_m_ready",-1); + vcdp->declBus (c+3101,"cache_simX VX_dram_req_rsp_icache NUMBER_BANKS",-1,31,0); + vcdp->declBus (c+3088,"cache_simX VX_dram_req_rsp_icache NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+230,"cache_simX VX_dram_req_rsp_icache o_m_evict_addr",-1,31,0); + vcdp->declBus (c+726,"cache_simX VX_dram_req_rsp_icache o_m_read_addr",-1,31,0); + vcdp->declBit (c+727,"cache_simX VX_dram_req_rsp_icache o_m_valid",-1); + vcdp->declArray(c+606,"cache_simX VX_dram_req_rsp_icache o_m_writedata",-1,127,0); + vcdp->declBit (c+610,"cache_simX VX_dram_req_rsp_icache o_m_read_or_write",-1); + vcdp->declArray(c+3132,"cache_simX VX_dram_req_rsp_icache i_m_readdata",-1,127,0); + vcdp->declBit (c+708,"cache_simX VX_dram_req_rsp_icache i_m_ready",-1); + vcdp->declArray(c+5,"cache_simX VX_dcache_req out_cache_driver_in_address",-1,127,0); + vcdp->declBus (c+3068,"cache_simX VX_dcache_req out_cache_driver_in_mem_read",-1,2,0); + vcdp->declBus (c+3069,"cache_simX VX_dcache_req out_cache_driver_in_mem_write",-1,2,0); + vcdp->declBus (c+314,"cache_simX VX_dcache_req out_cache_driver_in_valid",-1,3,0); + vcdp->declArray(c+3080,"cache_simX VX_dcache_req out_cache_driver_in_data",-1,127,0); + vcdp->declArray(c+315,"cache_simX VX_dcache_rsp in_cache_driver_out_data",-1,127,0); + vcdp->declBit (c+615,"cache_simX VX_dcache_rsp delay",-1); + vcdp->declBus (c+3098,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_SIZE",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_WAYS",-1,31,0); + vcdp->declBus (c+3099,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_BLOCK",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_BANKS",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[0] bank_structure LOG_NUM_BANKS",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure NUM_REQ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[0] bank_structure LOG_NUM_REQ",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller dcache genblk3[0] bank_structure NUM_IND",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure OFFSET_SIZE_START",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[0] bank_structure OFFSET_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3102,"cache_simX dmem_controller dcache genblk3[0] bank_structure TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure IND_SIZE_END",-1,31,0); + vcdp->declBus (c+3103,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_TAG_START",-1,31,0); + vcdp->declBus (c+3104,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_TAG_END",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_OFFSET_START",-1,31,0); + vcdp->declBus (c+3093,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_OFFSET_END",-1,31,0); + vcdp->declBus (c+3094,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_IND_START",-1,31,0); + vcdp->declBus (c+3105,"cache_simX dmem_controller dcache genblk3[0] bank_structure ADDR_IND_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure CACHE_IDLE",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[0] bank_structure SEND_MEM_REQ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[0] bank_structure RECIV_MEM_RSP",-1,31,0); + vcdp->declBus (c+3094,"cache_simX dmem_controller dcache genblk3[0] bank_structure BLOCK_NUM_BITS",-1,31,0); + vcdp->declBit (c+3064,"cache_simX dmem_controller dcache genblk3[0] bank_structure rst",-1); + vcdp->declBit (c+3063,"cache_simX dmem_controller dcache genblk3[0] bank_structure clk",-1); + vcdp->declBus (c+723,"cache_simX dmem_controller dcache genblk3[0] bank_structure state",-1,3,0); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[0] bank_structure actual_index",-1,4,0); + vcdp->declBus (c+195,"cache_simX dmem_controller dcache genblk3[0] bank_structure o_tag",-1,20,0); + vcdp->declBus (c+3125,"cache_simX dmem_controller dcache genblk3[0] bank_structure block_offset",-1,1,0); + vcdp->declBus (c+319,"cache_simX dmem_controller dcache genblk3[0] bank_structure writedata",-1,31,0); + vcdp->declBit (c+197,"cache_simX dmem_controller dcache genblk3[0] bank_structure valid_in",-1); + vcdp->declBit (c+4,"cache_simX dmem_controller dcache genblk3[0] bank_structure read_or_write",-1); + vcdp->declArray(c+3139,"cache_simX dmem_controller dcache genblk3[0] bank_structure fetched_writedata",-1,127,0); + vcdp->declBus (c+9,"cache_simX dmem_controller dcache genblk3[0] bank_structure i_p_mem_read",-1,2,0); + vcdp->declBus (c+10,"cache_simX dmem_controller dcache genblk3[0] bank_structure i_p_mem_write",-1,2,0); + vcdp->declBus (c+194,"cache_simX dmem_controller dcache genblk3[0] bank_structure byte_select",-1,1,0); + vcdp->declBus (c+722,"cache_simX dmem_controller dcache genblk3[0] bank_structure evicted_way",-1,0,0); + vcdp->declBus (c+320,"cache_simX dmem_controller dcache genblk3[0] bank_structure readdata",-1,31,0); + vcdp->declBit (c+321,"cache_simX dmem_controller dcache genblk3[0] bank_structure hit",-1); + vcdp->declBit (c+616,"cache_simX dmem_controller dcache genblk3[0] bank_structure eviction_wb",-1); + vcdp->declBus (c+322,"cache_simX dmem_controller dcache genblk3[0] bank_structure eviction_addr",-1,31,0); + vcdp->declArray(c+323,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_evicted",-1,127,0); + vcdp->declArray(c+323,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_use",-1,127,0); + vcdp->declBus (c+327,"cache_simX dmem_controller dcache genblk3[0] bank_structure tag_use",-1,20,0); + vcdp->declBus (c+327,"cache_simX dmem_controller dcache genblk3[0] bank_structure eviction_tag",-1,20,0); + vcdp->declBit (c+328,"cache_simX dmem_controller dcache genblk3[0] bank_structure valid_use",-1); + vcdp->declBit (c+616,"cache_simX dmem_controller dcache genblk3[0] bank_structure dirty_use",-1); + vcdp->declBit (c+329,"cache_simX dmem_controller dcache genblk3[0] bank_structure access",-1); + vcdp->declBit (c+330,"cache_simX dmem_controller dcache genblk3[0] bank_structure write_from_mem",-1); + vcdp->declBit (c+331,"cache_simX dmem_controller dcache genblk3[0] bank_structure miss",-1); + vcdp->declBus (c+644,"cache_simX dmem_controller dcache genblk3[0] bank_structure way_to_update",-1,0,0); + vcdp->declBit (c+332,"cache_simX dmem_controller dcache genblk3[0] bank_structure lw",-1); + vcdp->declBit (c+333,"cache_simX dmem_controller dcache genblk3[0] bank_structure lb",-1); + vcdp->declBit (c+334,"cache_simX dmem_controller dcache genblk3[0] bank_structure lh",-1); + vcdp->declBit (c+335,"cache_simX dmem_controller dcache genblk3[0] bank_structure lhu",-1); + vcdp->declBit (c+336,"cache_simX dmem_controller dcache genblk3[0] bank_structure lbu",-1); + vcdp->declBit (c+337,"cache_simX dmem_controller dcache genblk3[0] bank_structure sw",-1); + vcdp->declBit (c+338,"cache_simX dmem_controller dcache genblk3[0] bank_structure sb",-1); + vcdp->declBit (c+339,"cache_simX dmem_controller dcache genblk3[0] bank_structure sh",-1); + vcdp->declBit (c+340,"cache_simX dmem_controller dcache genblk3[0] bank_structure b0",-1); + vcdp->declBit (c+341,"cache_simX dmem_controller dcache genblk3[0] bank_structure b1",-1); + vcdp->declBit (c+342,"cache_simX dmem_controller dcache genblk3[0] bank_structure b2",-1); + vcdp->declBit (c+343,"cache_simX dmem_controller dcache genblk3[0] bank_structure b3",-1); + vcdp->declBus (c+344,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_unQual",-1,31,0); + vcdp->declBus (c+345,"cache_simX dmem_controller dcache genblk3[0] bank_structure lb_data",-1,31,0); + vcdp->declBus (c+346,"cache_simX dmem_controller dcache genblk3[0] bank_structure lh_data",-1,31,0); + vcdp->declBus (c+347,"cache_simX dmem_controller dcache genblk3[0] bank_structure lbu_data",-1,31,0); + vcdp->declBus (c+348,"cache_simX dmem_controller dcache genblk3[0] bank_structure lhu_data",-1,31,0); + vcdp->declBus (c+344,"cache_simX dmem_controller dcache genblk3[0] bank_structure lw_data",-1,31,0); + vcdp->declBus (c+319,"cache_simX dmem_controller dcache genblk3[0] bank_structure sw_data",-1,31,0); + vcdp->declBus (c+349,"cache_simX dmem_controller dcache genblk3[0] bank_structure sb_data",-1,31,0); + vcdp->declBus (c+350,"cache_simX dmem_controller dcache genblk3[0] bank_structure sh_data",-1,31,0); + vcdp->declBus (c+351,"cache_simX dmem_controller dcache genblk3[0] bank_structure use_write_data",-1,31,0); + vcdp->declBus (c+352,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_Qual",-1,31,0); + vcdp->declBus (c+353,"cache_simX dmem_controller dcache genblk3[0] bank_structure sb_mask",-1,3,0); + vcdp->declBus (c+354,"cache_simX dmem_controller dcache genblk3[0] bank_structure sh_mask",-1,3,0); + vcdp->declBus (c+355,"cache_simX dmem_controller dcache genblk3[0] bank_structure we",-1,15,0); + vcdp->declArray(c+356,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_write",-1,127,0); + // Tracing: cache_simX dmem_controller dcache genblk3[0] bank_structure g // Ignored: Verilator trace_off at ../rtl/cache/VX_Cache_Bank.v:203 + vcdp->declBit (c+360,"cache_simX dmem_controller dcache genblk3[0] bank_structure genblk1[0] normal_write",-1); + vcdp->declBit (c+3086,"cache_simX dmem_controller dcache genblk3[0] bank_structure genblk1[1] normal_write",-1); + vcdp->declBit (c+3086,"cache_simX dmem_controller dcache genblk3[0] bank_structure genblk1[2] normal_write",-1); + vcdp->declBit (c+3086,"cache_simX dmem_controller dcache genblk3[0] bank_structure genblk1[3] normal_write",-1); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures CACHE_WAYS",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures NUM_IND",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3102,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures rst",-1); + vcdp->declBit (c+197,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures valid_in",-1); + vcdp->declBus (c+723,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures state",-1,3,0); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures addr",-1,4,0); + vcdp->declBus (c+355,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures we",-1,15,0); + vcdp->declBit (c+330,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures evict",-1); + vcdp->declBus (c+644,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures way_to_update",-1,0,0); + vcdp->declArray(c+356,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures data_write",-1,127,0); + vcdp->declBus (c+195,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures tag_write",-1,20,0); + vcdp->declBus (c+327,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures tag_use",-1,20,0); + vcdp->declArray(c+323,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures data_use",-1,127,0); + vcdp->declBit (c+328,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures valid_use",-1); + vcdp->declBit (c+616,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures dirty_use",-1); + vcdp->declQuad (c+645,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures tag_use_per_way",-1,41,0); + vcdp->declArray(c+647,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures data_use_per_way",-1,255,0); + vcdp->declBus (c+655,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures valid_use_per_way",-1,1,0); + vcdp->declBus (c+656,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures dirty_use_per_way",-1,1,0); + vcdp->declBus (c+361,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures hit_per_way",-1,1,0); + vcdp->declBus (c+362,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures we_per_way",-1,31,0); + vcdp->declArray(c+363,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures data_write_per_way",-1,255,0); + vcdp->declBus (c+371,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures write_from_mem_per_way",-1,1,0); + vcdp->declBit (c+657,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures invalid_found",-1); + vcdp->declBus (c+372,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures way_index",-1,0,0); + vcdp->declBus (c+658,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures invalid_index",-1,0,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures CACHE_IDLE",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures SEND_MEM_REQ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures RECIV_MEM_RSP",-1,31,0); + vcdp->declBus (c+373,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures way_use_Qual",-1,0,0); + // Tracing: cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures ways // Ignored: Verilator trace_off at ../rtl/cache/VX_cache_data_per_index.v:107 + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index N",-1,31,0); + vcdp->declBus (c+659,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index valids",-1,1,0); + vcdp->declBus (c+658,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index index",-1,0,0); + vcdp->declBit (c+657,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index found",-1); + vcdp->declBus (c+3097,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 valid_index i",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing N",-1,31,0); + vcdp->declBus (c+361,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing valids",-1,1,0); + vcdp->declBus (c+372,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing index",-1,0,0); + vcdp->declBit (c+374,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing found",-1); + vcdp->declBus (c+3097,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures genblk1 way_indexing i",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3102,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures rst",-1); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures addr",-1,4,0); + vcdp->declBus (c+375,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures we",-1,15,0); + vcdp->declBit (c+376,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures evict",-1); + vcdp->declArray(c+377,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0); + vcdp->declBus (c+195,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures tag_write",-1,20,0); + vcdp->declBus (c+1199,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0); + vcdp->declArray(c+1200,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0); + vcdp->declBit (c+1204,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures valid_use",-1); + vcdp->declBit (c+1205,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures dirty_use",-1); + vcdp->declBit (c+381,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures currently_writing",-1); + vcdp->declBit (c+617,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures update_dirty",-1); + vcdp->declBit (c+382,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures dirt_new",-1); + vcdp->declArray(c+1206,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0); + vcdp->declArray(c+1210,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0); + vcdp->declArray(c+1214,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0); + vcdp->declArray(c+1218,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0); + vcdp->declArray(c+1222,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0); + vcdp->declArray(c+1226,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0); + vcdp->declArray(c+1230,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0); + vcdp->declArray(c+1234,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0); + vcdp->declArray(c+1238,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0); + vcdp->declArray(c+1242,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0); + vcdp->declArray(c+1246,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0); + vcdp->declArray(c+1250,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0); + vcdp->declArray(c+1254,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0); + vcdp->declArray(c+1258,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0); + vcdp->declArray(c+1262,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0); + vcdp->declArray(c+1266,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0); + vcdp->declArray(c+1270,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0); + vcdp->declArray(c+1274,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0); + vcdp->declArray(c+1278,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0); + vcdp->declArray(c+1282,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0); + vcdp->declArray(c+1286,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0); + vcdp->declArray(c+1290,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0); + vcdp->declArray(c+1294,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0); + vcdp->declArray(c+1298,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0); + vcdp->declArray(c+1302,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0); + vcdp->declArray(c+1306,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0); + vcdp->declArray(c+1310,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0); + vcdp->declArray(c+1314,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0); + vcdp->declArray(c+1318,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0); + vcdp->declArray(c+1322,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0); + vcdp->declArray(c+1326,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0); + vcdp->declArray(c+1330,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus (c+1334+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+1366+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+1398+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}} + vcdp->declBus (c+1430,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures f",-1,31,0); + vcdp->declBus (c+1431,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3102,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures rst",-1); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures addr",-1,4,0); + vcdp->declBus (c+383,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures we",-1,15,0); + vcdp->declBit (c+384,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures evict",-1); + vcdp->declArray(c+385,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0); + vcdp->declBus (c+195,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures tag_write",-1,20,0); + vcdp->declBus (c+1432,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0); + vcdp->declArray(c+1433,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0); + vcdp->declBit (c+1437,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures valid_use",-1); + vcdp->declBit (c+1438,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures dirty_use",-1); + vcdp->declBit (c+389,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures currently_writing",-1); + vcdp->declBit (c+618,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures update_dirty",-1); + vcdp->declBit (c+390,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures dirt_new",-1); + vcdp->declArray(c+1439,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0); + vcdp->declArray(c+1443,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0); + vcdp->declArray(c+1447,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0); + vcdp->declArray(c+1451,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0); + vcdp->declArray(c+1455,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0); + vcdp->declArray(c+1459,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0); + vcdp->declArray(c+1463,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0); + vcdp->declArray(c+1467,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0); + vcdp->declArray(c+1471,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0); + vcdp->declArray(c+1475,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0); + vcdp->declArray(c+1479,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0); + vcdp->declArray(c+1483,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0); + vcdp->declArray(c+1487,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0); + vcdp->declArray(c+1491,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0); + vcdp->declArray(c+1495,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0); + vcdp->declArray(c+1499,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0); + vcdp->declArray(c+1503,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0); + vcdp->declArray(c+1507,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0); + vcdp->declArray(c+1511,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0); + vcdp->declArray(c+1515,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0); + vcdp->declArray(c+1519,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0); + vcdp->declArray(c+1523,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0); + vcdp->declArray(c+1527,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0); + vcdp->declArray(c+1531,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0); + vcdp->declArray(c+1535,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0); + vcdp->declArray(c+1539,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0); + vcdp->declArray(c+1543,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0); + vcdp->declArray(c+1547,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0); + vcdp->declArray(c+1551,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0); + vcdp->declArray(c+1555,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0); + vcdp->declArray(c+1559,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0); + vcdp->declArray(c+1563,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus (c+1567+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+1599+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+1631+i*1,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}} + vcdp->declBus (c+1663,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures f",-1,31,0); + vcdp->declBus (c+1664,"cache_simX dmem_controller dcache genblk3[0] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0); + vcdp->declBus (c+3098,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_SIZE",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_WAYS",-1,31,0); + vcdp->declBus (c+3099,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_BLOCK",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_BANKS",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[1] bank_structure LOG_NUM_BANKS",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure NUM_REQ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[1] bank_structure LOG_NUM_REQ",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller dcache genblk3[1] bank_structure NUM_IND",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure OFFSET_SIZE_START",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[1] bank_structure OFFSET_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3102,"cache_simX dmem_controller dcache genblk3[1] bank_structure TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure IND_SIZE_END",-1,31,0); + vcdp->declBus (c+3103,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_TAG_START",-1,31,0); + vcdp->declBus (c+3104,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_TAG_END",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_OFFSET_START",-1,31,0); + vcdp->declBus (c+3093,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_OFFSET_END",-1,31,0); + vcdp->declBus (c+3094,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_IND_START",-1,31,0); + vcdp->declBus (c+3105,"cache_simX dmem_controller dcache genblk3[1] bank_structure ADDR_IND_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure CACHE_IDLE",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[1] bank_structure SEND_MEM_REQ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[1] bank_structure RECIV_MEM_RSP",-1,31,0); + vcdp->declBus (c+3094,"cache_simX dmem_controller dcache genblk3[1] bank_structure BLOCK_NUM_BITS",-1,31,0); + vcdp->declBit (c+3064,"cache_simX dmem_controller dcache genblk3[1] bank_structure rst",-1); + vcdp->declBit (c+3063,"cache_simX dmem_controller dcache genblk3[1] bank_structure clk",-1); + vcdp->declBus (c+723,"cache_simX dmem_controller dcache genblk3[1] bank_structure state",-1,3,0); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[1] bank_structure actual_index",-1,4,0); + vcdp->declBus (c+200,"cache_simX dmem_controller dcache genblk3[1] bank_structure o_tag",-1,20,0); + vcdp->declBus (c+3125,"cache_simX dmem_controller dcache genblk3[1] bank_structure block_offset",-1,1,0); + vcdp->declBus (c+391,"cache_simX dmem_controller dcache genblk3[1] bank_structure writedata",-1,31,0); + vcdp->declBit (c+202,"cache_simX dmem_controller dcache genblk3[1] bank_structure valid_in",-1); + vcdp->declBit (c+4,"cache_simX dmem_controller dcache genblk3[1] bank_structure read_or_write",-1); + vcdp->declArray(c+3143,"cache_simX dmem_controller dcache genblk3[1] bank_structure fetched_writedata",-1,127,0); + vcdp->declBus (c+9,"cache_simX dmem_controller dcache genblk3[1] bank_structure i_p_mem_read",-1,2,0); + vcdp->declBus (c+10,"cache_simX dmem_controller dcache genblk3[1] bank_structure i_p_mem_write",-1,2,0); + vcdp->declBus (c+199,"cache_simX dmem_controller dcache genblk3[1] bank_structure byte_select",-1,1,0); + vcdp->declBus (c+722,"cache_simX dmem_controller dcache genblk3[1] bank_structure evicted_way",-1,0,0); + vcdp->declBus (c+392,"cache_simX dmem_controller dcache genblk3[1] bank_structure readdata",-1,31,0); + vcdp->declBit (c+393,"cache_simX dmem_controller dcache genblk3[1] bank_structure hit",-1); + vcdp->declBit (c+619,"cache_simX dmem_controller dcache genblk3[1] bank_structure eviction_wb",-1); + vcdp->declBus (c+394,"cache_simX dmem_controller dcache genblk3[1] bank_structure eviction_addr",-1,31,0); + vcdp->declArray(c+395,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_evicted",-1,127,0); + vcdp->declArray(c+395,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_use",-1,127,0); + vcdp->declBus (c+399,"cache_simX dmem_controller dcache genblk3[1] bank_structure tag_use",-1,20,0); + vcdp->declBus (c+399,"cache_simX dmem_controller dcache genblk3[1] bank_structure eviction_tag",-1,20,0); + vcdp->declBit (c+400,"cache_simX dmem_controller dcache genblk3[1] bank_structure valid_use",-1); + vcdp->declBit (c+619,"cache_simX dmem_controller dcache genblk3[1] bank_structure dirty_use",-1); + vcdp->declBit (c+401,"cache_simX dmem_controller dcache genblk3[1] bank_structure access",-1); + vcdp->declBit (c+402,"cache_simX dmem_controller dcache genblk3[1] bank_structure write_from_mem",-1); + vcdp->declBit (c+403,"cache_simX dmem_controller dcache genblk3[1] bank_structure miss",-1); + vcdp->declBus (c+660,"cache_simX dmem_controller dcache genblk3[1] bank_structure way_to_update",-1,0,0); + vcdp->declBit (c+332,"cache_simX dmem_controller dcache genblk3[1] bank_structure lw",-1); + vcdp->declBit (c+333,"cache_simX dmem_controller dcache genblk3[1] bank_structure lb",-1); + vcdp->declBit (c+334,"cache_simX dmem_controller dcache genblk3[1] bank_structure lh",-1); + vcdp->declBit (c+335,"cache_simX dmem_controller dcache genblk3[1] bank_structure lhu",-1); + vcdp->declBit (c+336,"cache_simX dmem_controller dcache genblk3[1] bank_structure lbu",-1); + vcdp->declBit (c+337,"cache_simX dmem_controller dcache genblk3[1] bank_structure sw",-1); + vcdp->declBit (c+338,"cache_simX dmem_controller dcache genblk3[1] bank_structure sb",-1); + vcdp->declBit (c+339,"cache_simX dmem_controller dcache genblk3[1] bank_structure sh",-1); + vcdp->declBit (c+404,"cache_simX dmem_controller dcache genblk3[1] bank_structure b0",-1); + vcdp->declBit (c+405,"cache_simX dmem_controller dcache genblk3[1] bank_structure b1",-1); + vcdp->declBit (c+406,"cache_simX dmem_controller dcache genblk3[1] bank_structure b2",-1); + vcdp->declBit (c+407,"cache_simX dmem_controller dcache genblk3[1] bank_structure b3",-1); + vcdp->declBus (c+408,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_unQual",-1,31,0); + vcdp->declBus (c+409,"cache_simX dmem_controller dcache genblk3[1] bank_structure lb_data",-1,31,0); + vcdp->declBus (c+410,"cache_simX dmem_controller dcache genblk3[1] bank_structure lh_data",-1,31,0); + vcdp->declBus (c+411,"cache_simX dmem_controller dcache genblk3[1] bank_structure lbu_data",-1,31,0); + vcdp->declBus (c+412,"cache_simX dmem_controller dcache genblk3[1] bank_structure lhu_data",-1,31,0); + vcdp->declBus (c+408,"cache_simX dmem_controller dcache genblk3[1] bank_structure lw_data",-1,31,0); + vcdp->declBus (c+391,"cache_simX dmem_controller dcache genblk3[1] bank_structure sw_data",-1,31,0); + vcdp->declBus (c+413,"cache_simX dmem_controller dcache genblk3[1] bank_structure sb_data",-1,31,0); + vcdp->declBus (c+414,"cache_simX dmem_controller dcache genblk3[1] bank_structure sh_data",-1,31,0); + vcdp->declBus (c+415,"cache_simX dmem_controller dcache genblk3[1] bank_structure use_write_data",-1,31,0); + vcdp->declBus (c+416,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_Qual",-1,31,0); + vcdp->declBus (c+417,"cache_simX dmem_controller dcache genblk3[1] bank_structure sb_mask",-1,3,0); + vcdp->declBus (c+418,"cache_simX dmem_controller dcache genblk3[1] bank_structure sh_mask",-1,3,0); + vcdp->declBus (c+419,"cache_simX dmem_controller dcache genblk3[1] bank_structure we",-1,15,0); + vcdp->declArray(c+420,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_write",-1,127,0); + // Tracing: cache_simX dmem_controller dcache genblk3[1] bank_structure g // Ignored: Verilator trace_off at ../rtl/cache/VX_Cache_Bank.v:203 + vcdp->declBit (c+424,"cache_simX dmem_controller dcache genblk3[1] bank_structure genblk1[0] normal_write",-1); + vcdp->declBit (c+3086,"cache_simX dmem_controller dcache genblk3[1] bank_structure genblk1[1] normal_write",-1); + vcdp->declBit (c+3086,"cache_simX dmem_controller dcache genblk3[1] bank_structure genblk1[2] normal_write",-1); + vcdp->declBit (c+3086,"cache_simX dmem_controller dcache genblk3[1] bank_structure genblk1[3] normal_write",-1); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures CACHE_WAYS",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures NUM_IND",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3102,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures rst",-1); + vcdp->declBit (c+202,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures valid_in",-1); + vcdp->declBus (c+723,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures state",-1,3,0); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures addr",-1,4,0); + vcdp->declBus (c+419,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures we",-1,15,0); + vcdp->declBit (c+402,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures evict",-1); + vcdp->declBus (c+660,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures way_to_update",-1,0,0); + vcdp->declArray(c+420,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures data_write",-1,127,0); + vcdp->declBus (c+200,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures tag_write",-1,20,0); + vcdp->declBus (c+399,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures tag_use",-1,20,0); + vcdp->declArray(c+395,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures data_use",-1,127,0); + vcdp->declBit (c+400,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures valid_use",-1); + vcdp->declBit (c+619,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures dirty_use",-1); + vcdp->declQuad (c+661,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures tag_use_per_way",-1,41,0); + vcdp->declArray(c+663,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures data_use_per_way",-1,255,0); + vcdp->declBus (c+671,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures valid_use_per_way",-1,1,0); + vcdp->declBus (c+672,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures dirty_use_per_way",-1,1,0); + vcdp->declBus (c+425,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures hit_per_way",-1,1,0); + vcdp->declBus (c+426,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures we_per_way",-1,31,0); + vcdp->declArray(c+427,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures data_write_per_way",-1,255,0); + vcdp->declBus (c+435,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures write_from_mem_per_way",-1,1,0); + vcdp->declBit (c+673,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures invalid_found",-1); + vcdp->declBus (c+436,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures way_index",-1,0,0); + vcdp->declBus (c+674,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures invalid_index",-1,0,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures CACHE_IDLE",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures SEND_MEM_REQ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures RECIV_MEM_RSP",-1,31,0); + vcdp->declBus (c+437,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures way_use_Qual",-1,0,0); + // Tracing: cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures ways // Ignored: Verilator trace_off at ../rtl/cache/VX_cache_data_per_index.v:107 + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index N",-1,31,0); + vcdp->declBus (c+675,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index valids",-1,1,0); + vcdp->declBus (c+674,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index index",-1,0,0); + vcdp->declBit (c+673,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index found",-1); + vcdp->declBus (c+3097,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 valid_index i",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing N",-1,31,0); + vcdp->declBus (c+425,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing valids",-1,1,0); + vcdp->declBus (c+436,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing index",-1,0,0); + vcdp->declBit (c+438,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing found",-1); + vcdp->declBus (c+3097,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures genblk1 way_indexing i",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3102,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures rst",-1); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures addr",-1,4,0); + vcdp->declBus (c+439,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures we",-1,15,0); + vcdp->declBit (c+440,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures evict",-1); + vcdp->declArray(c+441,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0); + vcdp->declBus (c+200,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures tag_write",-1,20,0); + vcdp->declBus (c+1665,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0); + vcdp->declArray(c+1666,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0); + vcdp->declBit (c+1670,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures valid_use",-1); + vcdp->declBit (c+1671,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures dirty_use",-1); + vcdp->declBit (c+445,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures currently_writing",-1); + vcdp->declBit (c+620,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures update_dirty",-1); + vcdp->declBit (c+446,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures dirt_new",-1); + vcdp->declArray(c+1672,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0); + vcdp->declArray(c+1676,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0); + vcdp->declArray(c+1680,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0); + vcdp->declArray(c+1684,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0); + vcdp->declArray(c+1688,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0); + vcdp->declArray(c+1692,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0); + vcdp->declArray(c+1696,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0); + vcdp->declArray(c+1700,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0); + vcdp->declArray(c+1704,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0); + vcdp->declArray(c+1708,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0); + vcdp->declArray(c+1712,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0); + vcdp->declArray(c+1716,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0); + vcdp->declArray(c+1720,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0); + vcdp->declArray(c+1724,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0); + vcdp->declArray(c+1728,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0); + vcdp->declArray(c+1732,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0); + vcdp->declArray(c+1736,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0); + vcdp->declArray(c+1740,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0); + vcdp->declArray(c+1744,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0); + vcdp->declArray(c+1748,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0); + vcdp->declArray(c+1752,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0); + vcdp->declArray(c+1756,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0); + vcdp->declArray(c+1760,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0); + vcdp->declArray(c+1764,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0); + vcdp->declArray(c+1768,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0); + vcdp->declArray(c+1772,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0); + vcdp->declArray(c+1776,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0); + vcdp->declArray(c+1780,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0); + vcdp->declArray(c+1784,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0); + vcdp->declArray(c+1788,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0); + vcdp->declArray(c+1792,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0); + vcdp->declArray(c+1796,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus (c+1800+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+1832+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+1864+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}} + vcdp->declBus (c+1896,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures f",-1,31,0); + vcdp->declBus (c+1897,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3102,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures rst",-1); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures addr",-1,4,0); + vcdp->declBus (c+447,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures we",-1,15,0); + vcdp->declBit (c+448,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures evict",-1); + vcdp->declArray(c+449,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0); + vcdp->declBus (c+200,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures tag_write",-1,20,0); + vcdp->declBus (c+1898,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0); + vcdp->declArray(c+1899,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0); + vcdp->declBit (c+1903,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures valid_use",-1); + vcdp->declBit (c+1904,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures dirty_use",-1); + vcdp->declBit (c+453,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures currently_writing",-1); + vcdp->declBit (c+621,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures update_dirty",-1); + vcdp->declBit (c+454,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures dirt_new",-1); + vcdp->declArray(c+1905,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0); + vcdp->declArray(c+1909,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0); + vcdp->declArray(c+1913,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0); + vcdp->declArray(c+1917,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0); + vcdp->declArray(c+1921,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0); + vcdp->declArray(c+1925,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0); + vcdp->declArray(c+1929,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0); + vcdp->declArray(c+1933,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0); + vcdp->declArray(c+1937,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0); + vcdp->declArray(c+1941,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0); + vcdp->declArray(c+1945,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0); + vcdp->declArray(c+1949,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0); + vcdp->declArray(c+1953,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0); + vcdp->declArray(c+1957,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0); + vcdp->declArray(c+1961,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0); + vcdp->declArray(c+1965,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0); + vcdp->declArray(c+1969,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0); + vcdp->declArray(c+1973,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0); + vcdp->declArray(c+1977,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0); + vcdp->declArray(c+1981,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0); + vcdp->declArray(c+1985,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0); + vcdp->declArray(c+1989,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0); + vcdp->declArray(c+1993,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0); + vcdp->declArray(c+1997,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0); + vcdp->declArray(c+2001,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0); + vcdp->declArray(c+2005,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0); + vcdp->declArray(c+2009,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0); + vcdp->declArray(c+2013,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0); + vcdp->declArray(c+2017,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0); + vcdp->declArray(c+2021,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0); + vcdp->declArray(c+2025,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0); + vcdp->declArray(c+2029,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus (c+2033+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+2065+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+2097+i*1,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}} + vcdp->declBus (c+2129,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures f",-1,31,0); + vcdp->declBus (c+2130,"cache_simX dmem_controller dcache genblk3[1] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0); + vcdp->declBus (c+3098,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_SIZE",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_WAYS",-1,31,0); + vcdp->declBus (c+3099,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_BLOCK",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_BANKS",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[2] bank_structure LOG_NUM_BANKS",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure NUM_REQ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[2] bank_structure LOG_NUM_REQ",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller dcache genblk3[2] bank_structure NUM_IND",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure OFFSET_SIZE_START",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[2] bank_structure OFFSET_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3102,"cache_simX dmem_controller dcache genblk3[2] bank_structure TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure IND_SIZE_END",-1,31,0); + vcdp->declBus (c+3103,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_TAG_START",-1,31,0); + vcdp->declBus (c+3104,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_TAG_END",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_OFFSET_START",-1,31,0); + vcdp->declBus (c+3093,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_OFFSET_END",-1,31,0); + vcdp->declBus (c+3094,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_IND_START",-1,31,0); + vcdp->declBus (c+3105,"cache_simX dmem_controller dcache genblk3[2] bank_structure ADDR_IND_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure CACHE_IDLE",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[2] bank_structure SEND_MEM_REQ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[2] bank_structure RECIV_MEM_RSP",-1,31,0); + vcdp->declBus (c+3094,"cache_simX dmem_controller dcache genblk3[2] bank_structure BLOCK_NUM_BITS",-1,31,0); + vcdp->declBit (c+3064,"cache_simX dmem_controller dcache genblk3[2] bank_structure rst",-1); + vcdp->declBit (c+3063,"cache_simX dmem_controller dcache genblk3[2] bank_structure clk",-1); + vcdp->declBus (c+723,"cache_simX dmem_controller dcache genblk3[2] bank_structure state",-1,3,0); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[2] bank_structure actual_index",-1,4,0); + vcdp->declBus (c+205,"cache_simX dmem_controller dcache genblk3[2] bank_structure o_tag",-1,20,0); + vcdp->declBus (c+3125,"cache_simX dmem_controller dcache genblk3[2] bank_structure block_offset",-1,1,0); + vcdp->declBus (c+455,"cache_simX dmem_controller dcache genblk3[2] bank_structure writedata",-1,31,0); + vcdp->declBit (c+207,"cache_simX dmem_controller dcache genblk3[2] bank_structure valid_in",-1); + vcdp->declBit (c+4,"cache_simX dmem_controller dcache genblk3[2] bank_structure read_or_write",-1); + vcdp->declArray(c+3147,"cache_simX dmem_controller dcache genblk3[2] bank_structure fetched_writedata",-1,127,0); + vcdp->declBus (c+9,"cache_simX dmem_controller dcache genblk3[2] bank_structure i_p_mem_read",-1,2,0); + vcdp->declBus (c+10,"cache_simX dmem_controller dcache genblk3[2] bank_structure i_p_mem_write",-1,2,0); + vcdp->declBus (c+204,"cache_simX dmem_controller dcache genblk3[2] bank_structure byte_select",-1,1,0); + vcdp->declBus (c+722,"cache_simX dmem_controller dcache genblk3[2] bank_structure evicted_way",-1,0,0); + vcdp->declBus (c+456,"cache_simX dmem_controller dcache genblk3[2] bank_structure readdata",-1,31,0); + vcdp->declBit (c+457,"cache_simX dmem_controller dcache genblk3[2] bank_structure hit",-1); + vcdp->declBit (c+622,"cache_simX dmem_controller dcache genblk3[2] bank_structure eviction_wb",-1); + vcdp->declBus (c+458,"cache_simX dmem_controller dcache genblk3[2] bank_structure eviction_addr",-1,31,0); + vcdp->declArray(c+459,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_evicted",-1,127,0); + vcdp->declArray(c+459,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_use",-1,127,0); + vcdp->declBus (c+463,"cache_simX dmem_controller dcache genblk3[2] bank_structure tag_use",-1,20,0); + vcdp->declBus (c+463,"cache_simX dmem_controller dcache genblk3[2] bank_structure eviction_tag",-1,20,0); + vcdp->declBit (c+464,"cache_simX dmem_controller dcache genblk3[2] bank_structure valid_use",-1); + vcdp->declBit (c+622,"cache_simX dmem_controller dcache genblk3[2] bank_structure dirty_use",-1); + vcdp->declBit (c+465,"cache_simX dmem_controller dcache genblk3[2] bank_structure access",-1); + vcdp->declBit (c+466,"cache_simX dmem_controller dcache genblk3[2] bank_structure write_from_mem",-1); + vcdp->declBit (c+467,"cache_simX dmem_controller dcache genblk3[2] bank_structure miss",-1); + vcdp->declBus (c+676,"cache_simX dmem_controller dcache genblk3[2] bank_structure way_to_update",-1,0,0); + vcdp->declBit (c+332,"cache_simX dmem_controller dcache genblk3[2] bank_structure lw",-1); + vcdp->declBit (c+333,"cache_simX dmem_controller dcache genblk3[2] bank_structure lb",-1); + vcdp->declBit (c+334,"cache_simX dmem_controller dcache genblk3[2] bank_structure lh",-1); + vcdp->declBit (c+335,"cache_simX dmem_controller dcache genblk3[2] bank_structure lhu",-1); + vcdp->declBit (c+336,"cache_simX dmem_controller dcache genblk3[2] bank_structure lbu",-1); + vcdp->declBit (c+337,"cache_simX dmem_controller dcache genblk3[2] bank_structure sw",-1); + vcdp->declBit (c+338,"cache_simX dmem_controller dcache genblk3[2] bank_structure sb",-1); + vcdp->declBit (c+339,"cache_simX dmem_controller dcache genblk3[2] bank_structure sh",-1); + vcdp->declBit (c+468,"cache_simX dmem_controller dcache genblk3[2] bank_structure b0",-1); + vcdp->declBit (c+469,"cache_simX dmem_controller dcache genblk3[2] bank_structure b1",-1); + vcdp->declBit (c+470,"cache_simX dmem_controller dcache genblk3[2] bank_structure b2",-1); + vcdp->declBit (c+471,"cache_simX dmem_controller dcache genblk3[2] bank_structure b3",-1); + vcdp->declBus (c+472,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_unQual",-1,31,0); + vcdp->declBus (c+473,"cache_simX dmem_controller dcache genblk3[2] bank_structure lb_data",-1,31,0); + vcdp->declBus (c+474,"cache_simX dmem_controller dcache genblk3[2] bank_structure lh_data",-1,31,0); + vcdp->declBus (c+475,"cache_simX dmem_controller dcache genblk3[2] bank_structure lbu_data",-1,31,0); + vcdp->declBus (c+476,"cache_simX dmem_controller dcache genblk3[2] bank_structure lhu_data",-1,31,0); + vcdp->declBus (c+472,"cache_simX dmem_controller dcache genblk3[2] bank_structure lw_data",-1,31,0); + vcdp->declBus (c+455,"cache_simX dmem_controller dcache genblk3[2] bank_structure sw_data",-1,31,0); + vcdp->declBus (c+477,"cache_simX dmem_controller dcache genblk3[2] bank_structure sb_data",-1,31,0); + vcdp->declBus (c+478,"cache_simX dmem_controller dcache genblk3[2] bank_structure sh_data",-1,31,0); + vcdp->declBus (c+479,"cache_simX dmem_controller dcache genblk3[2] bank_structure use_write_data",-1,31,0); + vcdp->declBus (c+480,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_Qual",-1,31,0); + vcdp->declBus (c+481,"cache_simX dmem_controller dcache genblk3[2] bank_structure sb_mask",-1,3,0); + vcdp->declBus (c+482,"cache_simX dmem_controller dcache genblk3[2] bank_structure sh_mask",-1,3,0); + vcdp->declBus (c+483,"cache_simX dmem_controller dcache genblk3[2] bank_structure we",-1,15,0); + vcdp->declArray(c+484,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_write",-1,127,0); + // Tracing: cache_simX dmem_controller dcache genblk3[2] bank_structure g // Ignored: Verilator trace_off at ../rtl/cache/VX_Cache_Bank.v:203 + vcdp->declBit (c+488,"cache_simX dmem_controller dcache genblk3[2] bank_structure genblk1[0] normal_write",-1); + vcdp->declBit (c+3086,"cache_simX dmem_controller dcache genblk3[2] bank_structure genblk1[1] normal_write",-1); + vcdp->declBit (c+3086,"cache_simX dmem_controller dcache genblk3[2] bank_structure genblk1[2] normal_write",-1); + vcdp->declBit (c+3086,"cache_simX dmem_controller dcache genblk3[2] bank_structure genblk1[3] normal_write",-1); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures CACHE_WAYS",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures NUM_IND",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3102,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures rst",-1); + vcdp->declBit (c+207,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures valid_in",-1); + vcdp->declBus (c+723,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures state",-1,3,0); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures addr",-1,4,0); + vcdp->declBus (c+483,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures we",-1,15,0); + vcdp->declBit (c+466,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures evict",-1); + vcdp->declBus (c+676,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures way_to_update",-1,0,0); + vcdp->declArray(c+484,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures data_write",-1,127,0); + vcdp->declBus (c+205,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures tag_write",-1,20,0); + vcdp->declBus (c+463,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures tag_use",-1,20,0); + vcdp->declArray(c+459,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures data_use",-1,127,0); + vcdp->declBit (c+464,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures valid_use",-1); + vcdp->declBit (c+622,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures dirty_use",-1); + vcdp->declQuad (c+677,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures tag_use_per_way",-1,41,0); + vcdp->declArray(c+679,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures data_use_per_way",-1,255,0); + vcdp->declBus (c+687,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures valid_use_per_way",-1,1,0); + vcdp->declBus (c+688,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures dirty_use_per_way",-1,1,0); + vcdp->declBus (c+489,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures hit_per_way",-1,1,0); + vcdp->declBus (c+490,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures we_per_way",-1,31,0); + vcdp->declArray(c+491,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures data_write_per_way",-1,255,0); + vcdp->declBus (c+499,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures write_from_mem_per_way",-1,1,0); + vcdp->declBit (c+689,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures invalid_found",-1); + vcdp->declBus (c+500,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures way_index",-1,0,0); + vcdp->declBus (c+690,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures invalid_index",-1,0,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures CACHE_IDLE",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures SEND_MEM_REQ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures RECIV_MEM_RSP",-1,31,0); + vcdp->declBus (c+501,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures way_use_Qual",-1,0,0); + // Tracing: cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures ways // Ignored: Verilator trace_off at ../rtl/cache/VX_cache_data_per_index.v:107 + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index N",-1,31,0); + vcdp->declBus (c+691,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index valids",-1,1,0); + vcdp->declBus (c+690,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index index",-1,0,0); + vcdp->declBit (c+689,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index found",-1); + vcdp->declBus (c+3097,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 valid_index i",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing N",-1,31,0); + vcdp->declBus (c+489,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing valids",-1,1,0); + vcdp->declBus (c+500,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing index",-1,0,0); + vcdp->declBit (c+502,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing found",-1); + vcdp->declBus (c+3097,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures genblk1 way_indexing i",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3102,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures rst",-1); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures addr",-1,4,0); + vcdp->declBus (c+503,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures we",-1,15,0); + vcdp->declBit (c+504,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures evict",-1); + vcdp->declArray(c+505,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0); + vcdp->declBus (c+205,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures tag_write",-1,20,0); + vcdp->declBus (c+2131,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0); + vcdp->declArray(c+2132,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0); + vcdp->declBit (c+2136,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures valid_use",-1); + vcdp->declBit (c+2137,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures dirty_use",-1); + vcdp->declBit (c+509,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures currently_writing",-1); + vcdp->declBit (c+623,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures update_dirty",-1); + vcdp->declBit (c+510,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures dirt_new",-1); + vcdp->declArray(c+2138,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0); + vcdp->declArray(c+2142,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0); + vcdp->declArray(c+2146,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0); + vcdp->declArray(c+2150,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0); + vcdp->declArray(c+2154,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0); + vcdp->declArray(c+2158,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0); + vcdp->declArray(c+2162,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0); + vcdp->declArray(c+2166,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0); + vcdp->declArray(c+2170,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0); + vcdp->declArray(c+2174,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0); + vcdp->declArray(c+2178,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0); + vcdp->declArray(c+2182,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0); + vcdp->declArray(c+2186,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0); + vcdp->declArray(c+2190,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0); + vcdp->declArray(c+2194,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0); + vcdp->declArray(c+2198,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0); + vcdp->declArray(c+2202,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0); + vcdp->declArray(c+2206,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0); + vcdp->declArray(c+2210,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0); + vcdp->declArray(c+2214,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0); + vcdp->declArray(c+2218,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0); + vcdp->declArray(c+2222,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0); + vcdp->declArray(c+2226,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0); + vcdp->declArray(c+2230,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0); + vcdp->declArray(c+2234,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0); + vcdp->declArray(c+2238,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0); + vcdp->declArray(c+2242,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0); + vcdp->declArray(c+2246,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0); + vcdp->declArray(c+2250,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0); + vcdp->declArray(c+2254,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0); + vcdp->declArray(c+2258,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0); + vcdp->declArray(c+2262,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus (c+2266+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+2298+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+2330+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}} + vcdp->declBus (c+2362,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures f",-1,31,0); + vcdp->declBus (c+2363,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3102,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures rst",-1); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures addr",-1,4,0); + vcdp->declBus (c+511,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures we",-1,15,0); + vcdp->declBit (c+512,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures evict",-1); + vcdp->declArray(c+513,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0); + vcdp->declBus (c+205,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures tag_write",-1,20,0); + vcdp->declBus (c+2364,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0); + vcdp->declArray(c+2365,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0); + vcdp->declBit (c+2369,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures valid_use",-1); + vcdp->declBit (c+2370,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures dirty_use",-1); + vcdp->declBit (c+517,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures currently_writing",-1); + vcdp->declBit (c+624,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures update_dirty",-1); + vcdp->declBit (c+518,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures dirt_new",-1); + vcdp->declArray(c+2371,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0); + vcdp->declArray(c+2375,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0); + vcdp->declArray(c+2379,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0); + vcdp->declArray(c+2383,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0); + vcdp->declArray(c+2387,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0); + vcdp->declArray(c+2391,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0); + vcdp->declArray(c+2395,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0); + vcdp->declArray(c+2399,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0); + vcdp->declArray(c+2403,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0); + vcdp->declArray(c+2407,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0); + vcdp->declArray(c+2411,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0); + vcdp->declArray(c+2415,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0); + vcdp->declArray(c+2419,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0); + vcdp->declArray(c+2423,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0); + vcdp->declArray(c+2427,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0); + vcdp->declArray(c+2431,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0); + vcdp->declArray(c+2435,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0); + vcdp->declArray(c+2439,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0); + vcdp->declArray(c+2443,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0); + vcdp->declArray(c+2447,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0); + vcdp->declArray(c+2451,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0); + vcdp->declArray(c+2455,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0); + vcdp->declArray(c+2459,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0); + vcdp->declArray(c+2463,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0); + vcdp->declArray(c+2467,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0); + vcdp->declArray(c+2471,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0); + vcdp->declArray(c+2475,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0); + vcdp->declArray(c+2479,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0); + vcdp->declArray(c+2483,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0); + vcdp->declArray(c+2487,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0); + vcdp->declArray(c+2491,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0); + vcdp->declArray(c+2495,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus (c+2499+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+2531+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+2563+i*1,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}} + vcdp->declBus (c+2595,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures f",-1,31,0); + vcdp->declBus (c+2596,"cache_simX dmem_controller dcache genblk3[2] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0); + vcdp->declBus (c+3098,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_SIZE",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_WAYS",-1,31,0); + vcdp->declBus (c+3099,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_BLOCK",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_BANKS",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[3] bank_structure LOG_NUM_BANKS",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure NUM_REQ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[3] bank_structure LOG_NUM_REQ",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller dcache genblk3[3] bank_structure NUM_IND",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure OFFSET_SIZE_START",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[3] bank_structure OFFSET_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3102,"cache_simX dmem_controller dcache genblk3[3] bank_structure TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure IND_SIZE_END",-1,31,0); + vcdp->declBus (c+3103,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_TAG_START",-1,31,0); + vcdp->declBus (c+3104,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_TAG_END",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_OFFSET_START",-1,31,0); + vcdp->declBus (c+3093,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_OFFSET_END",-1,31,0); + vcdp->declBus (c+3094,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_IND_START",-1,31,0); + vcdp->declBus (c+3105,"cache_simX dmem_controller dcache genblk3[3] bank_structure ADDR_IND_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure CACHE_IDLE",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[3] bank_structure SEND_MEM_REQ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[3] bank_structure RECIV_MEM_RSP",-1,31,0); + vcdp->declBus (c+3094,"cache_simX dmem_controller dcache genblk3[3] bank_structure BLOCK_NUM_BITS",-1,31,0); + vcdp->declBit (c+3064,"cache_simX dmem_controller dcache genblk3[3] bank_structure rst",-1); + vcdp->declBit (c+3063,"cache_simX dmem_controller dcache genblk3[3] bank_structure clk",-1); + vcdp->declBus (c+723,"cache_simX dmem_controller dcache genblk3[3] bank_structure state",-1,3,0); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[3] bank_structure actual_index",-1,4,0); + vcdp->declBus (c+210,"cache_simX dmem_controller dcache genblk3[3] bank_structure o_tag",-1,20,0); + vcdp->declBus (c+3125,"cache_simX dmem_controller dcache genblk3[3] bank_structure block_offset",-1,1,0); + vcdp->declBus (c+519,"cache_simX dmem_controller dcache genblk3[3] bank_structure writedata",-1,31,0); + vcdp->declBit (c+212,"cache_simX dmem_controller dcache genblk3[3] bank_structure valid_in",-1); + vcdp->declBit (c+4,"cache_simX dmem_controller dcache genblk3[3] bank_structure read_or_write",-1); + vcdp->declArray(c+3151,"cache_simX dmem_controller dcache genblk3[3] bank_structure fetched_writedata",-1,127,0); + vcdp->declBus (c+9,"cache_simX dmem_controller dcache genblk3[3] bank_structure i_p_mem_read",-1,2,0); + vcdp->declBus (c+10,"cache_simX dmem_controller dcache genblk3[3] bank_structure i_p_mem_write",-1,2,0); + vcdp->declBus (c+209,"cache_simX dmem_controller dcache genblk3[3] bank_structure byte_select",-1,1,0); + vcdp->declBus (c+722,"cache_simX dmem_controller dcache genblk3[3] bank_structure evicted_way",-1,0,0); + vcdp->declBus (c+520,"cache_simX dmem_controller dcache genblk3[3] bank_structure readdata",-1,31,0); + vcdp->declBit (c+521,"cache_simX dmem_controller dcache genblk3[3] bank_structure hit",-1); + vcdp->declBit (c+625,"cache_simX dmem_controller dcache genblk3[3] bank_structure eviction_wb",-1); + vcdp->declBus (c+522,"cache_simX dmem_controller dcache genblk3[3] bank_structure eviction_addr",-1,31,0); + vcdp->declArray(c+523,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_evicted",-1,127,0); + vcdp->declArray(c+523,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_use",-1,127,0); + vcdp->declBus (c+527,"cache_simX dmem_controller dcache genblk3[3] bank_structure tag_use",-1,20,0); + vcdp->declBus (c+527,"cache_simX dmem_controller dcache genblk3[3] bank_structure eviction_tag",-1,20,0); + vcdp->declBit (c+528,"cache_simX dmem_controller dcache genblk3[3] bank_structure valid_use",-1); + vcdp->declBit (c+625,"cache_simX dmem_controller dcache genblk3[3] bank_structure dirty_use",-1); + vcdp->declBit (c+529,"cache_simX dmem_controller dcache genblk3[3] bank_structure access",-1); + vcdp->declBit (c+530,"cache_simX dmem_controller dcache genblk3[3] bank_structure write_from_mem",-1); + vcdp->declBit (c+531,"cache_simX dmem_controller dcache genblk3[3] bank_structure miss",-1); + vcdp->declBus (c+692,"cache_simX dmem_controller dcache genblk3[3] bank_structure way_to_update",-1,0,0); + vcdp->declBit (c+332,"cache_simX dmem_controller dcache genblk3[3] bank_structure lw",-1); + vcdp->declBit (c+333,"cache_simX dmem_controller dcache genblk3[3] bank_structure lb",-1); + vcdp->declBit (c+334,"cache_simX dmem_controller dcache genblk3[3] bank_structure lh",-1); + vcdp->declBit (c+335,"cache_simX dmem_controller dcache genblk3[3] bank_structure lhu",-1); + vcdp->declBit (c+336,"cache_simX dmem_controller dcache genblk3[3] bank_structure lbu",-1); + vcdp->declBit (c+337,"cache_simX dmem_controller dcache genblk3[3] bank_structure sw",-1); + vcdp->declBit (c+338,"cache_simX dmem_controller dcache genblk3[3] bank_structure sb",-1); + vcdp->declBit (c+339,"cache_simX dmem_controller dcache genblk3[3] bank_structure sh",-1); + vcdp->declBit (c+532,"cache_simX dmem_controller dcache genblk3[3] bank_structure b0",-1); + vcdp->declBit (c+533,"cache_simX dmem_controller dcache genblk3[3] bank_structure b1",-1); + vcdp->declBit (c+534,"cache_simX dmem_controller dcache genblk3[3] bank_structure b2",-1); + vcdp->declBit (c+535,"cache_simX dmem_controller dcache genblk3[3] bank_structure b3",-1); + vcdp->declBus (c+536,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_unQual",-1,31,0); + vcdp->declBus (c+537,"cache_simX dmem_controller dcache genblk3[3] bank_structure lb_data",-1,31,0); + vcdp->declBus (c+538,"cache_simX dmem_controller dcache genblk3[3] bank_structure lh_data",-1,31,0); + vcdp->declBus (c+539,"cache_simX dmem_controller dcache genblk3[3] bank_structure lbu_data",-1,31,0); + vcdp->declBus (c+540,"cache_simX dmem_controller dcache genblk3[3] bank_structure lhu_data",-1,31,0); + vcdp->declBus (c+536,"cache_simX dmem_controller dcache genblk3[3] bank_structure lw_data",-1,31,0); + vcdp->declBus (c+519,"cache_simX dmem_controller dcache genblk3[3] bank_structure sw_data",-1,31,0); + vcdp->declBus (c+541,"cache_simX dmem_controller dcache genblk3[3] bank_structure sb_data",-1,31,0); + vcdp->declBus (c+542,"cache_simX dmem_controller dcache genblk3[3] bank_structure sh_data",-1,31,0); + vcdp->declBus (c+543,"cache_simX dmem_controller dcache genblk3[3] bank_structure use_write_data",-1,31,0); + vcdp->declBus (c+544,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_Qual",-1,31,0); + vcdp->declBus (c+545,"cache_simX dmem_controller dcache genblk3[3] bank_structure sb_mask",-1,3,0); + vcdp->declBus (c+546,"cache_simX dmem_controller dcache genblk3[3] bank_structure sh_mask",-1,3,0); + vcdp->declBus (c+547,"cache_simX dmem_controller dcache genblk3[3] bank_structure we",-1,15,0); + vcdp->declArray(c+548,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_write",-1,127,0); + // Tracing: cache_simX dmem_controller dcache genblk3[3] bank_structure g // Ignored: Verilator trace_off at ../rtl/cache/VX_Cache_Bank.v:203 + vcdp->declBit (c+552,"cache_simX dmem_controller dcache genblk3[3] bank_structure genblk1[0] normal_write",-1); + vcdp->declBit (c+3086,"cache_simX dmem_controller dcache genblk3[3] bank_structure genblk1[1] normal_write",-1); + vcdp->declBit (c+3086,"cache_simX dmem_controller dcache genblk3[3] bank_structure genblk1[2] normal_write",-1); + vcdp->declBit (c+3086,"cache_simX dmem_controller dcache genblk3[3] bank_structure genblk1[3] normal_write",-1); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures CACHE_WAYS",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures NUM_IND",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures CACHE_WAY_INDEX",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3102,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures rst",-1); + vcdp->declBit (c+212,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures valid_in",-1); + vcdp->declBus (c+723,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures state",-1,3,0); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures addr",-1,4,0); + vcdp->declBus (c+547,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures we",-1,15,0); + vcdp->declBit (c+530,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures evict",-1); + vcdp->declBus (c+692,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures way_to_update",-1,0,0); + vcdp->declArray(c+548,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures data_write",-1,127,0); + vcdp->declBus (c+210,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures tag_write",-1,20,0); + vcdp->declBus (c+527,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures tag_use",-1,20,0); + vcdp->declArray(c+523,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures data_use",-1,127,0); + vcdp->declBit (c+528,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures valid_use",-1); + vcdp->declBit (c+625,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures dirty_use",-1); + vcdp->declQuad (c+693,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures tag_use_per_way",-1,41,0); + vcdp->declArray(c+695,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures data_use_per_way",-1,255,0); + vcdp->declBus (c+703,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures valid_use_per_way",-1,1,0); + vcdp->declBus (c+704,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures dirty_use_per_way",-1,1,0); + vcdp->declBus (c+553,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures hit_per_way",-1,1,0); + vcdp->declBus (c+554,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures we_per_way",-1,31,0); + vcdp->declArray(c+555,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures data_write_per_way",-1,255,0); + vcdp->declBus (c+563,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures write_from_mem_per_way",-1,1,0); + vcdp->declBit (c+705,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures invalid_found",-1); + vcdp->declBus (c+564,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures way_index",-1,0,0); + vcdp->declBus (c+706,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures invalid_index",-1,0,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures CACHE_IDLE",-1,31,0); + vcdp->declBus (c+3101,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures SEND_MEM_REQ",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures RECIV_MEM_RSP",-1,31,0); + vcdp->declBus (c+565,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures way_use_Qual",-1,0,0); + // Tracing: cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures ways // Ignored: Verilator trace_off at ../rtl/cache/VX_cache_data_per_index.v:107 + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index N",-1,31,0); + vcdp->declBus (c+707,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index valids",-1,1,0); + vcdp->declBus (c+706,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index index",-1,0,0); + vcdp->declBit (c+705,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index found",-1); + vcdp->declBus (c+3097,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 valid_index i",-1,31,0); + vcdp->declBus (c+3090,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing N",-1,31,0); + vcdp->declBus (c+553,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing valids",-1,1,0); + vcdp->declBus (c+564,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing index",-1,0,0); + vcdp->declBit (c+566,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing found",-1); + vcdp->declBus (c+3097,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures genblk1 way_indexing i",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures NUM_IND",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3102,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures rst",-1); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures addr",-1,4,0); + vcdp->declBus (c+567,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures we",-1,15,0); + vcdp->declBit (c+568,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures evict",-1); + vcdp->declArray(c+569,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data_write",-1,127,0); + vcdp->declBus (c+210,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures tag_write",-1,20,0); + vcdp->declBus (c+2597,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures tag_use",-1,20,0); + vcdp->declArray(c+2598,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data_use",-1,127,0); + vcdp->declBit (c+2602,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures valid_use",-1); + vcdp->declBit (c+2603,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures dirty_use",-1); + vcdp->declBit (c+573,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures currently_writing",-1); + vcdp->declBit (c+626,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures update_dirty",-1); + vcdp->declBit (c+574,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures dirt_new",-1); + vcdp->declArray(c+2604,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(0)",-1,127,0); + vcdp->declArray(c+2608,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(1)",-1,127,0); + vcdp->declArray(c+2612,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(2)",-1,127,0); + vcdp->declArray(c+2616,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(3)",-1,127,0); + vcdp->declArray(c+2620,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(4)",-1,127,0); + vcdp->declArray(c+2624,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(5)",-1,127,0); + vcdp->declArray(c+2628,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(6)",-1,127,0); + vcdp->declArray(c+2632,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(7)",-1,127,0); + vcdp->declArray(c+2636,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(8)",-1,127,0); + vcdp->declArray(c+2640,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(9)",-1,127,0); + vcdp->declArray(c+2644,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(10)",-1,127,0); + vcdp->declArray(c+2648,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(11)",-1,127,0); + vcdp->declArray(c+2652,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(12)",-1,127,0); + vcdp->declArray(c+2656,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(13)",-1,127,0); + vcdp->declArray(c+2660,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(14)",-1,127,0); + vcdp->declArray(c+2664,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(15)",-1,127,0); + vcdp->declArray(c+2668,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(16)",-1,127,0); + vcdp->declArray(c+2672,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(17)",-1,127,0); + vcdp->declArray(c+2676,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(18)",-1,127,0); + vcdp->declArray(c+2680,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(19)",-1,127,0); + vcdp->declArray(c+2684,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(20)",-1,127,0); + vcdp->declArray(c+2688,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(21)",-1,127,0); + vcdp->declArray(c+2692,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(22)",-1,127,0); + vcdp->declArray(c+2696,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(23)",-1,127,0); + vcdp->declArray(c+2700,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(24)",-1,127,0); + vcdp->declArray(c+2704,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(25)",-1,127,0); + vcdp->declArray(c+2708,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(26)",-1,127,0); + vcdp->declArray(c+2712,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(27)",-1,127,0); + vcdp->declArray(c+2716,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(28)",-1,127,0); + vcdp->declArray(c+2720,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(29)",-1,127,0); + vcdp->declArray(c+2724,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(30)",-1,127,0); + vcdp->declArray(c+2728,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus (c+2732+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures tag",(i+0),20,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+2764+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+2796+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures dirty",(i+0));}} + vcdp->declBus (c+2828,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures f",-1,31,0); + vcdp->declBus (c+2829,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[0] data_structures ini_ind",-1,31,0); + vcdp->declBus (c+3100,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures NUM_IND",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures NUM_WORDS_PER_BLOCK",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures TAG_SIZE_START",-1,31,0); + vcdp->declBus (c+3102,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures TAG_SIZE_END",-1,31,0); + vcdp->declBus (c+3085,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures IND_SIZE_START",-1,31,0); + vcdp->declBus (c+3088,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures IND_SIZE_END",-1,31,0); + vcdp->declBit (c+3063,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures clk",-1); + vcdp->declBit (c+3064,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures rst",-1); + vcdp->declBus (c+3126,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures addr",-1,4,0); + vcdp->declBus (c+575,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures we",-1,15,0); + vcdp->declBit (c+576,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures evict",-1); + vcdp->declArray(c+577,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data_write",-1,127,0); + vcdp->declBus (c+210,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures tag_write",-1,20,0); + vcdp->declBus (c+2830,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures tag_use",-1,20,0); + vcdp->declArray(c+2831,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data_use",-1,127,0); + vcdp->declBit (c+2835,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures valid_use",-1); + vcdp->declBit (c+2836,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures dirty_use",-1); + vcdp->declBit (c+581,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures currently_writing",-1); + vcdp->declBit (c+627,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures update_dirty",-1); + vcdp->declBit (c+582,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures dirt_new",-1); + vcdp->declArray(c+2837,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(0)",-1,127,0); + vcdp->declArray(c+2841,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(1)",-1,127,0); + vcdp->declArray(c+2845,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(2)",-1,127,0); + vcdp->declArray(c+2849,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(3)",-1,127,0); + vcdp->declArray(c+2853,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(4)",-1,127,0); + vcdp->declArray(c+2857,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(5)",-1,127,0); + vcdp->declArray(c+2861,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(6)",-1,127,0); + vcdp->declArray(c+2865,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(7)",-1,127,0); + vcdp->declArray(c+2869,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(8)",-1,127,0); + vcdp->declArray(c+2873,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(9)",-1,127,0); + vcdp->declArray(c+2877,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(10)",-1,127,0); + vcdp->declArray(c+2881,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(11)",-1,127,0); + vcdp->declArray(c+2885,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(12)",-1,127,0); + vcdp->declArray(c+2889,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(13)",-1,127,0); + vcdp->declArray(c+2893,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(14)",-1,127,0); + vcdp->declArray(c+2897,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(15)",-1,127,0); + vcdp->declArray(c+2901,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(16)",-1,127,0); + vcdp->declArray(c+2905,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(17)",-1,127,0); + vcdp->declArray(c+2909,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(18)",-1,127,0); + vcdp->declArray(c+2913,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(19)",-1,127,0); + vcdp->declArray(c+2917,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(20)",-1,127,0); + vcdp->declArray(c+2921,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(21)",-1,127,0); + vcdp->declArray(c+2925,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(22)",-1,127,0); + vcdp->declArray(c+2929,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(23)",-1,127,0); + vcdp->declArray(c+2933,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(24)",-1,127,0); + vcdp->declArray(c+2937,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(25)",-1,127,0); + vcdp->declArray(c+2941,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(26)",-1,127,0); + vcdp->declArray(c+2945,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(27)",-1,127,0); + vcdp->declArray(c+2949,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(28)",-1,127,0); + vcdp->declArray(c+2953,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(29)",-1,127,0); + vcdp->declArray(c+2957,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(30)",-1,127,0); + vcdp->declArray(c+2961,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures data(31)",-1,127,0); + {int i; for (i=0; i<32; i++) { + vcdp->declBus (c+2965+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures tag",(i+0),20,0);}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+2997+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures valid",(i+0));}} + {int i; for (i=0; i<32; i++) { + vcdp->declBit (c+3029+i*1,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures dirty",(i+0));}} + vcdp->declBus (c+3061,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures f",-1,31,0); + vcdp->declBus (c+3062,"cache_simX dmem_controller dcache genblk3[3] bank_structure data_structures each_way[1] data_structures ini_ind",-1,31,0); + } +} + +void Vcache_simX::traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c=code; + if (0 && vcdp && c) {} // Prevent unused + // Variables + VL_SIGW(__Vtemp207,127,0,4); + VL_SIGW(__Vtemp208,127,0,4); + VL_SIGW(__Vtemp209,127,0,4); + VL_SIGW(__Vtemp210,127,0,4); + VL_SIGW(__Vtemp211,127,0,4); + VL_SIGW(__Vtemp212,127,0,4); + VL_SIGW(__Vtemp213,127,0,4); + VL_SIGW(__Vtemp214,127,0,4); + VL_SIGW(__Vtemp215,127,0,4); + VL_SIGW(__Vtemp216,127,0,4); + VL_SIGW(__Vtemp217,127,0,4); + VL_SIGW(__Vtemp218,127,0,4); + VL_SIGW(__Vtemp219,127,0,4); + VL_SIGW(__Vtemp220,127,0,4); + VL_SIGW(__Vtemp221,127,0,4); + VL_SIGW(__Vtemp222,127,0,4); + VL_SIGW(__Vtemp223,127,0,4); + VL_SIGW(__Vtemp224,127,0,4); + VL_SIGW(__Vtemp225,127,0,4); + VL_SIGW(__Vtemp226,127,0,4); + VL_SIGW(__Vtemp227,127,0,4); + VL_SIGW(__Vtemp228,127,0,4); + VL_SIGW(__Vtemp229,127,0,4); + VL_SIGW(__Vtemp230,127,0,4); + VL_SIGW(__Vtemp231,127,0,4); + VL_SIGW(__Vtemp232,127,0,4); + VL_SIGW(__Vtemp233,127,0,4); + VL_SIGW(__Vtemp234,127,0,4); + VL_SIGW(__Vtemp235,127,0,4); + VL_SIGW(__Vtemp236,127,0,4); + VL_SIGW(__Vtemp237,127,0,4); + VL_SIGW(__Vtemp238,127,0,4); + VL_SIGW(__Vtemp239,127,0,4); + VL_SIGW(__Vtemp240,127,0,4); + VL_SIGW(__Vtemp241,127,0,4); + VL_SIGW(__Vtemp242,127,0,4); + VL_SIGW(__Vtemp243,127,0,4); + VL_SIGW(__Vtemp244,127,0,4); + VL_SIGW(__Vtemp245,127,0,4); + VL_SIGW(__Vtemp246,127,0,4); + VL_SIGW(__Vtemp247,127,0,4); + VL_SIGW(__Vtemp248,127,0,4); + VL_SIGW(__Vtemp249,127,0,4); + VL_SIGW(__Vtemp250,127,0,4); + VL_SIGW(__Vtemp251,127,0,4); + VL_SIGW(__Vtemp252,127,0,4); + VL_SIGW(__Vtemp253,127,0,4); + VL_SIGW(__Vtemp254,127,0,4); + VL_SIGW(__Vtemp255,127,0,4); + VL_SIGW(__Vtemp256,127,0,4); + VL_SIGW(__Vtemp257,127,0,4); + VL_SIGW(__Vtemp258,127,0,4); + VL_SIGW(__Vtemp259,127,0,4); + VL_SIGW(__Vtemp260,127,0,4); + VL_SIGW(__Vtemp261,127,0,4); + VL_SIGW(__Vtemp262,127,0,4); + VL_SIGW(__Vtemp263,127,0,4); + VL_SIGW(__Vtemp264,127,0,4); + VL_SIGW(__Vtemp265,127,0,4); + VL_SIGW(__Vtemp266,127,0,4); + VL_SIGW(__Vtemp267,127,0,4); + VL_SIGW(__Vtemp268,127,0,4); + VL_SIGW(__Vtemp269,127,0,4); + VL_SIGW(__Vtemp270,127,0,4); + VL_SIGW(__Vtemp271,127,0,4); + VL_SIGW(__Vtemp272,127,0,4); + VL_SIGW(__Vtemp273,127,0,4); + VL_SIGW(__Vtemp274,127,0,4); + VL_SIGW(__Vtemp275,127,0,4); + VL_SIGW(__Vtemp276,127,0,4); + VL_SIGW(__Vtemp277,127,0,4); + VL_SIGW(__Vtemp278,127,0,4); + VL_SIGW(__Vtemp279,127,0,4); + VL_SIGW(__Vtemp280,127,0,4); + VL_SIGW(__Vtemp281,127,0,4); + VL_SIGW(__Vtemp282,127,0,4); + VL_SIGW(__Vtemp283,127,0,4); + VL_SIGW(__Vtemp284,127,0,4); + VL_SIGW(__Vtemp285,127,0,4); + VL_SIGW(__Vtemp286,127,0,4); + VL_SIGW(__Vtemp287,127,0,4); + VL_SIGW(__Vtemp288,127,0,4); + VL_SIGW(__Vtemp289,127,0,4); + VL_SIGW(__Vtemp290,127,0,4); + VL_SIGW(__Vtemp291,127,0,4); + VL_SIGW(__Vtemp292,127,0,4); + VL_SIGW(__Vtemp293,127,0,4); + VL_SIGW(__Vtemp294,127,0,4); + VL_SIGW(__Vtemp295,127,0,4); + VL_SIGW(__Vtemp296,127,0,4); + VL_SIGW(__Vtemp297,127,0,4); + VL_SIGW(__Vtemp298,127,0,4); + VL_SIGW(__Vtemp299,127,0,4); + VL_SIGW(__Vtemp300,127,0,4); + VL_SIGW(__Vtemp301,127,0,4); + VL_SIGW(__Vtemp302,127,0,4); + VL_SIGW(__Vtemp303,127,0,4); + VL_SIGW(__Vtemp304,127,0,4); + VL_SIGW(__Vtemp305,127,0,4); + VL_SIGW(__Vtemp306,127,0,4); + VL_SIGW(__Vtemp307,127,0,4); + VL_SIGW(__Vtemp308,127,0,4); + VL_SIGW(__Vtemp309,127,0,4); + VL_SIGW(__Vtemp310,127,0,4); + VL_SIGW(__Vtemp311,127,0,4); + VL_SIGW(__Vtemp312,127,0,4); + VL_SIGW(__Vtemp313,127,0,4); + VL_SIGW(__Vtemp314,127,0,4); + VL_SIGW(__Vtemp315,127,0,4); + VL_SIGW(__Vtemp316,127,0,4); + VL_SIGW(__Vtemp317,127,0,4); + VL_SIGW(__Vtemp318,127,0,4); + VL_SIGW(__Vtemp319,127,0,4); + VL_SIGW(__Vtemp320,127,0,4); + VL_SIGW(__Vtemp321,127,0,4); + VL_SIGW(__Vtemp322,127,0,4); + VL_SIGW(__Vtemp323,127,0,4); + VL_SIGW(__Vtemp324,127,0,4); + VL_SIGW(__Vtemp325,127,0,4); + VL_SIGW(__Vtemp326,127,0,4); + VL_SIGW(__Vtemp327,127,0,4); + VL_SIGW(__Vtemp328,127,0,4); + VL_SIGW(__Vtemp329,127,0,4); + VL_SIGW(__Vtemp330,127,0,4); + VL_SIGW(__Vtemp331,127,0,4); + VL_SIGW(__Vtemp332,127,0,4); + VL_SIGW(__Vtemp333,127,0,4); + VL_SIGW(__Vtemp334,127,0,4); + VL_SIGW(__Vtemp335,127,0,4); + VL_SIGW(__Vtemp336,127,0,4); + VL_SIGW(__Vtemp337,127,0,4); + VL_SIGW(__Vtemp338,127,0,4); + VL_SIGW(__Vtemp339,127,0,4); + VL_SIGW(__Vtemp340,127,0,4); + VL_SIGW(__Vtemp341,127,0,4); + VL_SIGW(__Vtemp342,127,0,4); + VL_SIGW(__Vtemp343,127,0,4); + VL_SIGW(__Vtemp344,127,0,4); + VL_SIGW(__Vtemp345,127,0,4); + VL_SIGW(__Vtemp346,127,0,4); + VL_SIGW(__Vtemp347,127,0,4); + VL_SIGW(__Vtemp348,127,0,4); + VL_SIGW(__Vtemp349,127,0,4); + VL_SIGW(__Vtemp350,127,0,4); + VL_SIGW(__Vtemp351,127,0,4); + VL_SIGW(__Vtemp352,127,0,4); + VL_SIGW(__Vtemp353,127,0,4); + VL_SIGW(__Vtemp354,127,0,4); + VL_SIGW(__Vtemp355,127,0,4); + VL_SIGW(__Vtemp356,127,0,4); + VL_SIGW(__Vtemp357,127,0,4); + VL_SIGW(__Vtemp358,127,0,4); + VL_SIGW(__Vtemp359,127,0,4); + VL_SIGW(__Vtemp360,127,0,4); + VL_SIGW(__Vtemp361,127,0,4); + VL_SIGW(__Vtemp362,127,0,4); + VL_SIGW(__Vtemp363,127,0,4); + VL_SIGW(__Vtemp364,127,0,4); + VL_SIGW(__Vtemp365,127,0,4); + VL_SIGW(__Vtemp366,127,0,4); + VL_SIGW(__Vtemp367,127,0,4); + VL_SIGW(__Vtemp368,127,0,4); + VL_SIGW(__Vtemp369,127,0,4); + VL_SIGW(__Vtemp370,127,0,4); + VL_SIGW(__Vtemp371,127,0,4); + VL_SIGW(__Vtemp372,127,0,4); + VL_SIGW(__Vtemp373,127,0,4); + VL_SIGW(__Vtemp374,127,0,4); + VL_SIGW(__Vtemp375,127,0,4); + VL_SIGW(__Vtemp376,127,0,4); + VL_SIGW(__Vtemp377,127,0,4); + VL_SIGW(__Vtemp378,127,0,4); + VL_SIGW(__Vtemp379,127,0,4); + VL_SIGW(__Vtemp380,127,0,4); + VL_SIGW(__Vtemp381,127,0,4); + VL_SIGW(__Vtemp382,127,0,4); + VL_SIGW(__Vtemp383,127,0,4); + VL_SIGW(__Vtemp384,127,0,4); + VL_SIGW(__Vtemp385,127,0,4); + VL_SIGW(__Vtemp386,127,0,4); + VL_SIGW(__Vtemp387,127,0,4); + VL_SIGW(__Vtemp388,127,0,4); + VL_SIGW(__Vtemp389,127,0,4); + VL_SIGW(__Vtemp390,127,0,4); + VL_SIGW(__Vtemp391,127,0,4); + VL_SIGW(__Vtemp392,127,0,4); + VL_SIGW(__Vtemp393,127,0,4); + VL_SIGW(__Vtemp394,127,0,4); + VL_SIGW(__Vtemp395,127,0,4); + VL_SIGW(__Vtemp396,127,0,4); + VL_SIGW(__Vtemp397,127,0,4); + VL_SIGW(__Vtemp398,127,0,4); + VL_SIGW(__Vtemp399,127,0,4); + VL_SIGW(__Vtemp400,127,0,4); + VL_SIGW(__Vtemp401,127,0,4); + VL_SIGW(__Vtemp402,127,0,4); + VL_SIGW(__Vtemp403,127,0,4); + VL_SIGW(__Vtemp404,127,0,4); + VL_SIGW(__Vtemp405,127,0,4); + VL_SIGW(__Vtemp406,127,0,4); + VL_SIGW(__Vtemp407,127,0,4); + VL_SIGW(__Vtemp408,127,0,4); + VL_SIGW(__Vtemp409,127,0,4); + VL_SIGW(__Vtemp410,127,0,4); + VL_SIGW(__Vtemp411,127,0,4); + VL_SIGW(__Vtemp412,127,0,4); + VL_SIGW(__Vtemp413,127,0,4); + VL_SIGW(__Vtemp414,127,0,4); + VL_SIGW(__Vtemp415,127,0,4); + VL_SIGW(__Vtemp416,127,0,4); + VL_SIGW(__Vtemp417,127,0,4); + VL_SIGW(__Vtemp418,127,0,4); + VL_SIGW(__Vtemp419,127,0,4); + VL_SIGW(__Vtemp420,127,0,4); + VL_SIGW(__Vtemp421,127,0,4); + VL_SIGW(__Vtemp422,127,0,4); + VL_SIGW(__Vtemp423,127,0,4); + VL_SIGW(__Vtemp424,127,0,4); + VL_SIGW(__Vtemp425,127,0,4); + VL_SIGW(__Vtemp426,127,0,4); + VL_SIGW(__Vtemp427,127,0,4); + VL_SIGW(__Vtemp428,127,0,4); + VL_SIGW(__Vtemp429,127,0,4); + VL_SIGW(__Vtemp430,127,0,4); + VL_SIGW(__Vtemp431,127,0,4); + VL_SIGW(__Vtemp432,127,0,4); + VL_SIGW(__Vtemp433,127,0,4); + VL_SIGW(__Vtemp434,127,0,4); + VL_SIGW(__Vtemp435,127,0,4); + VL_SIGW(__Vtemp436,127,0,4); + VL_SIGW(__Vtemp437,127,0,4); + VL_SIGW(__Vtemp438,127,0,4); + VL_SIGW(__Vtemp439,127,0,4); + VL_SIGW(__Vtemp440,127,0,4); + VL_SIGW(__Vtemp441,127,0,4); + VL_SIGW(__Vtemp442,127,0,4); + VL_SIGW(__Vtemp443,127,0,4); + VL_SIGW(__Vtemp444,127,0,4); + VL_SIGW(__Vtemp445,127,0,4); + VL_SIGW(__Vtemp446,127,0,4); + VL_SIGW(__Vtemp447,127,0,4); + VL_SIGW(__Vtemp448,127,0,4); + VL_SIGW(__Vtemp449,127,0,4); + VL_SIGW(__Vtemp450,127,0,4); + VL_SIGW(__Vtemp451,127,0,4); + VL_SIGW(__Vtemp452,127,0,4); + VL_SIGW(__Vtemp453,127,0,4); + VL_SIGW(__Vtemp454,127,0,4); + VL_SIGW(__Vtemp455,127,0,4); + VL_SIGW(__Vtemp456,127,0,4); + VL_SIGW(__Vtemp457,127,0,4); + VL_SIGW(__Vtemp458,127,0,4); + VL_SIGW(__Vtemp459,127,0,4); + VL_SIGW(__Vtemp460,127,0,4); + VL_SIGW(__Vtemp461,127,0,4); + VL_SIGW(__Vtemp462,127,0,4); + VL_SIGW(__Vtemp463,127,0,4); + VL_SIGW(__Vtemp464,127,0,4); + VL_SIGW(__Vtemp465,127,0,4); + VL_SIGW(__Vtemp466,127,0,4); + VL_SIGW(__Vtemp467,127,0,4); + VL_SIGW(__Vtemp468,127,0,4); + VL_SIGW(__Vtemp469,127,0,4); + VL_SIGW(__Vtemp470,127,0,4); + VL_SIGW(__Vtemp471,127,0,4); + VL_SIGW(__Vtemp472,127,0,4); + VL_SIGW(__Vtemp473,127,0,4); + VL_SIGW(__Vtemp474,127,0,4); + VL_SIGW(__Vtemp475,127,0,4); + VL_SIGW(__Vtemp476,127,0,4); + VL_SIGW(__Vtemp477,127,0,4); + VL_SIGW(__Vtemp478,127,0,4); + VL_SIGW(__Vtemp479,127,0,4); + VL_SIGW(__Vtemp480,127,0,4); + VL_SIGW(__Vtemp481,127,0,4); + VL_SIGW(__Vtemp482,127,0,4); + VL_SIGW(__Vtemp483,127,0,4); + VL_SIGW(__Vtemp484,127,0,4); + VL_SIGW(__Vtemp485,127,0,4); + VL_SIGW(__Vtemp486,127,0,4); + VL_SIGW(__Vtemp487,127,0,4); + VL_SIGW(__Vtemp488,127,0,4); + VL_SIGW(__Vtemp489,127,0,4); + VL_SIGW(__Vtemp490,127,0,4); + VL_SIGW(__Vtemp491,127,0,4); + VL_SIGW(__Vtemp492,127,0,4); + VL_SIGW(__Vtemp493,127,0,4); + VL_SIGW(__Vtemp494,127,0,4); + VL_SIGW(__Vtemp495,127,0,4); + VL_SIGW(__Vtemp496,127,0,4); + VL_SIGW(__Vtemp497,127,0,4); + VL_SIGW(__Vtemp498,127,0,4); + VL_SIGW(__Vtemp499,127,0,4); + VL_SIGW(__Vtemp500,127,0,4); + VL_SIGW(__Vtemp501,127,0,4); + VL_SIGW(__Vtemp502,127,0,4); + VL_SIGW(__Vtemp503,127,0,4); + VL_SIGW(__Vtemp504,127,0,4); + VL_SIGW(__Vtemp505,127,0,4); + VL_SIGW(__Vtemp506,127,0,4); + VL_SIGW(__Vtemp507,127,0,4); + VL_SIGW(__Vtemp508,127,0,4); + VL_SIGW(__Vtemp509,127,0,4); + VL_SIGW(__Vtemp510,127,0,4); + VL_SIGW(__Vtemp511,127,0,4); + VL_SIGW(__Vtemp512,127,0,4); + VL_SIGW(__Vtemp513,127,0,4); + VL_SIGW(__Vtemp514,127,0,4); + VL_SIGW(__Vtemp515,127,0,4); + VL_SIGW(__Vtemp516,127,0,4); + VL_SIGW(__Vtemp517,127,0,4); + VL_SIGW(__Vtemp518,127,0,4); + VL_SIGW(__Vtemp519,127,0,4); + VL_SIGW(__Vtemp520,127,0,4); + VL_SIGW(__Vtemp521,127,0,4); + VL_SIGW(__Vtemp522,127,0,4); + VL_SIGW(__Vtemp523,127,0,4); + VL_SIGW(__Vtemp524,127,0,4); + VL_SIGW(__Vtemp525,127,0,4); + VL_SIGW(__Vtemp526,127,0,4); + VL_SIGW(__Vtemp527,127,0,4); + VL_SIGW(__Vtemp528,127,0,4); + VL_SIGW(__Vtemp529,127,0,4); + VL_SIGW(__Vtemp530,127,0,4); + VL_SIGW(__Vtemp531,127,0,4); + VL_SIGW(__Vtemp532,127,0,4); + VL_SIGW(__Vtemp533,127,0,4); + VL_SIGW(__Vtemp534,127,0,4); + VL_SIGW(__Vtemp535,127,0,4); + VL_SIGW(__Vtemp536,127,0,4); + VL_SIGW(__Vtemp146,127,0,4); + VL_SIGW(__Vtemp147,127,0,4); + VL_SIGW(__Vtemp148,127,0,4); + VL_SIGW(__Vtemp149,127,0,4); + VL_SIGW(__Vtemp150,127,0,4); + VL_SIGW(__Vtemp151,127,0,4); + VL_SIGW(__Vtemp152,127,0,4); + VL_SIGW(__Vtemp157,127,0,4); + VL_SIGW(__Vtemp158,127,0,4); + VL_SIGW(__Vtemp159,127,0,4); + VL_SIGW(__Vtemp160,127,0,4); + VL_SIGW(__Vtemp161,127,0,4); + VL_SIGW(__Vtemp162,127,0,4); + VL_SIGW(__Vtemp163,127,0,4); + VL_SIGW(__Vtemp164,127,0,4); + VL_SIGW(__Vtemp165,127,0,4); + VL_SIGW(__Vtemp166,127,0,4); + VL_SIGW(__Vtemp167,127,0,4); + VL_SIGW(__Vtemp168,127,0,4); + VL_SIGW(__Vtemp169,127,0,4); + VL_SIGW(__Vtemp170,127,0,4); + VL_SIGW(__Vtemp171,127,0,4); + VL_SIGW(__Vtemp172,127,0,4); + VL_SIGW(__Vtemp173,127,0,4); + VL_SIGW(__Vtemp174,127,0,4); + VL_SIGW(__Vtemp175,127,0,4); + VL_SIGW(__Vtemp176,127,0,4); + VL_SIGW(__Vtemp177,127,0,4); + VL_SIGW(__Vtemp178,127,0,4); + VL_SIGW(__Vtemp179,127,0,4); + VL_SIGW(__Vtemp180,127,0,4); + VL_SIGW(__Vtemp181,127,0,4); + VL_SIGW(__Vtemp182,127,0,4); + VL_SIGW(__Vtemp183,127,0,4); + VL_SIGW(__Vtemp184,127,0,4); + VL_SIGW(__Vtemp185,127,0,4); + VL_SIGW(__Vtemp186,127,0,4); + VL_SIGW(__Vtemp187,127,0,4); + VL_SIGW(__Vtemp188,127,0,4); + VL_SIGW(__Vtemp189,127,0,4); + VL_SIGW(__Vtemp190,127,0,4); + VL_SIGW(__Vtemp191,127,0,4); + VL_SIGW(__Vtemp192,127,0,4); + VL_SIGW(__Vtemp193,127,0,4); + VL_SIGW(__Vtemp196,127,0,4); + VL_SIGW(__Vtemp199,127,0,4); + VL_SIGW(__Vtemp202,127,0,4); + VL_SIGW(__Vtemp205,127,0,4); + VL_SIGW(__Vtemp206,127,0,4); + VL_SIGW(__Vtemp537,127,0,4); + VL_SIGW(__Vtemp538,127,0,4); + VL_SIGW(__Vtemp539,127,0,4); + VL_SIGW(__Vtemp540,127,0,4); + VL_SIGW(__Vtemp541,127,0,4); + // Body + { + vcdp->fullBit (c+1,((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))))); + vcdp->fullBus (c+2,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid),4); + vcdp->fullBus (c+3,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid),4); + vcdp->fullBit (c+4,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__read_or_write)); + vcdp->fullArray(c+5,(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address),128); + vcdp->fullBus (c+9,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read),3); + vcdp->fullBus (c+10,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write),3); + vcdp->fullBus (c+11,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read),3); + vcdp->fullBus (c+12,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write),3); + vcdp->fullArray(c+13,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual),128); + __Vtemp146[0U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[0U] + : 0U); + __Vtemp146[1U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[1U] + : 0U); + __Vtemp146[2U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[2U] + : 0U); + __Vtemp146[3U] = (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[3U] + : 0U); + vcdp->fullArray(c+17,(__Vtemp146),128); + vcdp->fullBus (c+21,((0xfU & (((~ (IData)( + (0U + != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid) + : 0U))),4); + vcdp->fullBit (c+22,((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))); + vcdp->fullBus (c+23,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read),3); + vcdp->fullArray(c+24,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address),128); + vcdp->fullArray(c+28,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data),128); + vcdp->fullBus (c+32,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid),4); + vcdp->fullBus (c+33,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid),4); + vcdp->fullArray(c+34,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data),128); + vcdp->fullBus (c+38,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr),28); + vcdp->fullArray(c+39,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata),512); + vcdp->fullArray(c+55,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata),512); + vcdp->fullBus (c+71,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we),8); + vcdp->fullBit (c+72,(((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))))); + vcdp->fullBus (c+73,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num),12); + vcdp->fullBus (c+74,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid),4); + vcdp->fullBit (c+75,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write)); + vcdp->fullBit (c+76,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write)); + vcdp->fullBit (c+77,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write)); + vcdp->fullBit (c+78,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write)); + vcdp->fullBus (c+79,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced),4); + vcdp->fullBus (c+80,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid),4); + vcdp->fullBus (c+81,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids),16); + vcdp->fullBus (c+82,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid),4); + vcdp->fullBus (c+83,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num),8); + vcdp->fullBus (c+84,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual),4); + vcdp->fullBus (c+85,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids),3); + vcdp->fullBus (c+86,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids),3); + vcdp->fullBus (c+87,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids),3); + vcdp->fullBus (c+88,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids),3); + vcdp->fullBus (c+89,((0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids))),4); + vcdp->fullBus (c+90,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 4U))),4); + vcdp->fullBus (c+91,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 8U))),4); + vcdp->fullBus (c+92,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids) + >> 0xcU))),4); + vcdp->fullBus (c+93,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index),2); + vcdp->fullBit (c+94,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found)); + vcdp->fullBus (c+95,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i),32); + vcdp->fullBus (c+96,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index),2); + vcdp->fullBit (c+97,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found)); + vcdp->fullBus (c+98,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i),32); + vcdp->fullBus (c+99,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index),2); + vcdp->fullBit (c+100,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found)); + vcdp->fullBus (c+101,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i),32); + vcdp->fullBus (c+102,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index),2); + vcdp->fullBit (c+103,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found)); + vcdp->fullBus (c+104,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i),32); + vcdp->fullBus (c+105,((0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)),7); + __Vtemp147[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0U]; + __Vtemp147[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[1U]; + __Vtemp147[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[2U]; + __Vtemp147[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[3U]; + vcdp->fullArray(c+106,(__Vtemp147),128); + vcdp->fullBus (c+110,((3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we))),2); + vcdp->fullBus (c+111,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))),7); + __Vtemp148[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[4U]; + __Vtemp148[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[5U]; + __Vtemp148[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[6U]; + __Vtemp148[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[7U]; + vcdp->fullArray(c+112,(__Vtemp148),128); + vcdp->fullBus (c+116,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 2U))),2); + vcdp->fullBus (c+117,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))),7); + __Vtemp149[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[8U]; + __Vtemp149[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[9U]; + __Vtemp149[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xaU]; + __Vtemp149[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xbU]; + vcdp->fullArray(c+118,(__Vtemp149),128); + vcdp->fullBus (c+122,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 4U))),2); + vcdp->fullBus (c+123,((0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))),7); + __Vtemp150[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xcU]; + __Vtemp150[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xdU]; + __Vtemp150[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xeU]; + __Vtemp150[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata[0xfU]; + vcdp->fullArray(c+124,(__Vtemp150),128); + vcdp->fullBus (c+128,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we) + >> 6U))),2); + vcdp->fullBus (c+129,((0xffffffc0U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank[0U])),32); + vcdp->fullArray(c+130,(vlTOPp->cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata),512); + vcdp->fullArray(c+146,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read),128); + vcdp->fullBus (c+150,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks),16); + vcdp->fullBus (c+151,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank),8); + vcdp->fullBus (c+152,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank),16); + vcdp->fullBus (c+153,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank),4); + vcdp->fullBus (c+154,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank),16); + vcdp->fullArray(c+155,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank),128); + vcdp->fullBus (c+159,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank),4); + vcdp->fullBus (c+160,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb),4); + vcdp->fullBus (c+161,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state),4); + vcdp->fullBus (c+162,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid),4); + vcdp->fullBus (c+163,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid),4); + vcdp->fullArray(c+164,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank),128); + vcdp->fullBit (c+168,((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid)))); + vcdp->fullBus (c+169,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual),4); + vcdp->fullBus (c+170,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[0]),4); + vcdp->fullBus (c+171,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[1]),4); + vcdp->fullBus (c+172,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[2]),4); + vcdp->fullBus (c+173,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[3]),4); + vcdp->fullBus (c+174,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss),4); + vcdp->fullBus (c+175,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index),2); + vcdp->fullBit (c+176,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found)); + vcdp->fullBus (c+177,((0xfU & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks))),4); + vcdp->fullBus (c+178,((3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))),2); + vcdp->fullBit (c+179,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank)))); + vcdp->fullBus (c+180,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[0U]),32); + vcdp->fullBus (c+181,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 4U))),4); + vcdp->fullBus (c+182,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))),2); + vcdp->fullBit (c+183,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) + >> 1U)))); + vcdp->fullBus (c+184,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[1U]),32); + vcdp->fullBus (c+185,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 8U))),4); + vcdp->fullBus (c+186,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))),2); + vcdp->fullBit (c+187,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) + >> 2U)))); + vcdp->fullBus (c+188,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[2U]),32); + vcdp->fullBus (c+189,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks) + >> 0xcU))),4); + vcdp->fullBus (c+190,((3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))),2); + vcdp->fullBit (c+191,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank) + >> 3U)))); + vcdp->fullBus (c+192,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank[3U]),32); + vcdp->fullBus (c+193,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr),32); + vcdp->fullBus (c+194,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)),2); + vcdp->fullBus (c+195,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU))),21); + vcdp->fullBit (c+196,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank)))); + vcdp->fullBit (c+197,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + vcdp->fullBus (c+198,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr),32); + vcdp->fullBus (c+199,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)),2); + vcdp->fullBus (c+200,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU))),21); + vcdp->fullBit (c+201,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 1U)))); + vcdp->fullBit (c+202,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in)); + vcdp->fullBus (c+203,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr),32); + vcdp->fullBus (c+204,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)),2); + vcdp->fullBus (c+205,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU))),21); + vcdp->fullBit (c+206,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 2U)))); + vcdp->fullBit (c+207,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in)); + vcdp->fullBus (c+208,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr),32); + vcdp->fullBus (c+209,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)),2); + vcdp->fullBus (c+210,((0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU))),21); + vcdp->fullBit (c+211,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank) + >> 3U)))); + vcdp->fullBit (c+212,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in)); + vcdp->fullBus (c+213,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i),32); + vcdp->fullBus (c+214,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found) + ? ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index)) + : 0U))),4); + vcdp->fullBus (c+215,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index),2); + vcdp->fullBit (c+216,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found)); + vcdp->fullBus (c+217,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i),32); + vcdp->fullBus (c+218,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found) + ? ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index)) + : 0U))),4); + vcdp->fullBus (c+219,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index),2); + vcdp->fullBit (c+220,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found)); + vcdp->fullBus (c+221,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i),32); + vcdp->fullBus (c+222,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found) + ? ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index)) + : 0U))),4); + vcdp->fullBus (c+223,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index),2); + vcdp->fullBit (c+224,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found)); + vcdp->fullBus (c+225,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i),32); + vcdp->fullBus (c+226,((0xfU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found) + ? ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index)) + : 0U))),4); + vcdp->fullBus (c+227,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index),2); + vcdp->fullBit (c+228,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found)); + vcdp->fullBus (c+229,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i),32); + vcdp->fullBus (c+230,((0xfffffff0U & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + << 9U))),32); + vcdp->fullBus (c+231,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read),32); + vcdp->fullBus (c+232,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks),1); + vcdp->fullBus (c+233,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index),1); + vcdp->fullBus (c+234,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank) + ? ((IData)(1U) + << (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index)) + : 0U))),1); + vcdp->fullBus (c+235,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank),1); + vcdp->fullBus (c+236,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank),1); + vcdp->fullBus (c+237,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffffff00U + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x8000U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffff0000U + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : ((4U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? + (0xffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)))) + : 0U)),32); + vcdp->fullBus (c+238,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank),1); + vcdp->fullBus (c+239,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state),4); + vcdp->fullBus (c+240,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid),1); + vcdp->fullBus (c+241,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid),1); + vcdp->fullBus (c+242,((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + << 9U)),32); + vcdp->fullBus (c+243,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank),1); + vcdp->fullBus (c+244,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[0]),1); + vcdp->fullBus (c+245,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss),1); + vcdp->fullBus (c+246,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index),1); + vcdp->fullBit (c+247,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found)); + vcdp->fullBit (c+248,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank)); + vcdp->fullBus (c+249,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr),32); + vcdp->fullBus (c+250,((3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)),2); + vcdp->fullBus (c+251,((0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U))),23); + vcdp->fullBit (c+252,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank)); + vcdp->fullBit (c+253,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)); + vcdp->fullBus (c+254,(0U),32); + vcdp->fullBus (c+255,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use),23); + vcdp->fullBit (c+256,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use)); + vcdp->fullBit (c+257,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access)); + vcdp->fullBit (c+258,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem)); + vcdp->fullBit (c+259,((((vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use + != (0x7fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 9U))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)))); + vcdp->fullBit (c+260,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->fullBit (c+261,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->fullBit (c+262,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->fullBit (c+263,((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->fullBit (c+264,((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)))); + vcdp->fullBit (c+265,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->fullBit (c+266,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->fullBit (c+267,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->fullBit (c+268,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->fullBus (c+269,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual),32); + vcdp->fullBus (c+270,(((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffffff00U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))),32); + vcdp->fullBus (c+271,(((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffff0000U | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))),32); + vcdp->fullBus (c+272,((0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)),32); + vcdp->fullBus (c+273,((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)),32); + vcdp->fullBus (c+274,(0U),32); + vcdp->fullBus (c+275,(0U),32); + vcdp->fullBus (c+276,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x80U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffffff00U + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? ((0x8000U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + ? (0xffff0000U + | vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : (0xffffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read)) + ? (0xffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual) + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual))))),32); + vcdp->fullBus (c+277,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 1U : ((1U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 2U : ((2U + == + (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 4U + : 8U)))),4); + vcdp->fullBus (c+278,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->fullBus (c+279,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we),16); + vcdp->fullArray(c+280,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write),128); + vcdp->fullBus (c+284,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way),2); + vcdp->fullBus (c+285,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way),32); + vcdp->fullArray(c+286,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way),256); + vcdp->fullBus (c+294,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->fullBus (c+295,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index),1); + vcdp->fullBus (c+296,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual),1); + vcdp->fullBit (c+297,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->fullBus (c+298,((0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)),16); + vcdp->fullBit (c+299,((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp151[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp151[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp151[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp151[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[3U]; + vcdp->fullArray(c+300,(__Vtemp151),128); + vcdp->fullBit (c+304,((0U != (0xffffU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)))); + vcdp->fullBit (c+305,((1U & ((1U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way)))))); + vcdp->fullBus (c+306,((0xffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->fullBit (c+307,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp152[0U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp152[1U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp152[2U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp152[3U] = vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way[7U]; + vcdp->fullArray(c+308,(__Vtemp152),128); + vcdp->fullBit (c+312,((0U != (0xffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->fullBit (c+313,((1U & ((2U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way + >> 0x10U))))))); + vcdp->fullBus (c+314,(vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_valid),4); + __Vtemp157[0U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))) + ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[0U] + : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[0U]); + __Vtemp157[1U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))) + ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[1U] + : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[1U]); + __Vtemp157[2U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))) + ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[2U] + : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[2U]); + __Vtemp157[3U] = ((0xffU == (0xffU & ((vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[1U] + << 8U) + | (vlSymsp->TOP__cache_simX__DOT__VX_dcache_req.out_cache_driver_in_address[0U] + >> 0x18U)))) + ? (((~ (IData)((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid)))) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid))) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data[3U] + : 0U) : vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual[3U]); + vcdp->fullArray(c+315,(__Vtemp157),128); + __Vtemp158[0U] = 0U; + __Vtemp158[1U] = 0U; + __Vtemp158[2U] = 0U; + __Vtemp158[3U] = 0U; + vcdp->fullBus (c+319,(__Vtemp158[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))]),32); + vcdp->fullBus (c+320,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? + (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U)),32); + vcdp->fullBit (c+321,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU)))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use)))); + vcdp->fullBus (c+322,((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU)),32); + vcdp->fullArray(c+323,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128); + vcdp->fullBus (c+327,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use),21); + vcdp->fullBit (c+328,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use)); + vcdp->fullBit (c+329,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__access)); + vcdp->fullBit (c+330,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__write_from_mem)); + vcdp->fullBit (c+331,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__tag_use + != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in)))); + vcdp->fullBit (c+332,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->fullBit (c+333,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->fullBit (c+334,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->fullBit (c+335,((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->fullBit (c+336,((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)))); + vcdp->fullBit (c+337,((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))); + vcdp->fullBit (c+338,((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))); + vcdp->fullBit (c+339,((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write)))); + vcdp->fullBit (c+340,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->fullBit (c+341,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->fullBit (c+342,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->fullBit (c+343,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)))); + vcdp->fullBus (c+344,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual),32); + vcdp->fullBus (c+345,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->fullBus (c+346,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->fullBus (c+347,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32); + vcdp->fullBus (c+348,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)),32); + __Vtemp159[0U] = 0U; + __Vtemp159[1U] = 0U; + __Vtemp159[2U] = 0U; + __Vtemp159[3U] = 0U; + __Vtemp160[0U] = 0U; + __Vtemp160[1U] = 0U; + __Vtemp160[2U] = 0U; + __Vtemp160[3U] = 0U; + __Vtemp161[0U] = 0U; + __Vtemp161[1U] = 0U; + __Vtemp161[2U] = 0U; + __Vtemp161[3U] = 0U; + __Vtemp162[0U] = 0U; + __Vtemp162[1U] = 0U; + __Vtemp162[2U] = 0U; + __Vtemp162[3U] = 0U; + vcdp->fullBus (c+349,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff00U & (__Vtemp159[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 8U)) + : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff0000U & + (__Vtemp160[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x10U)) + : ((3U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp161[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x18U)) + : __Vtemp162[ + (3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])))),32); + __Vtemp163[0U] = 0U; + __Vtemp163[1U] = 0U; + __Vtemp163[2U] = 0U; + __Vtemp163[3U] = 0U; + __Vtemp164[0U] = 0U; + __Vtemp164[1U] = 0U; + __Vtemp164[2U] = 0U; + __Vtemp164[3U] = 0U; + vcdp->fullBus (c+350,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? (0xffff0000U & ( + __Vtemp163[ + (3U + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))] + << 0x10U)) + : __Vtemp164[(3U & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank))])),32); + vcdp->fullBus (c+351,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__use_write_data),32); + vcdp->fullBus (c+352,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_unQual))))),32); + vcdp->fullBus (c+353,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__sb_mask),4); + vcdp->fullBus (c+354,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->fullBus (c+355,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__we),16); + vcdp->fullArray(c+356,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_write),128); + vcdp->fullBit (c+360,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write)); + vcdp->fullBus (c+361,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2); + vcdp->fullBus (c+362,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32); + vcdp->fullArray(c+363,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256); + vcdp->fullBus (c+371,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->fullBus (c+372,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1); + vcdp->fullBus (c+373,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1); + vcdp->fullBit (c+374,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->fullBus (c+375,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16); + vcdp->fullBit (c+376,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp165[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp165[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp165[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp165[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U]; + vcdp->fullArray(c+377,(__Vtemp165),128); + vcdp->fullBit (c+381,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))); + vcdp->fullBit (c+382,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))))); + vcdp->fullBus (c+383,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->fullBit (c+384,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp166[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp166[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp166[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp166[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U]; + vcdp->fullArray(c+385,(__Vtemp166),128); + vcdp->fullBit (c+389,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->fullBit (c+390,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))))); + __Vtemp167[0U] = 0U; + __Vtemp167[1U] = 0U; + __Vtemp167[2U] = 0U; + __Vtemp167[3U] = 0U; + vcdp->fullBus (c+391,(__Vtemp167[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))]),32); + vcdp->fullBus (c+392,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? + (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U)),32); + vcdp->fullBit (c+393,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU)))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use)))); + vcdp->fullBus (c+394,((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU)),32); + vcdp->fullArray(c+395,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128); + vcdp->fullBus (c+399,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use),21); + vcdp->fullBit (c+400,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use)); + vcdp->fullBit (c+401,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__access)); + vcdp->fullBit (c+402,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__write_from_mem)); + vcdp->fullBit (c+403,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__tag_use + != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in)))); + vcdp->fullBit (c+404,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)))); + vcdp->fullBit (c+405,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)))); + vcdp->fullBit (c+406,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)))); + vcdp->fullBit (c+407,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)))); + vcdp->fullBus (c+408,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual),32); + vcdp->fullBus (c+409,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->fullBus (c+410,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->fullBus (c+411,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32); + vcdp->fullBus (c+412,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)),32); + __Vtemp168[0U] = 0U; + __Vtemp168[1U] = 0U; + __Vtemp168[2U] = 0U; + __Vtemp168[3U] = 0U; + __Vtemp169[0U] = 0U; + __Vtemp169[1U] = 0U; + __Vtemp169[2U] = 0U; + __Vtemp169[3U] = 0U; + __Vtemp170[0U] = 0U; + __Vtemp170[1U] = 0U; + __Vtemp170[2U] = 0U; + __Vtemp170[3U] = 0U; + __Vtemp171[0U] = 0U; + __Vtemp171[1U] = 0U; + __Vtemp171[2U] = 0U; + __Vtemp171[3U] = 0U; + vcdp->fullBus (c+413,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff00U & (__Vtemp168[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 8U)) + : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff0000U & + (__Vtemp169[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x10U)) + : ((3U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp170[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x18U)) + : __Vtemp171[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))])))),32); + __Vtemp172[0U] = 0U; + __Vtemp172[1U] = 0U; + __Vtemp172[2U] = 0U; + __Vtemp172[3U] = 0U; + __Vtemp173[0U] = 0U; + __Vtemp173[1U] = 0U; + __Vtemp173[2U] = 0U; + __Vtemp173[3U] = 0U; + vcdp->fullBus (c+414,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? (0xffff0000U & ( + __Vtemp172[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))] + << 0x10U)) + : __Vtemp173[(3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 2U))])),32); + vcdp->fullBus (c+415,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__use_write_data),32); + vcdp->fullBus (c+416,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_unQual))))),32); + vcdp->fullBus (c+417,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__sb_mask),4); + vcdp->fullBus (c+418,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->fullBus (c+419,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__we),16); + vcdp->fullArray(c+420,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_write),128); + vcdp->fullBit (c+424,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write)); + vcdp->fullBus (c+425,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2); + vcdp->fullBus (c+426,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32); + vcdp->fullArray(c+427,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256); + vcdp->fullBus (c+435,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->fullBus (c+436,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1); + vcdp->fullBus (c+437,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1); + vcdp->fullBit (c+438,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->fullBus (c+439,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16); + vcdp->fullBit (c+440,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp174[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp174[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp174[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp174[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U]; + vcdp->fullArray(c+441,(__Vtemp174),128); + vcdp->fullBit (c+445,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))); + vcdp->fullBit (c+446,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))))); + vcdp->fullBus (c+447,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->fullBit (c+448,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp175[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp175[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp175[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp175[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U]; + vcdp->fullArray(c+449,(__Vtemp175),128); + vcdp->fullBit (c+453,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->fullBit (c+454,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))))); + __Vtemp176[0U] = 0U; + __Vtemp176[1U] = 0U; + __Vtemp176[2U] = 0U; + __Vtemp176[3U] = 0U; + vcdp->fullBus (c+455,(__Vtemp176[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))]),32); + vcdp->fullBus (c+456,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? + (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U)),32); + vcdp->fullBit (c+457,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU)))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use)))); + vcdp->fullBus (c+458,((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU)),32); + vcdp->fullArray(c+459,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128); + vcdp->fullBus (c+463,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use),21); + vcdp->fullBit (c+464,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use)); + vcdp->fullBit (c+465,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__access)); + vcdp->fullBit (c+466,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__write_from_mem)); + vcdp->fullBit (c+467,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__tag_use + != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in)))); + vcdp->fullBit (c+468,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)))); + vcdp->fullBit (c+469,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)))); + vcdp->fullBit (c+470,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)))); + vcdp->fullBit (c+471,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)))); + vcdp->fullBus (c+472,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual),32); + vcdp->fullBus (c+473,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->fullBus (c+474,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->fullBus (c+475,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32); + vcdp->fullBus (c+476,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)),32); + __Vtemp177[0U] = 0U; + __Vtemp177[1U] = 0U; + __Vtemp177[2U] = 0U; + __Vtemp177[3U] = 0U; + __Vtemp178[0U] = 0U; + __Vtemp178[1U] = 0U; + __Vtemp178[2U] = 0U; + __Vtemp178[3U] = 0U; + __Vtemp179[0U] = 0U; + __Vtemp179[1U] = 0U; + __Vtemp179[2U] = 0U; + __Vtemp179[3U] = 0U; + __Vtemp180[0U] = 0U; + __Vtemp180[1U] = 0U; + __Vtemp180[2U] = 0U; + __Vtemp180[3U] = 0U; + vcdp->fullBus (c+477,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff00U & (__Vtemp177[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 8U)) + : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff0000U & + (__Vtemp178[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x10U)) + : ((3U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp179[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x18U)) + : __Vtemp180[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))])))),32); + __Vtemp181[0U] = 0U; + __Vtemp181[1U] = 0U; + __Vtemp181[2U] = 0U; + __Vtemp181[3U] = 0U; + __Vtemp182[0U] = 0U; + __Vtemp182[1U] = 0U; + __Vtemp182[2U] = 0U; + __Vtemp182[3U] = 0U; + vcdp->fullBus (c+478,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? (0xffff0000U & ( + __Vtemp181[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))] + << 0x10U)) + : __Vtemp182[(3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 4U))])),32); + vcdp->fullBus (c+479,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__use_write_data),32); + vcdp->fullBus (c+480,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_unQual))))),32); + vcdp->fullBus (c+481,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__sb_mask),4); + vcdp->fullBus (c+482,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->fullBus (c+483,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__we),16); + vcdp->fullArray(c+484,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_write),128); + vcdp->fullBit (c+488,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write)); + vcdp->fullBus (c+489,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2); + vcdp->fullBus (c+490,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32); + vcdp->fullArray(c+491,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256); + vcdp->fullBus (c+499,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->fullBus (c+500,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1); + vcdp->fullBus (c+501,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1); + vcdp->fullBit (c+502,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->fullBus (c+503,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16); + vcdp->fullBit (c+504,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp183[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp183[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp183[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp183[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U]; + vcdp->fullArray(c+505,(__Vtemp183),128); + vcdp->fullBit (c+509,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))); + vcdp->fullBit (c+510,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))))); + vcdp->fullBus (c+511,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->fullBit (c+512,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp184[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp184[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp184[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp184[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U]; + vcdp->fullArray(c+513,(__Vtemp184),128); + vcdp->fullBit (c+517,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->fullBit (c+518,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))))); + __Vtemp185[0U] = 0U; + __Vtemp185[1U] = 0U; + __Vtemp185[2U] = 0U; + __Vtemp185[3U] = 0U; + vcdp->fullBus (c+519,(__Vtemp185[(3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))]),32); + vcdp->fullBus (c+520,(((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) + ? ((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U + == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? + (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)))) + : 0U)),32); + vcdp->fullBit (c+521,((((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access) + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use + == (0x1fffffU & + (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU)))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use)))); + vcdp->fullBus (c+522,((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use + << 0xbU)),32); + vcdp->fullArray(c+523,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vcellout__data_structures__data_use),128); + vcdp->fullBus (c+527,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use),21); + vcdp->fullBit (c+528,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use)); + vcdp->fullBit (c+529,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__access)); + vcdp->fullBit (c+530,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__write_from_mem)); + vcdp->fullBit (c+531,((((vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__tag_use + != (0x1fffffU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr + >> 0xbU))) + & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__valid_use)) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in)))); + vcdp->fullBit (c+532,((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)))); + vcdp->fullBit (c+533,((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)))); + vcdp->fullBit (c+534,((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)))); + vcdp->fullBit (c+535,((3U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)))); + vcdp->fullBus (c+536,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual),32); + vcdp->fullBus (c+537,(((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->fullBus (c+538,(((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))),32); + vcdp->fullBus (c+539,((0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32); + vcdp->fullBus (c+540,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)),32); + __Vtemp186[0U] = 0U; + __Vtemp186[1U] = 0U; + __Vtemp186[2U] = 0U; + __Vtemp186[3U] = 0U; + __Vtemp187[0U] = 0U; + __Vtemp187[1U] = 0U; + __Vtemp187[2U] = 0U; + __Vtemp187[3U] = 0U; + __Vtemp188[0U] = 0U; + __Vtemp188[1U] = 0U; + __Vtemp188[2U] = 0U; + __Vtemp188[3U] = 0U; + __Vtemp189[0U] = 0U; + __Vtemp189[1U] = 0U; + __Vtemp189[2U] = 0U; + __Vtemp189[3U] = 0U; + vcdp->fullBus (c+541,(((1U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff00U & (__Vtemp186[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 8U)) + : ((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff0000U & + (__Vtemp187[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x10U)) + : ((3U == (3U + & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xff000000U + & (__Vtemp188[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x18U)) + : __Vtemp189[ + (3U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))])))),32); + __Vtemp190[0U] = 0U; + __Vtemp190[1U] = 0U; + __Vtemp190[2U] = 0U; + __Vtemp190[3U] = 0U; + __Vtemp191[0U] = 0U; + __Vtemp191[1U] = 0U; + __Vtemp191[2U] = 0U; + __Vtemp191[3U] = 0U; + vcdp->fullBus (c+542,(((2U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? (0xffff0000U & ( + __Vtemp190[ + (3U + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))] + << 0x10U)) + : __Vtemp191[(3U & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank) + >> 6U))])),32); + vcdp->fullBus (c+543,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__use_write_data),32); + vcdp->fullBus (c+544,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x80U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffffff00U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? ((0x8000U & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + ? (0xffff0000U + | vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual)) + : ((5U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : ((4U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read)) + ? (0xffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual) + : vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_unQual))))),32); + vcdp->fullBus (c+545,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__sb_mask),4); + vcdp->fullBus (c+546,(((0U == (3U & vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr)) + ? 3U : 0xcU)),4); + vcdp->fullBus (c+547,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__we),16); + vcdp->fullArray(c+548,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_write),128); + vcdp->fullBit (c+552,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__genblk1__BRA__0__KET____DOT__normal_write)); + vcdp->fullBus (c+553,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__hit_per_way),2); + vcdp->fullBus (c+554,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way),32); + vcdp->fullArray(c+555,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way),256); + vcdp->fullBus (c+563,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way),2); + vcdp->fullBus (c+564,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_index),1); + vcdp->fullBus (c+565,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__way_use_Qual),1); + vcdp->fullBit (c+566,(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found)); + vcdp->fullBus (c+567,((0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)),16); + vcdp->fullBit (c+568,((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)))); + __Vtemp192[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[0U]; + __Vtemp192[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[1U]; + __Vtemp192[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[2U]; + __Vtemp192[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[3U]; + vcdp->fullArray(c+569,(__Vtemp192),128); + vcdp->fullBit (c+573,((0U != (0xffffU & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))); + vcdp->fullBit (c+574,((1U & ((1U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way)))))); + vcdp->fullBus (c+575,((0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))),16); + vcdp->fullBit (c+576,((1U & ((IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way) + >> 1U)))); + __Vtemp193[0U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[4U]; + __Vtemp193[1U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[5U]; + __Vtemp193[2U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[6U]; + __Vtemp193[3U] = vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__data_write_per_way[7U]; + vcdp->fullArray(c+577,(__Vtemp193),128); + vcdp->fullBit (c+581,((0U != (0xffffU & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))); + vcdp->fullBit (c+582,((1U & ((2U & (IData)(vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__write_from_mem_per_way)) + ? 0U : (0U != + (0xffffU + & (vlSymsp->TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__PVT__data_structures__DOT__we_per_way + >> 0x10U))))))); + vcdp->fullBit (c+583,(((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state))))); + vcdp->fullBus (c+584,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank) + ? vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read + : vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read)),32); + vcdp->fullBit (c+585,(((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state))))); + vcdp->fullBit (c+586,((1U & ((~ ((0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid)) + | (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)))) + & (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid))))); + vcdp->fullBus (c+587,(((0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests)) + ? ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))) + : ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests) + & (~ (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual))))),4); + __Vtemp196[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][0U]); + __Vtemp196[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][1U]); + __Vtemp196[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][2U]); + __Vtemp196[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr)][3U]); + vcdp->fullArray(c+588,(__Vtemp196),128); + __Vtemp199[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][0U]); + __Vtemp199[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][1U]); + __Vtemp199[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][2U]); + __Vtemp199[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 7U))][3U]); + vcdp->fullArray(c+592,(__Vtemp199),128); + __Vtemp202[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][0U]); + __Vtemp202[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][1U]); + __Vtemp202[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][2U]); + __Vtemp202[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0xeU))][3U]); + vcdp->fullArray(c+596,(__Vtemp202),128); + __Vtemp205[0U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][0U]); + __Vtemp205[1U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][1U]); + __Vtemp205[2U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][2U]); + __Vtemp205[3U] = ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write) + ? 0U : vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory + [(0x7fU & (vlTOPp->cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr + >> 0x15U))][3U]); + vcdp->fullArray(c+600,(__Vtemp205),128); + vcdp->fullBit (c+604,(((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (0U != (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb))))); + vcdp->fullBit (c+605,(((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state)) + & (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state))))); + __Vtemp206[0U] = (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U))] >> (0x1fU + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))); + __Vtemp206[1U] = (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(1U) + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))); + __Vtemp206[2U] = (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(2U) + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))); + __Vtemp206[3U] = (((0U == (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))) + ? 0U : (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(4U) + + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + << ((IData)(0x20U) + - (0x1fU & + ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U))))) + | (vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way[ + ((IData)(3U) + (4U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 2U)))] + >> (0x1fU & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual) + << 7U)))); + vcdp->fullArray(c+606,(__Vtemp206),128); + vcdp->fullBit (c+610,(((1U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual))))); + vcdp->fullBus (c+611,((1U & ((IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way) + >> (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual)))),1); + vcdp->fullBit (c+612,(((2U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__state)) + & (0U == (IData)(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state))))); 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+ vcdp->fullBit (c+3070,(vlTOPp->in_dcache_in_valid[0])); + vcdp->fullBit (c+3071,(vlTOPp->in_dcache_in_valid[1])); + vcdp->fullBit (c+3072,(vlTOPp->in_dcache_in_valid[2])); + vcdp->fullBit (c+3073,(vlTOPp->in_dcache_in_valid[3])); + vcdp->fullBus (c+3074,(vlTOPp->in_dcache_in_address[0]),32); + vcdp->fullBus (c+3075,(vlTOPp->in_dcache_in_address[1]),32); + vcdp->fullBus (c+3076,(vlTOPp->in_dcache_in_address[2]),32); + vcdp->fullBus (c+3077,(vlTOPp->in_dcache_in_address[3]),32); + vcdp->fullBit (c+3078,(vlTOPp->out_dcache_stall)); + vcdp->fullBus (c+3079,(((IData)(vlTOPp->in_icache_valid_pc_addr) + ? 2U : 7U)),3); + __Vtemp537[0U] = 0U; + __Vtemp537[1U] = 0U; + __Vtemp537[2U] = 0U; + __Vtemp537[3U] = 0U; + vcdp->fullArray(c+3080,(__Vtemp537),128); + vcdp->fullBus (c+3084,(7U),3); + vcdp->fullBus (c+3085,(0U),32); + vcdp->fullBit (c+3086,(0U)); + vcdp->fullBus (c+3087,(0x2000U),32); + vcdp->fullBus (c+3088,(4U),32); + vcdp->fullBus (c+3089,(0x10U),32); + vcdp->fullBus (c+3090,(2U),32); + vcdp->fullBus (c+3091,(0x80U),32); + vcdp->fullBus (c+3092,(3U),32); + vcdp->fullBus (c+3093,(5U),32); + vcdp->fullBus (c+3094,(6U),32); + vcdp->fullBus (c+3095,(0xcU),32); + vcdp->fullBus (c+3096,(4U),32); + vcdp->fullBus (c+3097,(0xffffffffU),32); + vcdp->fullBus (c+3098,(0x1000U),32); + vcdp->fullBus (c+3099,(0x40U),32); + vcdp->fullBus (c+3100,(0x20U),32); + vcdp->fullBus (c+3101,(1U),32); + vcdp->fullBus (c+3102,(0x14U),32); + vcdp->fullBus (c+3103,(0xbU),32); + vcdp->fullBus (c+3104,(0x1fU),32); + vcdp->fullBus (c+3105,(0xaU),32); + vcdp->fullBus (c+3106,(0xffffffc0U),32); + vcdp->fullArray(c+3107,(vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata),512); + vcdp->fullBus (c+3123,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb_old),4); + vcdp->fullBus (c+3124,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__dcache__DOT__init_b),32); + vcdp->fullBus (c+3125,(0U),2); + vcdp->fullBus (c+3126,(0U),5); + vcdp->fullBus (c+3127,(0x400U),32); + vcdp->fullBus (c+3128,(0x16U),32); + vcdp->fullBus (c+3129,(9U),32); + vcdp->fullBus (c+3130,(8U),32); + vcdp->fullBus (c+3131,(0xfffffff0U),32); + vcdp->fullArray(c+3132,(vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp_icache.i_m_readdata),128); + vcdp->fullBus (c+3136,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb_old),1); + vcdp->fullBus (c+3137,(1U),32); + vcdp->fullBus (c+3138,(vlTOPp->cache_simX__DOT__dmem_controller__DOT__icache__DOT__init_b),32); + __Vtemp538[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0U]; + __Vtemp538[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[1U]; + __Vtemp538[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[2U]; + __Vtemp538[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[3U]; + vcdp->fullArray(c+3139,(__Vtemp538),128); + __Vtemp539[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[4U]; + __Vtemp539[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[5U]; + __Vtemp539[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[6U]; + __Vtemp539[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[7U]; + vcdp->fullArray(c+3143,(__Vtemp539),128); + __Vtemp540[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[8U]; + __Vtemp540[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[9U]; + __Vtemp540[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xaU]; + __Vtemp540[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xbU]; + vcdp->fullArray(c+3147,(__Vtemp540),128); + __Vtemp541[0U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xcU]; + __Vtemp541[1U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xdU]; + __Vtemp541[2U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xeU]; + __Vtemp541[3U] = vlSymsp->TOP__cache_simX__DOT__VX_dram_req_rsp.i_m_readdata[0xfU]; + vcdp->fullArray(c+3151,(__Vtemp541),128); + } +} diff --git a/simX/obj_dir/Vcache_simX__ver.d b/simX/obj_dir/Vcache_simX__ver.d new file mode 100644 index 00000000..8c664704 --- /dev/null +++ b/simX/obj_dir/Vcache_simX__ver.d @@ -0,0 +1 @@ +obj_dir/Vcache_simX.cpp obj_dir/Vcache_simX.h obj_dir/Vcache_simX.mk obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h obj_dir/Vcache_simX_VX_dcache_request_inter.cpp obj_dir/Vcache_simX_VX_dcache_request_inter.h obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h obj_dir/Vcache_simX__Syms.cpp obj_dir/Vcache_simX__Syms.h obj_dir/Vcache_simX__Trace.cpp obj_dir/Vcache_simX__Trace__Slow.cpp obj_dir/Vcache_simX__ver.d obj_dir/Vcache_simX_classes.mk : /usr/bin/verilator_bin ../rtl/./VX_define_synth.v ../rtl/VX_countones.v ../rtl/VX_define.v ../rtl/VX_dmem_controller.v ../rtl/VX_generic_priority_encoder.v ../rtl/VX_priority_encoder_w_mask.v ../rtl/cache/VX_Cache_Bank.v ../rtl/cache/VX_cache_bank_valid.v ../rtl/cache/VX_cache_data.v ../rtl/cache/VX_cache_data_per_index.v ../rtl/cache/VX_d_cache.v ../rtl/interfaces/VX_dcache_request_inter.v ../rtl/interfaces/VX_dcache_response_inter.v ../rtl/interfaces/VX_dram_req_rsp_inter.v ../rtl/interfaces/VX_icache_request_inter.v ../rtl/interfaces/VX_icache_response_inter.v ../rtl/shared_memory/../VX_define.v ../rtl/shared_memory/VX_bank_valids.v ../rtl/shared_memory/VX_priority_encoder_sm.v ../rtl/shared_memory/VX_shared_memory.v ../rtl/shared_memory/VX_shared_memory_block.v /usr/bin/verilator_bin cache_simX.v diff --git a/simX/obj_dir/Vcache_simX__verFiles.dat b/simX/obj_dir/Vcache_simX__verFiles.dat new file mode 100644 index 00000000..97154400 --- /dev/null +++ b/simX/obj_dir/Vcache_simX__verFiles.dat @@ -0,0 +1,43 @@ +# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. +C "--compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -CFLAGS -std=c++11 -fPIC -O3 -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1" +S 26 4200738 1579395713 628434579 1579395713 628434579 "../rtl/./VX_define_synth.v" +S 283 4200733 1579395713 624434332 1579395713 624434332 "../rtl/VX_countones.v" +S 7240 4200737 1579395713 628434579 1579395713 628434579 "../rtl/VX_define.v" +S 8325 4200739 1579395713 628434579 1579395713 628434579 "../rtl/VX_dmem_controller.v" +S 517 4200743 1579395713 628434579 1579395713 628434579 "../rtl/VX_generic_priority_encoder.v" +S 683 4200754 1579395713 628434579 1579395713 628434579 "../rtl/VX_priority_encoder_w_mask.v" +S 8590 4200764 1579395713 628434579 1579395713 628434579 "../rtl/cache/VX_Cache_Bank.v" +S 748 4200765 1579395713 628434579 1579395713 628434579 "../rtl/cache/VX_cache_bank_valid.v" +S 7349 4200766 1579395713 628434579 1579395713 628434579 "../rtl/cache/VX_cache_data.v" +S 6476 4200767 1579395713 628434579 1579395713 628434579 "../rtl/cache/VX_cache_data_per_index.v" +S 14645 4200768 1579395713 628434579 1579395713 628434579 "../rtl/cache/VX_d_cache.v" +S 393 4200780 1579395713 628434579 1579395713 628434579 "../rtl/interfaces/VX_dcache_request_inter.v" +S 215 4200781 1579395713 628434579 1579395713 628434579 "../rtl/interfaces/VX_dcache_response_inter.v" +S 870 4200782 1579395713 628434579 1579395713 628434579 "../rtl/interfaces/VX_dram_req_rsp_inter.v" +S 354 4200791 1579395713 628434579 1579395713 628434579 "../rtl/interfaces/VX_icache_request_inter.v" +S 212 4200792 1579395713 628434579 1579395713 628434579 "../rtl/interfaces/VX_icache_response_inter.v" +S 7240 4200737 1579395713 628434579 1579395713 628434579 "../rtl/shared_memory/../VX_define.v" +S 676 4200836 1579395713 632434826 1579395713 632434826 "../rtl/shared_memory/VX_bank_valids.v" +S 3038 4200837 1579395713 632434826 1579395713 632434826 "../rtl/shared_memory/VX_priority_encoder_sm.v" +S 4962 4200838 1579395713 632434826 1579395713 632434826 "../rtl/shared_memory/VX_shared_memory.v" +S 3207 4200839 1579395713 632434826 1579395713 632434826 "../rtl/shared_memory/VX_shared_memory_block.v" +S 5279832 2492902 1578745602 593855204 1519110675 0 "/usr/bin/verilator_bin" +S 3144 4201058 1579395714 588493892 1579395714 588493892 "cache_simX.v" +T 606556 4194579 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX.cpp" +T 31121 4194577 1579629057 321619018 1579629057 321619018 "obj_dir/Vcache_simX.h" +T 2305 4196430 1579629057 341619018 1579629057 341619018 "obj_dir/Vcache_simX.mk" +T 539818 4194597 1579629057 341619018 1579629057 341619018 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp" +T 19062 4194595 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h" +T 1024 4194591 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_dcache_request_inter.cpp" +T 1561 4194589 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_dcache_request_inter.h" +T 999 4194587 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp" +T 1556 4194585 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h" +T 999 4194583 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp" +T 1557 4194581 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h" +T 3807 4194517 1579629057 293619017 1579629057 293619017 "obj_dir/Vcache_simX__Syms.cpp" +T 1918 4194514 1579629057 293619017 1579629057 293619017 "obj_dir/Vcache_simX__Syms.h" +T 704422 4194575 1579629057 317619018 1579629057 317619018 "obj_dir/Vcache_simX__Trace.cpp" +T 921157 4194573 1579629057 309619018 1579629057 309619018 "obj_dir/Vcache_simX__Trace__Slow.cpp" +T 1461 4196431 1579629057 341619018 1579629057 341619018 "obj_dir/Vcache_simX__ver.d" +T 0 0 1579629057 341619018 1579629057 341619018 "obj_dir/Vcache_simX__verFiles.dat" +T 1403 4196429 1579629057 341619018 1579629057 341619018 "obj_dir/Vcache_simX_classes.mk" diff --git a/simX/obj_dir/Vcache_simX_classes.mk b/simX/obj_dir/Vcache_simX_classes.mk new file mode 100644 index 00000000..61f3273c --- /dev/null +++ b/simX/obj_dir/Vcache_simX_classes.mk @@ -0,0 +1,45 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Make include file with class lists +# +# This file lists generated Verilated files, for including in higher level makefiles. +# See Vcache_simX.mk for the caller. + +### Switches... +# Coverage output mode? 0/1 (from --coverage) +VM_COVERAGE = 0 +# Threaded output mode? 0/1/N threads (from --threads) +VM_THREADS = 0 +# Tracing output mode? 0/1 (from --trace) +VM_TRACE = 1 + +### Object file lists... +# Generated module classes, fast-path, compile with highest optimization +VM_CLASSES_FAST += \ + Vcache_simX \ + Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 \ + Vcache_simX_VX_dram_req_rsp_inter__N1_NB4 \ + Vcache_simX_VX_dcache_request_inter \ + Vcache_simX_VX_Cache_Bank__pi8 \ + +# Generated module classes, non-fast-path, compile with low/medium optimization +VM_CLASSES_SLOW += \ + +# Generated support classes, fast-path, compile with highest optimization +VM_SUPPORT_FAST += \ + Vcache_simX__Trace \ + +# Generated support classes, non-fast-path, compile with low/medium optimization +VM_SUPPORT_SLOW += \ + Vcache_simX__Syms \ + Vcache_simX__Trace__Slow \ + +# Global classes, need linked once per executable, fast-path, compile with highest optimization +VM_GLOBAL_FAST += \ + verilated \ + verilated_vcd_c \ + +# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization +VM_GLOBAL_SLOW += \ + + +# Verilated -*- Makefile -*- diff --git a/simX/obj_dir/args.d b/simX/obj_dir/args.d new file mode 100644 index 00000000..bef545e5 --- /dev/null +++ b/simX/obj_dir/args.d @@ -0,0 +1 @@ +args.o: ../args.cpp ../include/args.h diff --git a/simX/obj_dir/args.o b/simX/obj_dir/args.o new file mode 100644 index 00000000..31f08d3d Binary files /dev/null and b/simX/obj_dir/args.o differ diff --git a/simX/obj_dir/core.d b/simX/obj_dir/core.d new file mode 100644 index 00000000..a9e0c102 --- /dev/null +++ b/simX/obj_dir/core.d @@ -0,0 +1,11 @@ +core.o: ../core.cpp ../include/types.h ../include/util.h \ + ../include/types.h ../include/archdef.h ../include/mem.h \ + ../include/enc.h ../include/instruction.h ../include/trace.h \ + ../include/obj.h ../include/archdef.h ../include/enc.h \ + ../include/asm-tokens.h ../include/core.h ../include/mem.h \ + ../include/debug.h Vcache_simX.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilatedos.h \ + /usr/share/verilator/include/verilated_vcd_c.h \ + /usr/share/verilator/include/verilated.h ../include/debug.h diff --git a/simX/obj_dir/core.o b/simX/obj_dir/core.o new file mode 100644 index 00000000..e17e2431 Binary files /dev/null and b/simX/obj_dir/core.o differ diff --git a/simX/obj_dir/emulator.debug b/simX/obj_dir/emulator.debug new file mode 100644 index 00000000..48bafd32 --- /dev/null +++ b/simX/obj_dir/emulator.debug @@ -0,0 +1 @@ +../rvvector/basic/vx_vector_main.hex not found diff --git a/simX/obj_dir/enc.d b/simX/obj_dir/enc.d new file mode 100644 index 00000000..c9cdd837 --- /dev/null +++ b/simX/obj_dir/enc.d @@ -0,0 +1,5 @@ +enc.o: ../enc.cpp ../include/debug.h ../include/types.h ../include/util.h \ + ../include/types.h ../include/enc.h ../include/instruction.h \ + ../include/trace.h ../include/obj.h ../include/archdef.h \ + ../include/enc.h ../include/asm-tokens.h ../include/archdef.h \ + ../include/instruction.h diff --git a/simX/obj_dir/enc.o b/simX/obj_dir/enc.o new file mode 100644 index 00000000..b35d5861 Binary files /dev/null and b/simX/obj_dir/enc.o differ diff --git a/simX/obj_dir/instruction.d b/simX/obj_dir/instruction.d new file mode 100644 index 00000000..bdb032a2 --- /dev/null +++ b/simX/obj_dir/instruction.d @@ -0,0 +1,11 @@ +instruction.o: ../instruction.cpp ../include/instruction.h \ + ../include/types.h ../include/trace.h ../include/obj.h \ + ../include/archdef.h ../include/instruction.h ../include/enc.h \ + ../include/obj.h ../include/asm-tokens.h ../include/core.h \ + ../include/mem.h ../include/debug.h Vcache_simX.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilatedos.h \ + /usr/share/verilator/include/verilated_vcd_c.h \ + /usr/share/verilator/include/verilated.h ../include/harpfloat.h \ + ../include/debug.h diff --git a/simX/obj_dir/instruction.o b/simX/obj_dir/instruction.o new file mode 100644 index 00000000..2ce51278 Binary files /dev/null and b/simX/obj_dir/instruction.o differ diff --git a/simX/obj_dir/mem.d b/simX/obj_dir/mem.d new file mode 100644 index 00000000..9ce03ac1 --- /dev/null +++ b/simX/obj_dir/mem.d @@ -0,0 +1,10 @@ +mem.o: ../mem.cpp ../include/debug.h ../include/types.h ../include/util.h \ + ../include/types.h ../include/mem.h ../include/core.h \ + ../include/archdef.h ../include/enc.h ../include/instruction.h \ + ../include/trace.h ../include/obj.h ../include/asm-tokens.h \ + ../include/mem.h ../include/debug.h Vcache_simX.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilatedos.h \ + /usr/share/verilator/include/verilated_vcd_c.h \ + /usr/share/verilator/include/verilated.h diff --git a/simX/obj_dir/mem.o b/simX/obj_dir/mem.o new file mode 100644 index 00000000..4e52e766 Binary files /dev/null and b/simX/obj_dir/mem.o differ diff --git a/simX/obj_dir/simX.d b/simX/obj_dir/simX.d new file mode 100644 index 00000000..be88d414 --- /dev/null +++ b/simX/obj_dir/simX.d @@ -0,0 +1,12 @@ +simX.o: ../simX.cpp ../include/debug.h ../include/types.h \ + ../include/core.h ../include/types.h ../include/archdef.h \ + ../include/enc.h ../include/instruction.h ../include/trace.h \ + ../include/obj.h ../include/asm-tokens.h ../include/mem.h \ + ../include/debug.h Vcache_simX.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilatedos.h \ + /usr/share/verilator/include/verilated_vcd_c.h \ + /usr/share/verilator/include/verilated.h ../include/enc.h \ + ../include/instruction.h ../include/mem.h ../include/obj.h \ + ../include/archdef.h ../include/args.h ../include/help.h diff --git a/simX/obj_dir/simX.o b/simX/obj_dir/simX.o new file mode 100644 index 00000000..b7d7869f Binary files /dev/null and b/simX/obj_dir/simX.o differ diff --git a/simX/obj_dir/util.d b/simX/obj_dir/util.d new file mode 100644 index 00000000..d7d5aee0 --- /dev/null +++ b/simX/obj_dir/util.d @@ -0,0 +1,2 @@ +util.o: ../util.cpp ../include/types.h ../include/util.h \ + ../include/types.h diff --git a/simX/obj_dir/util.o b/simX/obj_dir/util.o new file mode 100644 index 00000000..e9cb97ef Binary files /dev/null and b/simX/obj_dir/util.o differ diff --git a/simX/obj_dir/verilated.d b/simX/obj_dir/verilated.d new file mode 100644 index 00000000..378ca2d9 --- /dev/null +++ b/simX/obj_dir/verilated.d @@ -0,0 +1,7 @@ +verilated.o: /usr/share/verilator/include/verilated.cpp \ + /usr/share/verilator/include/verilated_imp.h \ + /usr/share/verilator/include/verilatedos.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilated_heavy.h \ + /usr/share/verilator/include/verilated_syms.h diff --git a/simX/obj_dir/verilated.o b/simX/obj_dir/verilated.o new file mode 100644 index 00000000..39b118dc Binary files /dev/null and b/simX/obj_dir/verilated.o differ diff --git a/simX/obj_dir/verilated_vcd_c.d b/simX/obj_dir/verilated_vcd_c.d new file mode 100644 index 00000000..d96f0805 --- /dev/null +++ b/simX/obj_dir/verilated_vcd_c.d @@ -0,0 +1,5 @@ +verilated_vcd_c.o: /usr/share/verilator/include/verilated_vcd_c.cpp \ + /usr/share/verilator/include/verilatedos.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilated_vcd_c.h diff --git a/simX/obj_dir/verilated_vcd_c.o b/simX/obj_dir/verilated_vcd_c.o new file mode 100644 index 00000000..b3766fb9 Binary files /dev/null and b/simX/obj_dir/verilated_vcd_c.o differ diff --git a/simX/test_vec.sh b/simX/test_vec.sh index db6a9cf4..e37f2ed5 100755 --- a/simX/test_vec.sh +++ b/simX/test_vec.sh @@ -3,4 +3,4 @@ echo start > results.txt # echo ../kernel/vortex_test.hex make printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n" -cd obj_dir && ./Vcache_simX -E -a rv32i --core ../../rvvector/basic/vx_vector_main.hex -s -b 1> emulator.debug +cd obj_dir && ./Vcache_simX -E -a rv32i --core ../rvvector/basic/vx_vector_main.hex -s -b 1> emulator.debug