diff --git a/doc/cache_subsystem.md b/doc/cache_subsystem.md
index 9de9aef7..41d2fad6 100644
--- a/doc/cache_subsystem.md
+++ b/doc/cache_subsystem.md
@@ -8,7 +8,7 @@ The Vortex Cache Sub-system has the following main properties:
 
 ### Cache Hierarchy 
 
-![Image of Cache Hierarchy](./Images/cache_hierarchy.png)
+![Image of Cache Hierarchy](./images/cache_hierarchy.png)
 
 - Cache can be configured to be any level in the hierarchy
 - Caches communicate via snooping
@@ -18,7 +18,7 @@ The Vortex Cache Sub-system has the following main properties:
 
 VX.cache.v is the top module of the cache verilog code located in the `/hw/rtl/cache` directory.
 
-![Image of Vortex Cache](./Images/vortex_cache_top_module.png)
+![Image of Vortex Cache](./images/vortex_cache_top_module.png)
 
 - Configurable (Cache size, number of banks, bank line size, etc.)
 - I/O signals
@@ -44,7 +44,7 @@ VX.cache.v is the top module of the cache verilog code located in the `/hw/rtl/c
 
 VX_bank.v is the verilog code that handles cache bank functionality and is located in the `/hw/rtl/cache` directory.
 
-![Image of Vortex Cache Bank](./Images/vortex_bank.png)
+![Image of Vortex Cache Bank](./images/vortex_bank.png)
 
 - Allows for high throughput​
 - Each bank contains queues to hold requests to the cache​
diff --git a/doc/codebase.md b/doc/codebase.md
index ae1f3d02..4f4db1fc 100644
--- a/doc/codebase.md
+++ b/doc/codebase.md
@@ -2,33 +2,34 @@
 
 The directory/file layout of the Vortex codebase is as followed:
 
-- `hw`: 
-  - `unit_tests`: contains unit test for RTL of cache and queue
-  - `syn`: contains all synthesis scripts (quartus and yosys)
-    - `quartus`: contains synthesis scripts for Intel Quartus toolchain
-    - `opae`: contains synthesis scripts for Intel OPAE FPGA
-  - `simulate`: contains RTL simulator (verilator)  
-  - `rtl`: contains rtl source code
-    - `cache`: contains cache subsystem code
-    - `fp_cores`: contains floating point unit code
-    - `interfaces`: contains code that handles communication for each of the units of the microarchitecture
-    - `libs`: contains general-purpose modules (i.e., buffers, encoders, arbiters, pipe registers)
-- `driver`: contains driver software implementation (software that is run on the host to communicate with the vortex processor)
-  - `include`: contains vortex.h which has the vortex API that is used by the drivers
-  - `opae`: contains code for driver that runs on FPGA
-  - `rtlsim`: contains code for driver that runs on local machine (driver built using verilator which converts rtl to c++ binary)
-  - `simx`: contains code for driver that runs on local machine (vortex)  
-- `runtime`: contains software used inside kernel programs to expose GPGPU capabilities
-  - `include`: contains vortex API needed for runtime
-  - `linker`: contains linker file for compiling kernels
-  - `src`: contains implementation of vortex API (from include folder)
-- `simX`: contains simX, the cycle approximate simulator for vortex
-  - `tests`: contains tests suite
-    - `runtime`: contains vortex runtime tests
-    - `driver`: contains vortex driver tests
-    - `opencl`: contains opencl tests and benchmarks
-    - `riscv`: contains official riscv tests
-    - `regression`: contains regression tests
-    - `vector`: tests for vector instructions (not yet implemented)
-  - `ci`: contain tests to be run during continuous integration (Travis CI)
-  - `miscs`: contains miscellaneous stuffs
\ No newline at end of file
+- `hw`:     
+  - `rtl`: hardware rtl sources
+    - `cache`: cache subsystem code
+    - `fp_cores`: floating point unit code
+    - `interfaces`: interfaces for inter-module communication
+    - `libs`: general-purpose modules (i.e., encoder, arbiter, ...)
+  - `syn`: synthesis directory
+    - `opae`: OPAE synthesis scripts
+    - `quartus`: Quartus synthesis scripts    
+    - `synopsys`: Synopsys synthesis scripts
+    - `yosys`: Yosys synthesis scripts
+  - `simulate`: baseline RTL simulator (used by RTLSIM)
+  - `unit_tests`: unit tests for some hardware components
+- `driver`: Host driver software
+  - `include`: Vortex driver public headers
+  - `opae`: software driver that uses Intel OPAE
+  - `vlsim`: software driver that simulates Full RTL (include AFU)
+  - `rtlsim`: software driver that simulates processor RTL
+  - `simx`: software driver that uses simX simulator
+- `runtime`: Kernel runtime software
+  - `include`: Vortex runtime public headers
+  - `linker`: linker file for compiling kernels
+  - `src`: runtime implementation
+- `simX`: cycle approximate simulator for vortex
+- `tests`: tests repository.
+  - `runtime`: runtime tests
+  - `regression`: regression tests
+  - `riscv`: RISC-V standard tests
+  - `opencl`: opencl benchmarks and tests
+- `ci`: continuous integration scripts
+- `miscs`: miscellaneous resources.
diff --git a/doc/microarchitecture.md b/doc/microarchitecture.md
index 1b410066..7e7a6a59 100644
--- a/doc/microarchitecture.md
+++ b/doc/microarchitecture.md
@@ -32,7 +32,7 @@ Vortex uses the SIMT (Single Instruction, Multiple Threads) execution model with
 
 ### Vortex Pipeline/Datapath
 
-![Image of Vortex Microarchitecture](./Images/vortex_microarchitecture_v2.png)
+![Image of Vortex Microarchitecture](./images/vortex_microarchitecture_v2.png)
 
 Vortex has a 5-stage pipeline: FI | ID | Issue | EX | WB.