From 79cbea0a13de748f6697206a495841789cb0d648 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 22 Mar 2021 12:20:01 -0400 Subject: [PATCH] tex_unit compiler fixes --- hw/rtl/VX_define.vh | 3 ++- hw/rtl/VX_execute.v | 33 ++++++++++++++--------- hw/rtl/interfaces/VX_dcache_core_rsp_if.v | 8 +++--- hw/rtl/tex_unit/VX_tex_sampler.v | 4 +-- hw/rtl/tex_unit/VX_tex_unit.v | 6 ++--- 5 files changed, 32 insertions(+), 22 deletions(-) diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 6a2a8125..e0443a55 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -293,7 +293,8 @@ `ifdef EXT_TEX_ENABLE `define LSU_DACHE_TAG_BITS (`DBG_CACHE_REQ_MDATAW + `LSUQ_ADDR_BITS) `define TEX_DACHE_TAG_BITS (`DBG_CACHE_REQ_MDATAW + 2 + `LSUQ_ADDR_BITS) -`define DCORE_TAG_WIDTH (`MAX(`LSU_DACHE_TAG_BITS, `TEX_DACHE_TAG_BITS) + 1) +`define LSU_TEX_DACHE_TAG_BITS `MAX(`LSU_DACHE_TAG_BITS, `TEX_DACHE_TAG_BITS) +`define DCORE_TAG_WIDTH (`LSU_TEX_DACHE_TAG_BITS + 1) `else `define DCORE_TAG_WIDTH (`DBG_CACHE_REQ_MDATAW + `DCORE_TAG_ID_BITS) `endif diff --git a/hw/rtl/VX_execute.v b/hw/rtl/VX_execute.v index c690ae75..59786851 100644 --- a/hw/rtl/VX_execute.v +++ b/hw/rtl/VX_execute.v @@ -72,29 +72,38 @@ module VX_execute #( .CORE_TAG_WIDTH(`TEX_DACHE_TAG_BITS) ) tex_dcache_rsp_if(); - VX_tex_csr_if tex_csr_if(); + VX_tex_csr_if tex_csr_if(); - wire [1:0] tmp; - `UNUSED_VAR (tmp) + wire [`NUM_THREADS-1:0][`LSU_TEX_DACHE_TAG_BITS-1:0] lsu_tag_in; + wire [`LSU_TEX_DACHE_TAG_BITS-1:0] lsu_tag_out; + + for (genvar i = 0; i < `NUM_THREADS; ++i) begin + assign lsu_tag_in[i][`LSUQ_ADDR_BITS-1:0] = lsu_dcache_req_if.tag[i][`LSUQ_ADDR_BITS-1:0]; + assign lsu_tag_in[i][`LSUQ_ADDR_BITS+:2] = '0; + assign lsu_tag_in[i][(`LSUQ_ADDR_BITS+2)+:`DBG_CACHE_REQ_MDATAW] = lsu_dcache_req_if.tag[i][`LSUQ_ADDR_BITS+:`DBG_CACHE_REQ_MDATAW]; + end + assign lsu_dcache_rsp_if.tag[`LSUQ_ADDR_BITS-1:0] = lsu_tag_out[`LSUQ_ADDR_BITS-1:0]; + assign lsu_dcache_rsp_if.tag[`LSUQ_ADDR_BITS+:`DBG_CACHE_REQ_MDATAW] = lsu_tag_out[(`LSUQ_ADDR_BITS+2)+:`DBG_CACHE_REQ_MDATAW]; + `UNUSED_VAR (lsu_tag_out) VX_tex_lsu_arb #( .NUM_REQS (2), .LANES (`NUM_THREADS), .WORD_SIZE (4), - .TAG_IN_WIDTH (`MAX(`LSU_DACHE_TAG_BITS, `TEX_DACHE_TAG_BITS)), + .TAG_IN_WIDTH (`LSU_TEX_DACHE_TAG_BITS), .TAG_OUT_WIDTH (`DCORE_TAG_WIDTH) ) tex_lsu_arb ( .clk (clk), .reset (reset), // Tex/LSU request - .req_valid_in ({tex_dcache_req_if.valid, lsu_dcache_req_if.valid}), - .req_rw_in ({tex_dcache_req_if.rw, lsu_dcache_req_if.rw}), + .req_valid_in ({tex_dcache_req_if.valid, lsu_dcache_req_if.valid}), + .req_rw_in ({tex_dcache_req_if.rw, lsu_dcache_req_if.rw}), .req_byteen_in ({tex_dcache_req_if.byteen, lsu_dcache_req_if.byteen}), - .req_addr_in ({tex_dcache_req_if.addr, lsu_dcache_req_if.addr}), - .req_data_in ({tex_dcache_req_if.data, lsu_dcache_req_if.data}), - .req_tag_in ({tex_dcache_req_if.tag, {2'b0, lsu_dcache_req_if.tag}}), - .req_ready_in ({tex_dcache_req_if.ready, lsu_dcache_req_if.ready}), + .req_addr_in ({tex_dcache_req_if.addr, lsu_dcache_req_if.addr}), + .req_data_in ({tex_dcache_req_if.data, lsu_dcache_req_if.data}), + .req_tag_in ({tex_dcache_req_if.tag, lsu_tag_in}), + .req_ready_in ({tex_dcache_req_if.ready, lsu_dcache_req_if.ready}), // Dcache request .req_valid_out (dcache_req_if.valid), @@ -107,8 +116,8 @@ module VX_execute #( // Tex/LSU response .rsp_valid_out ({tex_dcache_rsp_if.valid, lsu_dcache_rsp_if.valid}), - .rsp_data_out ({tex_dcache_rsp_if.data, lsu_dcache_rsp_if.data}), - .rsp_tag_out ({tex_dcache_rsp_if.tag, {tmp, lsu_dcache_rsp_if.tag}}), + .rsp_data_out ({tex_dcache_rsp_if.data, lsu_dcache_rsp_if.data}), + .rsp_tag_out ({tex_dcache_rsp_if.tag, lsu_tag_out}), .rsp_ready_out ({tex_dcache_rsp_if.ready, lsu_dcache_rsp_if.ready}), // Dcache response diff --git a/hw/rtl/interfaces/VX_dcache_core_rsp_if.v b/hw/rtl/interfaces/VX_dcache_core_rsp_if.v index 4d17d24a..64dcc0da 100644 --- a/hw/rtl/interfaces/VX_dcache_core_rsp_if.v +++ b/hw/rtl/interfaces/VX_dcache_core_rsp_if.v @@ -9,10 +9,10 @@ interface VX_dcache_core_rsp_if #( parameter CORE_TAG_WIDTH = 1 ) (); - wire [LANES-1:0] valid; - wire [LANES-1:0][`WORD_WIDTH-1:0]data; - wire [CORE_TAG_WIDTH-1:0] tag; - wire ready; + wire [LANES-1:0] valid; + wire [LANES-1:0][`WORD_WIDTH-1:0] data; + wire [CORE_TAG_WIDTH-1:0] tag; + wire ready; endinterface diff --git a/hw/rtl/tex_unit/VX_tex_sampler.v b/hw/rtl/tex_unit/VX_tex_sampler.v index 43cd4f5f..742472f3 100644 --- a/hw/rtl/tex_unit/VX_tex_sampler.v +++ b/hw/rtl/tex_unit/VX_tex_sampler.v @@ -33,7 +33,7 @@ module VX_tex_sampler #( `UNUSED_PARAM (CORE_ID) - wire [31:0] req_data [`NUM_THREADS-1:0]; + /*wire [31:0] req_data [`NUM_THREADS-1:0]; if (req_filter == 0) begin // point sampling @@ -93,6 +93,6 @@ module VX_tex_sampler #( .enable (~stall_out), .data_in ({req_valid, req_wid, req_tmask, req_PC, req_rd, req_wb, req_data}), .data_out ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data}) - ); + );*/ endmodule \ No newline at end of file diff --git a/hw/rtl/tex_unit/VX_tex_unit.v b/hw/rtl/tex_unit/VX_tex_unit.v index eb3609f8..9694f987 100644 --- a/hw/rtl/tex_unit/VX_tex_unit.v +++ b/hw/rtl/tex_unit/VX_tex_unit.v @@ -91,7 +91,7 @@ module VX_tex_unit #( VX_tex_addr #( .REQ_INFO_WIDTH (REQ_INFO_WIDTH_A) - ) tex_addr ( + ) _tex_addr ( .clk (clk), .reset (reset), @@ -174,9 +174,9 @@ module VX_tex_unit #( assign {rsp_format, rsp_u, rsp_v, rsp_rd, rsp_wb} = mem_rsp_info; - VX_tex_sampler #( + VX_tex_sampler #( .CORE_ID (CORE_ID) - ) tex_sampler ( + ) tex_sampler ( .clk (clk), .reset (reset),