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cache bank refactoring - removing unecessary core response fifo & restoring single port data access

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This commit is contained in:
Blaise Tine
2021-02-21 21:47:46 -08:00
parent ccb74ef286
commit 7560202f8b
12 changed files with 129 additions and 294 deletions
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25
hw/rtl/VX_config.vh
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@@ -264,11 +264,6 @@
`define ICREQ_SIZE 4
`endif
// Core Response Queue Size
`ifndef ICRSQ_SIZE
`define ICRSQ_SIZE 4
`endif
// Miss Handling Register Size
`ifndef IMSHR_SIZE
`define IMSHR_SIZE `NUM_WARPS
@@ -306,11 +301,6 @@
`define DCREQ_SIZE 4
`endif
// Core Response Queue Size
`ifndef DCRSQ_SIZE
`define DCRSQ_SIZE 4
`endif
// Miss Handling Register Size
`ifndef DMSHR_SIZE
`define DMSHR_SIZE `LSUQ_SIZE
@@ -348,11 +338,6 @@
`define SCREQ_SIZE 4
`endif
// Core Response Queue Size
`ifndef SCRSQ_SIZE
`define SCRSQ_SIZE 4
`endif
// L2cache Configurable Knobs /////////////////////////////////////////////////
// Size of cache in bytes
@@ -370,11 +355,6 @@
`define L2CREQ_SIZE 4
`endif
// Core Response Queue Size
`ifndef L2CRSQ_SIZE
`define L2CRSQ_SIZE 4
`endif
// Miss Handling Register Size
`ifndef L2MSHR_SIZE
`define L2MSHR_SIZE 16
@@ -407,11 +387,6 @@
`define L3CREQ_SIZE 4
`endif
// Core Response Queue Size
`ifndef L3CRSQ_SIZE
`define L3CRSQ_SIZE 4
`endif
// Miss Handling Register Size
`ifndef L3MSHR_SIZE
`define L3MSHR_SIZE 16