fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags

hw/rtl/cache/VX_bank.v

@@ -447,6 +447,8 @@ module VX_bank #(
 `ifdef DBG_CORE_REQ_INFO
     if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
         assign {debug_pc_st1, debug_rd_st1, debug_wid_st1, debug_tagid_st1, debug_rw_st1, debug_byteen_st1, debug_tid_st1} = inst_meta_st1;
+    end else begin
+        assign {debug_pc_st1, debug_rd_st1, debug_wid_st1, debug_tagid_st1, debug_rw_st1, debug_byteen_st1, debug_tid_st1} = 0;
     end
 `endif
     

hw/rtl/cache/VX_cache_miss_resrv.v

@@ -58,6 +58,7 @@ module VX_cache_miss_resrv #(
 );
     reg [`MRVQ_METADATA_WIDTH-1:0] metadata_table[MRVQ_SIZE-1:0];
     reg [MRVQ_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table;
+    
     reg [MRVQ_SIZE-1:0]            valid_table;
     reg [MRVQ_SIZE-1:0]            ready_table;
     reg [`LOG2UP(MRVQ_SIZE)-1:0]   schedule_ptr;

hw/rtl/cache/VX_tag_data_store.v

@@ -30,7 +30,6 @@ module VX_tag_data_store #(
     input  wire                             fill_sent    
 );
 
-    reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0][7:0] data [`BANK_LINE_COUNT-1:0];    
     reg [`TAG_SELECT_BITS-1:0]                      tag [`BANK_LINE_COUNT-1:0];
     reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0]     dirtyb[`BANK_LINE_COUNT-1:0];
     reg [`BANK_LINE_COUNT-1:0]                     dirty;   
@@ -40,8 +39,7 @@ module VX_tag_data_store #(
     assign read_dirty  = dirty  [read_addr];
     assign read_dirtyb = dirtyb [read_addr];
     assign read_tag    = tag    [read_addr];
-    assign read_data   = data   [read_addr];
-
+    
     wire do_write = (| write_enable);
 
     always @(posedge clk) begin
@@ -69,15 +67,26 @@ module VX_tag_data_store #(
             if (invalidate) begin
                 valid[write_addr] <= 0;
             end
-
-            for (integer j = 0; j < `BANK_LINE_WORDS; j++) begin
-                for (integer i = 0; i < WORD_SIZE; i++) begin
-                    if (write_enable[j][i]) begin
-                        data[write_addr][j][i] <= write_data[j * `WORD_WIDTH + i * 8 +: 8];
-                    end
-                end
-            end
         end
     end
 
+    wire [(`BANK_LINE_WORDS * WORD_SIZE)-1:0] ram_wren;
+    assign ram_wren = write_enable & {(`BANK_LINE_WORDS * WORD_SIZE){!stall_bank_pipe}};
+
+    VX_dp_ram #(
+        .DATAW(`BANK_LINE_WORDS * WORD_SIZE * 8),
+        .SIZE(`BANK_LINE_COUNT),
+        .BYTEENW(`BANK_LINE_WORDS * WORD_SIZE),
+        .BUFFERED(0),
+        .RWCHECK(1)
+    ) dp_ram (
+        .clk(clk),	                
+        .waddr(write_addr),                                
+        .raddr(read_addr),                
+        .wren(ram_wren),
+        .rden(1'b1),
+        .din(write_data),
+        .dout(read_data)
+    );
+
 endmodule