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fixed DRAM response backpressure inside Cache

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This commit is contained in:
Blaise Tine
2020-11-10 05:24:57 -08:00
parent ed69be4027
commit 725322807e
19 changed files with 69 additions and 36 deletions
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6
driver/opae/vlsim/Makefile
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@@ -20,11 +20,11 @@ DBG_FLAGS += $(DBG_PRINT_FLAGS)
DBG_FLAGS += -DDBG_CORE_REQ_INFO
#CONFIGS += -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1 -DL3_ENABLE=1
CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1
#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1
CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=1
DEBUG=1
#DEBUG=1
#SCOPE=1
CFLAGS += -fPIC

20
driver/opae/vlsim/opae_sim.cpp
View File

@@ -263,7 +263,16 @@ void opae_sim::avs_bus() {
if (dram_rd_it != dram_reads_.end()) {
vortex_afu_->avs_readdatavalid = 1;
memcpy(vortex_afu_->avs_readdata, dram_rd_it->block.data(), CACHE_BLOCK_SIZE);
uint32_t tag = dram_rd_it->tag;
dram_reads_.erase(dram_rd_it);
/*printf("%0ld: VLSIM: DRAM rsp: addr=%x, pending={", timestamp, tag);
for (auto& req : dram_reads_) {
if (req.cycles_left != 0)
printf(" !%0x", req.tag);
else
printf(" %0x", req.tag);
}
printf("}\n");*/
}
// handle DRAM stalls
@@ -293,10 +302,19 @@ void opae_sim::avs_bus() {
if (vortex_afu_->avs_read) {
assert(0 == vortex_afu_->mem_bank_select);
dram_rd_req_t dram_req;
dram_req.cycles_left = DRAM_LATENCY;
dram_req.cycles_left = DRAM_LATENCY;
unsigned base_addr = (vortex_afu_->avs_address * CACHE_BLOCK_SIZE);
ram_.read(base_addr, CACHE_BLOCK_SIZE, dram_req.block.data());
dram_req.tag = base_addr;
dram_reads_.emplace_back(dram_req);
/*printf("%0ld: VLSIM: DRAM req: addr=%x, pending={", timestamp, base_addr);
for (auto& req : dram_reads_) {
if (req.cycles_left != 0)
printf(" !%0x", req.tag);
else
printf(" %0x", req.tag);
}
printf("}\n");*/
}
}