synthesis fixes

rtl/VX_cache/VX_cache_core_req_bank_sel.v

@@ -1,4 +1,6 @@
 
+`include "VX_cache_config.v"
+
 module VX_cache_core_req_bank_sel (
 	input  wire [`NUMBER_REQUESTS-1:0]                       core_req_valid,
 	input  wire [`NUMBER_REQUESTS-1:0][31:0]                 core_req_addr,

rtl/VX_cache/VX_fill_invalidator.v

@@ -1,4 +1,3 @@
-
 `include "VX_cache_config.v"
 
 module VX_fill_invalidator (
@@ -30,19 +29,19 @@ module VX_fill_invalidator (
 
 		integer curr_fill;
 		always @(*) begin
-			assign invalidate_fill = 0;
-			assign success_found   = 0;
-			assign success_index   = 0;
+			invalidate_fill = 0;
+			success_found   = 0;
+			success_index   = 0;
 			for (curr_fill = 0; curr_fill < `FILL_INVALIDAOR_SIZE; curr_fill=curr_fill+1) begin
 
 				if (fill_addr[31:`LINE_SELECT_ADDR_START] == fills_address[curr_fill][31:`LINE_SELECT_ADDR_START]) begin
 					if (possible_fill && fills_active[curr_fill]) begin
-						assign invalidate_fill = 1;
+						invalidate_fill = 1;
 					end
 
 					if (success_fill) begin
-						assign success_found = 1;
-						assign success_index = curr_fill;
+						success_found = 1;
+						success_index = curr_fill;
 					end
 				end
 			end

rtl/VX_cache/VX_tag_data_structure.v

@@ -1,3 +1,5 @@
+`include "VX_cache_config.v"
+
 module VX_tag_data_structure (
 	input  wire                            clk,
 	input  wire                            reset,