diff --git a/driver/simx/vortex.cpp b/driver/simx/vortex.cpp
index 95b57370..8f448dd8 100644
--- a/driver/simx/vortex.cpp
+++ b/driver/simx/vortex.cpp
@@ -159,7 +159,7 @@ public:
     }    
 
     int set_csr(int core_id, int addr, unsigned value) {
-        cores_.at(core_id)->set_csr(addr, value);
+        cores_.at(core_id)->set_csr(addr, value, 0, 0);
         return 0;
     }
 
diff --git a/simX/decode.cpp b/simX/decode.cpp
index d74cff86..e9745344 100644
--- a/simX/decode.cpp
+++ b/simX/decode.cpp
@@ -78,7 +78,7 @@ static const char* op_string(const Instr &instr) {
     }
   case Opcode::I_INST:
     switch (func3) {
-    case 0: return func7 ? "SUBI" : "ADDI";
+    case 0: return "ADDI";
     case 1: return "SLLI";
     case 2: return "SLTI";
     case 3: return "SLTIU";
@@ -163,10 +163,10 @@ static const char* op_string(const Instr &instr) {
       default:
         std::abort();
       }
-    case 0x60: return rs2 ? "FCVT.WU" : "FCVT.W";
-    case 0x68: return rs2 ? "FCVT.S" : "FCVT.S";
+    case 0x60: return rs2 ? "FCVT.WU.S" : "FCVT.W.S";
+    case 0x68: return rs2 ? "FCVT.S.WU" : "FCVT.S.W";
     case 0x70: return func3 ? "FLASS" : "FMV.X.W";
-    case 0x78: return "FMV.W";
+    case 0x78: return "FMV.W.X";
     default:
       std::abort();
     }
@@ -283,11 +283,18 @@ std::shared_ptr<Instr> Decoder::decode(Word code) {
 
   case InstType::R_TYPE:
     if (op == Opcode::FCI) {      
-      instr->setSrcFReg(rs1);
+      switch (func7) {
+      case 0x68: // FCVT.S.W, FCVT.S.WU
+      case 0x78: // FMV.W.X
+        instr->setSrcReg(rs1);
+        break;
+      default:
+        instr->setSrcFReg(rs1);
+      }      
       instr->setSrcFReg(rs2);
       switch (func7) {
       case 0x50: // FLE, FLT, FEQ
-      case 0x60: // FCVT.WU, FCVT.W
+      case 0x60: // FCVT.WU.S, FCVT.W.S
       case 0x70: // FLASS, FMV.X.W
         instr->setDestReg(rd);
         break;
@@ -304,12 +311,11 @@ std::shared_ptr<Instr> Decoder::decode(Word code) {
     break;
 
   case InstType::I_TYPE: {
-    if (op == Opcode::FCI || op == Opcode::FL) {
-      instr->setDestFReg(rd);
-      instr->setSrcFReg(rs1);
+    instr->setSrcReg(rs1);
+    if (op == Opcode::FL) {
+      instr->setDestFReg(rd);      
     } else {
       instr->setDestReg(rd);
-      instr->setSrcReg(rs1);
     }    
     instr->setFunc3(func3);
     instr->setFunc7(func7);    
@@ -320,12 +326,11 @@ std::shared_ptr<Instr> Decoder::decode(Word code) {
     }
   } break;
 
-  case InstType::S_TYPE: {
+  case InstType::S_TYPE: {    
+    instr->setSrcReg(rs1);
     if (op == Opcode::FS) {
-      instr->setSrcFReg(rs1);
       instr->setSrcFReg(rs2);
     } else {
-      instr->setSrcReg(rs1);
       instr->setSrcReg(rs2);
     }
     instr->setFunc3(func3);
diff --git a/simX/execute.cpp b/simX/execute.cpp
index 39e4efb2..35cbfbf7 100644
--- a/simX/execute.cpp
+++ b/simX/execute.cpp
@@ -41,6 +41,33 @@ static bool checkUnanimous(unsigned p,
   return true;
 }
 
+static void update_fcrs(Core* core, int tid, int wid, bool outOfRange = false) {
+  if (fetestexcept(FE_INEXACT)) {
+    core->set_csr(CSR_FCSR, core->get_csr(CSR_FCSR, tid, wid) | 0x1, tid, wid); // set NX bit
+    core->set_csr(CSR_FFLAGS, core->get_csr(CSR_FFLAGS, tid, wid) | 0x1, tid, wid); // set NX bit
+  }
+  
+  if (fetestexcept(FE_UNDERFLOW)) {
+    core->set_csr(CSR_FCSR, core->get_csr(CSR_FCSR, tid, wid) | 0x2, tid, wid); // set UF bit
+    core->set_csr(CSR_FFLAGS, core->get_csr(CSR_FFLAGS, tid, wid) | 0x2, tid, wid); // set UF bit
+  }
+
+  if (fetestexcept(FE_OVERFLOW)) {
+    core->set_csr(CSR_FCSR, core->get_csr(CSR_FCSR, tid, wid) | 0x4, tid, wid); // set OF bit
+    core->set_csr(CSR_FFLAGS, core->get_csr(CSR_FFLAGS, tid, wid) | 0x4, tid, wid); // set OF bit
+  }
+
+  if (fetestexcept(FE_DIVBYZERO)) {
+    core->set_csr(CSR_FCSR, core->get_csr(CSR_FCSR, tid, wid) | 0x8, tid, wid); // set DZ bit
+    core->set_csr(CSR_FFLAGS, core->get_csr(CSR_FFLAGS, tid, wid) | 0x8, tid, wid); // set DZ bit
+  } 
+
+  if (fetestexcept(FE_INVALID) || outOfRange) {
+    core->set_csr(CSR_FCSR, core->get_csr(CSR_FCSR, tid, wid) | 0x10, tid, wid); // set NV bit
+    core->set_csr(CSR_FFLAGS, core->get_csr(CSR_FFLAGS, tid, wid) | 0x10, tid, wid); // set NV bit
+  }
+}
+
 void Warp::execute(const Instr &instr, Pipeline *pipeline) {
   assert(tmask_.any());
 
@@ -55,7 +82,6 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
   int rdest  = instr.getRDest();
   int rsrc0  = instr.getRSrc(0);
   int rsrc1  = instr.getRSrc(1);
-  int rsrc2  = instr.getRSrc(2);
   Word immsrc= instr.getImm();
   Word vmask = instr.getVmask();
 
@@ -68,8 +94,7 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
     auto &fregs = fRegFile_.at(t);
 
     Word rsdata[3];
-    Word iresult;
-    Word fresult;
+    Word rddata;
 
     int num_rsrcs = instr.getNRSrc();
     if (num_rsrcs) {    
@@ -97,88 +122,88 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
     case NOP:
       break;
     case LUI_INST:
-      iresult = (immsrc << 12) & 0xfffff000;
+      rddata = (immsrc << 12) & 0xfffff000;
       break;
     case AUIPC_INST:
-      iresult = ((immsrc << 12) & 0xfffff000) + PC_;
+      rddata = ((immsrc << 12) & 0xfffff000) + PC_;
       break;
     case R_INST: {
       if (func7 & 0x1) {
         switch (func3) {
         case 0:
           // MUL
-          iresult = ((WordI)iregs[rsrc0]) * ((WordI)iregs[rsrc1]);
+          rddata = ((WordI)rsdata[0]) * ((WordI)rsdata[1]);
           break;
         case 1: {
           // MULH
-          int64_t first = (int64_t)iregs[rsrc0];
-          if (iregs[rsrc0] & 0x80000000) {
+          int64_t first = (int64_t)rsdata[0];
+          if (rsdata[0] & 0x80000000) {
             first = first | 0xFFFFFFFF00000000;
           }
-          int64_t second = (int64_t)iregs[rsrc1];
-          if (iregs[rsrc1] & 0x80000000) {
+          int64_t second = (int64_t)rsdata[1];
+          if (rsdata[1] & 0x80000000) {
             second = second | 0xFFFFFFFF00000000;
           }
           uint64_t result = first * second;
-          iresult = (result >> 32) & 0xFFFFFFFF;
+          rddata = (result >> 32) & 0xFFFFFFFF;
         } break;
         case 2: {
           // MULHSU          
-          int64_t first = (int64_t)iregs[rsrc0];
-          if (iregs[rsrc0] & 0x80000000) {
+          int64_t first = (int64_t)rsdata[0];
+          if (rsdata[0] & 0x80000000) {
             first = first | 0xFFFFFFFF00000000;
           }
-          int64_t second = (int64_t)iregs[rsrc1];
-          iresult = ((first * second) >> 32) & 0xFFFFFFFF;
+          int64_t second = (int64_t)rsdata[1];
+          rddata = ((first * second) >> 32) & 0xFFFFFFFF;
         } break;
         case 3: {
           // MULHU
-          uint64_t first = (uint64_t)iregs[rsrc0];
-          uint64_t second = (uint64_t)iregs[rsrc1];
-          iresult = ((first * second) >> 32) & 0xFFFFFFFF;
+          uint64_t first = (uint64_t)rsdata[0];
+          uint64_t second = (uint64_t)rsdata[1];
+          rddata = ((first * second) >> 32) & 0xFFFFFFFF;
         } break;
         case 4: {
           // DIV
-          WordI dividen = iregs[rsrc0];
-          WordI divisor = iregs[rsrc1];
+          WordI dividen = rsdata[0];
+          WordI divisor = rsdata[1];
           if (divisor == 0) {
-            iresult = -1;
+            rddata = -1;
           } else if (dividen == WordI(0x80000000) && divisor == WordI(0xffffffff)) {
-            iresult = dividen;
+            rddata = dividen;
           } else {
-            iresult = dividen / divisor;
+            rddata = dividen / divisor;
           }
         } break;
         case 5: {
           // DIVU
-          Word dividen = iregs[rsrc0];
-          Word divisor = iregs[rsrc1];
+          Word dividen = rsdata[0];
+          Word divisor = rsdata[1];
           if (divisor == 0) {
-            iresult = -1;
+            rddata = -1;
           } else {
-            iresult = dividen / divisor;
+            rddata = dividen / divisor;
           }
         } break;
         case 6: {
           // REM
-          WordI dividen = iregs[rsrc0];
-          WordI divisor = iregs[rsrc1];
-          if (iregs[rsrc1] == 0) {
-            iresult = dividen;
+          WordI dividen = rsdata[0];
+          WordI divisor = rsdata[1];
+          if (rsdata[1] == 0) {
+            rddata = dividen;
           } else if (dividen == WordI(0x80000000) && divisor == WordI(0xffffffff)) {
-            iresult = 0;
+            rddata = 0;
           } else {
-            iresult = dividen % divisor;
+            rddata = dividen % divisor;
           }
         } break;
         case 7: {
           // REMU
-          Word dividen = iregs[rsrc0];
-          Word divisor = iregs[rsrc1];
-          if (iregs[rsrc1] == 0) {
-            iresult = dividen;
+          Word dividen = rsdata[0];
+          Word divisor = rsdata[1];
+          if (rsdata[1] == 0) {
+            rddata = dividen;
           } else {
-            iresult = dividen % divisor;
+            rddata = dividen % divisor;
           }
         } break;
         default:
@@ -189,43 +214,35 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
         switch (func3) {
         case 0:
           if (func7) {
-            iresult = iregs[rsrc0] - iregs[rsrc1];
+            rddata = rsdata[0] - rsdata[1];
           } else {
-            iresult = iregs[rsrc0] + iregs[rsrc1];
+            rddata = rsdata[0] + rsdata[1];
           }
           break;
         case 1:
-          iresult = iregs[rsrc0] << iregs[rsrc1];
+          rddata = rsdata[0] << rsdata[1];
           break;
         case 2:
-          if (WordI(iregs[rsrc0]) < WordI(iregs[rsrc1])) {
-            iresult = 1;
-          } else {
-            iresult = 0;
-          }
+          rddata = (WordI(rsdata[0]) < WordI(rsdata[1]));
           break;
         case 3:
-          if (Word(iregs[rsrc0]) < Word(iregs[rsrc1])) {
-            iresult = 1;
-          } else {
-            iresult = 0;
-          }
+          rddata = (Word(rsdata[0]) < Word(rsdata[1]));
           break;
         case 4:
-          iresult = iregs[rsrc0] ^ iregs[rsrc1];
+          rddata = rsdata[0] ^ rsdata[1];
           break;
         case 5:
           if (func7) {
-            iresult = WordI(iregs[rsrc0]) >> WordI(iregs[rsrc1]);
+            rddata = WordI(rsdata[0]) >> WordI(rsdata[1]);
           } else {
-            iresult = Word(iregs[rsrc0]) >> Word(iregs[rsrc1]);
+            rddata = Word(rsdata[0]) >> Word(rsdata[1]);
           }
           break;
         case 6:
-          iresult = iregs[rsrc0] | iregs[rsrc1];
+          rddata = rsdata[0] | rsdata[1];
           break;
         case 7:
-          iresult = iregs[rsrc0] & iregs[rsrc1];
+          rddata = rsdata[0] & rsdata[1];
           break;
         default:
           std::abort();
@@ -236,50 +253,42 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
       switch (func3) {
       case 0:
         // ADDI
-        iresult = iregs[rsrc0] + immsrc;
+        rddata = rsdata[0] + immsrc;
         break;
       case 1:
         // SLLI
-        iresult = iregs[rsrc0] << immsrc;
+        rddata = rsdata[0] << immsrc;
         break;
       case 2:
         // SLTI
-        if (WordI(iregs[rsrc0]) < WordI(immsrc)) {
-          iresult = 1;
-        } else {
-          iresult = 0;
-        }
+        rddata = (WordI(rsdata[0]) < WordI(immsrc));
         break;
       case 3: {
         // SLTIU
-        if (Word(iregs[rsrc0]) < Word(immsrc)) {
-          iresult = 1;
-        } else {
-          iresult = 0;
-        }
+        rddata = (Word(rsdata[0]) < Word(immsrc));
       } break;
       case 4:
         // XORI
-        iresult = iregs[rsrc0] ^ immsrc;
+        rddata = rsdata[0] ^ immsrc;
         break;
       case 5:
         if (func7) {
           // SRAI
-          Word result = WordI(iregs[rsrc0]) >> immsrc;
-          iresult = result;
+          Word result = WordI(rsdata[0]) >> immsrc;
+          rddata = result;
         } else {
           // SRLI
-          Word result = Word(iregs[rsrc0]) >> immsrc;
-          iresult = result;
+          Word result = Word(rsdata[0]) >> immsrc;
+          rddata = result;
         }
         break;
       case 6:
         // ORI
-        iresult = iregs[rsrc0] | immsrc;
+        rddata = rsdata[0] | immsrc;
         break;
       case 7:
         // ANDI
-        iresult = iregs[rsrc0] & immsrc;
+        rddata = rsdata[0] & immsrc;
         break;
       default:
         std::abort();
@@ -289,37 +298,37 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
       switch (func3) {
       case 0:
         // BEQ
-        if (iregs[rsrc0] == iregs[rsrc1]) {
+        if (rsdata[0] == rsdata[1]) {
           nextPC = PC_ + immsrc;
         }
         break;
       case 1:
         // BNE
-        if (iregs[rsrc0] != iregs[rsrc1]) {
+        if (rsdata[0] != rsdata[1]) {
           nextPC = PC_ + immsrc;
         }
         break;
       case 4:
         // BLT
-        if (WordI(iregs[rsrc0]) < WordI(iregs[rsrc1])) {
+        if (WordI(rsdata[0]) < WordI(rsdata[1])) {
           nextPC = PC_ + immsrc;
         }
         break;
       case 5:
         // BGE
-        if (WordI(iregs[rsrc0]) >= WordI(iregs[rsrc1])) {
+        if (WordI(rsdata[0]) >= WordI(rsdata[1])) {
           nextPC = PC_ + immsrc;
         }
         break;
       case 6:
         // BLTU
-        if (Word(iregs[rsrc0]) < Word(iregs[rsrc1])) {
+        if (Word(rsdata[0]) < Word(rsdata[1])) {
           nextPC = PC_ + immsrc;
         }
         break;
       case 7:
         // BGEU
-        if (Word(iregs[rsrc0]) >= Word(iregs[rsrc1])) {
+        if (Word(rsdata[0]) >= Word(rsdata[1])) {
           nextPC = PC_ + immsrc;
         }
         break;
@@ -328,61 +337,61 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
       runOnce = true;
       break;
     case JAL_INST:
-      iresult = nextPC;
+      rddata = nextPC;
       nextPC = PC_ + immsrc;  
       pipeline->stall_warp = true;
       runOnce = true;
       break;
     case JALR_INST:
-      iresult = nextPC;
-      nextPC = iregs[rsrc0] + immsrc;
+      rddata = nextPC;
+      nextPC = rsdata[0] + immsrc;
       pipeline->stall_warp = true;
       runOnce = true;
       break;
     case L_INST: {
-      Word memAddr   = ((iregs[rsrc0] + immsrc) & 0xFFFFFFFC); // Address word alignment
-      Word shift_by  = ((iregs[rsrc0] + immsrc) & 0x00000003) * 8;
+      Word memAddr   = ((rsdata[0] + immsrc) & 0xFFFFFFFC); // word aligned
+      Word shift_by  = ((rsdata[0] + immsrc) & 0x00000003) * 8;
       Word data_read = core_->dcache_read(memAddr, 0);
       D(3, "LOAD MEM ADDRESS: " << std::hex << memAddr << ", DATA=0x" << data_read);
       switch (func3) {
       case 0:
         // LBI
-        iresult = signExt((data_read >> shift_by) & 0xFF, 8, 0xFF);
+        rddata = signExt((data_read >> shift_by) & 0xFF, 8, 0xFF);
         break;
       case 1:
         // LHI
-        iresult = signExt((data_read >> shift_by) & 0xFFFF, 16, 0xFFFF);
+        rddata = signExt((data_read >> shift_by) & 0xFFFF, 16, 0xFFFF);
         break;
       case 2:
         // LW
-        iresult = data_read;
+        rddata = data_read;
         break;
       case 4:
         // LBU
-        iresult = Word((data_read >> shift_by) & 0xFF);
+        rddata = Word((data_read >> shift_by) & 0xFF);
         break;
       case 5:
         // LHU
-        iresult = Word((data_read >> shift_by) & 0xFFFF);
+        rddata = Word((data_read >> shift_by) & 0xFFFF);
         break;
       default:
         std::abort();        
       }
     } break;
     case S_INST: {
-      Word memAddr = iregs[rsrc0] + immsrc;
+      Word memAddr = rsdata[0] + immsrc;
       switch (func3) {
       case 0:
         // SB
-        core_->dcache_write(memAddr, iregs[rsrc1] & 0x000000FF, 0, 1);
+        core_->dcache_write(memAddr, rsdata[1] & 0x000000FF, 0, 1);
         break;
       case 1:
         // SH
-        core_->dcache_write(memAddr, iregs[rsrc1], 0, 2);
+        core_->dcache_write(memAddr, rsdata[1], 0, 2);
         break;
       case 2:
         // SW
-        core_->dcache_write(memAddr, iregs[rsrc1], 0, 4);
+        core_->dcache_write(memAddr, rsdata[1], 0, 4);
         break;
       default:
         std::abort();
@@ -403,32 +412,32 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
         break;
       case 1:
         // CSRRW
-        iresult = csr_value;
-        core_->set_csr(csr_addr, iregs[rsrc0], t, id_);
+        rddata = csr_value;
+        core_->set_csr(csr_addr, rsdata[0], t, id_);
         break;
       case 2:
         // CSRRS
-        iresult = csr_value;
-        core_->set_csr(csr_addr, csr_value | iregs[rsrc0], t, id_);
+        rddata = csr_value;
+        core_->set_csr(csr_addr, csr_value | rsdata[0], t, id_);
         break;
       case 3:
         // CSRRC
-        iresult = csr_value;
-        core_->set_csr(csr_addr, csr_value & ~iregs[rsrc0], t, id_);
+        rddata = csr_value;
+        core_->set_csr(csr_addr, csr_value & ~rsdata[0], t, id_);
         break;
       case 5:
         // CSRRWI
-        iresult = csr_value;
+        rddata = csr_value;
         core_->set_csr(csr_addr, rsrc0, t, id_);
         break;
       case 6:
         // CSRRSI
-        iresult = csr_value;
+        rddata = csr_value;
         core_->set_csr(csr_addr, csr_value | rsrc0, t, id_);
         break;
       case 7:
         // CSRRCI
-        iresult = csr_value;
+        rddata = csr_value;
         core_->set_csr(csr_addr, csr_value & ~rsrc0, t, id_);
         break;
       default:
@@ -442,14 +451,14 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
       break;
     case (FL | VL):
       if (func3 == 0x2) {
-        Word memAddr = iregs[rsrc0] + immsrc;
+        Word memAddr = rsdata[0] + immsrc;
         Word data_read = core_->dcache_read(memAddr, 0);        
         D(3, "LOAD MEM ADDRESS: " << std::hex << memAddr << ", DATA=0x" << data_read);
-        fresult = data_read;
+        rddata = data_read;
       } else {  
         D(3, "Executing vector load");      
         D(4, "lmul: " << vtype_.vlmul << " VLEN:" << (core_->arch().vsize() * 8) << "sew: " << vtype_.vsew);
-        D(4, "src: " << rsrc0 << " " << iregs[rsrc0]);
+        D(4, "src: " << rsrc0 << " " << rsdata[0]);
         D(4, "dest" << rdest);
         D(4, "width" << instr.getVlsWidth());
 
@@ -458,12 +467,11 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
         switch (instr.getVlsWidth()) {
         case 6: { //load word and unit strided (not checking for unit stride)
           for (int i = 0; i < vl_; i++) {
-            Word memAddr = ((iregs[rsrc0]) & 0xFFFFFFFC) + (i * vtype_.vsew / 8);
+            Word memAddr = ((rsdata[0]) & 0xFFFFFFFC) + (i * vtype_.vsew / 8);
             Word data_read = core_->dcache_read(memAddr, 0);
             D(4, "Mem addr: " << std::hex << memAddr << " Data read " << data_read);
             int *result_ptr = (int *)(vd.data() + i);
-            *result_ptr = data_read;
-            
+            *result_ptr = data_read;            
             D(3, "STORE MEM ADDRESS: " << std::hex << memAddr);
           }
         } break;
@@ -475,12 +483,12 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
       break;
     case (FS | VS):
       if (func3 == 0x2) {
-        Word memAddr = iregs[rsrc0] + immsrc;
-        core_->dcache_write(memAddr, fregs[rsrc1], 0, 4);
+        Word memAddr = rsdata[0] + immsrc;
+        core_->dcache_write(memAddr, rsdata[1], 0, 4);
         D(3, "STORE MEM ADDRESS: " << std::hex << memAddr);
       } else {
         for (int i = 0; i < vl_; i++) {
-          Word memAddr = iregs[rsrc0] + (i * vtype_.vsew / 8);
+          Word memAddr = rsdata[0] + (i * vtype_.vsew / 8);
           switch (instr.getVlsWidth()) {
           case 6: {
             //store word and unit strided (not checking for unit stride)          
@@ -503,21 +511,21 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
         case 0x0c: //FDIV
         case 0x2c: //FSQRT
         {
-          if (fpBinIsNan(fregs[rsrc0]) || fpBinIsNan(fregs[rsrc1])) { 
+          if (fpBinIsNan(rsdata[0]) || fpBinIsNan(rsdata[1])) { 
             // if one of op is NaN, one of them is not quiet NaN, them set FCSR
-            if ((fpBinIsNan(fregs[rsrc0])==2) | (fpBinIsNan(fregs[rsrc1])==2)) {
+            if ((fpBinIsNan(rsdata[0])==2) | (fpBinIsNan(rsdata[1])==2)) {
               core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit                
               core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit
             }
-            if (fpBinIsNan(fregs[rsrc0]) && fpBinIsNan(fregs[rsrc1])) 
-              fresult = 0x7fc00000;  // canonical(quiet) NaN 
-            else if (fpBinIsNan(fregs[rsrc0]))
-              fresult = fregs[rsrc1];
+            if (fpBinIsNan(rsdata[0]) && fpBinIsNan(rsdata[1])) 
+              rddata = 0x7fc00000;  // canonical(quiet) NaN 
+            else if (fpBinIsNan(rsdata[0]))
+              rddata = rsdata[1];
             else
-              fresult = fregs[rsrc0];
+              rddata = rsdata[0];
           } else {
-            float fpsrc_0 = intregToFloat(fregs[rsrc0]);
-            float fpsrc_1 = intregToFloat(fregs[rsrc1]);
+            float fpsrc_0 = intregToFloat(rsdata[0]);
+            float fpsrc_1 = intregToFloat(rsdata[1]);
             float fpDest;                          
             
             feclearexcept(FE_ALL_EXCEPT);
@@ -535,102 +543,80 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
             else {
               std::abort();
             }            
-            // fcsr defined in riscv
-            if (fetestexcept(FE_INEXACT)) {
-              core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x1, t, id_); // set NX bit
-              core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x1, t, id_); // set NX bit
-            }
             
-            if (fetestexcept(FE_UNDERFLOW)) {
-              core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x2, t, id_); // set UF bit
-              core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x2, t, id_); // set UF bit
-            }
-
-            if (fetestexcept(FE_OVERFLOW)) {
-              core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x4, t, id_); // set OF bit
-              core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x4, t, id_); // set OF bit
-            }
-
-            if (fetestexcept(FE_DIVBYZERO)) {
-              core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x8, t, id_); // set DZ bit
-              core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x8, t, id_); // set DZ bit
-            } 
-
-            if (fetestexcept(FE_INVALID)) {
-              core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NX bit
-              core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NX bit
-            }
+            // update fcsrs
+            update_fcrs(core_, t, id_);
 
             D(4, "fpDest: " << fpDest);
             if (fpBinIsNan(floatToBin(fpDest)) == 0) {
-              fresult = floatToBin(fpDest);
+              rddata = floatToBin(fpDest);
             } else  {              
               // According to risc-v spec p.64 section 11.3
               // If the result is NaN, it is the canonical NaN
-              fresult = 0x7fc00000;
+              rddata = 0x7fc00000;
             }          
           }
         } break;
 
         // FSGNJ.S, FSGNJN.S, FSGNJX.S
         case 0x10: {
-          bool     fsign1 = fregs[rsrc0] & 0x80000000;
-          uint32_t fdata1 = fregs[rsrc0] & 0x7FFFFFFF;
-          bool     fsign2 = fregs[rsrc1] & 0x80000000;
+          bool     fsign1 = rsdata[0] & 0x80000000;
+          uint32_t fdata1 = rsdata[0] & 0x7FFFFFFF;
+          bool     fsign2 = rsdata[1] & 0x80000000;
           switch (func3) {            
           case 0: // FSGNJ.S
-            fresult = (fsign2 << 31) | fdata1;
+            rddata = (fsign2 << 31) | fdata1;
             break;          
           case 1: // FSGNJN.S
             fsign2 = !fsign2;
-            fresult = (fsign2 << 31) | fdata1;
+            rddata = (fsign2 << 31) | fdata1;
             break;          
           case 2: { // FSGNJX.S
             bool sign = fsign1 ^ fsign2;
-            fresult = (sign << 31) | fdata1;
+            rddata = (sign << 31) | fdata1;
             } break;
           }
         } break;
 
         // FMIN.S, FMAX.S
         case 0x14: {
-          if (fpBinIsNan(fregs[rsrc0]) || fpBinIsNan(fregs[rsrc1])) { // if one of src is NaN
+          if (fpBinIsNan(rsdata[0]) || fpBinIsNan(rsdata[1])) { // if one of src is NaN
             // one of them is not quiet NaN, them set FCSR
-            if ((fpBinIsNan(fregs[rsrc0])==2) | (fpBinIsNan(fregs[rsrc1])==2)) {
+            if ((fpBinIsNan(rsdata[0])==2) | (fpBinIsNan(rsdata[1])==2)) {
               core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit
               core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit
             }
-            if (fpBinIsNan(fregs[rsrc0]) && fpBinIsNan(fregs[rsrc1])) 
-              fresult = 0x7fc00000;  // canonical(quiet) NaN 
-            else if (fpBinIsNan(fregs[rsrc0]))
-              fresult = fregs[rsrc1];
+            if (fpBinIsNan(rsdata[0]) && fpBinIsNan(rsdata[1])) 
+              rddata = 0x7fc00000;  // canonical(quiet) NaN 
+            else if (fpBinIsNan(rsdata[0]))
+              rddata = rsdata[1];
             else
-              fresult = fregs[rsrc0];
+              rddata = rsdata[0];
           } else {
-            uint8_t sr0IsZero = fpBinIsZero(fregs[rsrc0]);
-            uint8_t sr1IsZero = fpBinIsZero(fregs[rsrc1]);
+            uint8_t sr0IsZero = fpBinIsZero(rsdata[0]);
+            uint8_t sr1IsZero = fpBinIsZero(rsdata[1]);
 
             if (sr0IsZero && sr1IsZero && (sr0IsZero != sr1IsZero)) { 
               // both are zero and not equal
               // handle corner case that compare +0 and -0              
               if (func3) {
                 // FMAX.S
-                fresult = (sr1IsZero==2) ? fregs[rsrc1] : fregs[rsrc0];
+                rddata = (sr1IsZero==2) ? rsdata[1] : rsdata[0];
               } else {
                 // FMIM.S
-                fresult = (sr1IsZero==2) ? fregs[rsrc0] : fregs[rsrc1];
+                rddata = (sr1IsZero==2) ? rsdata[0] : rsdata[1];
               }
             } else {
-              float rs1 = intregToFloat(fregs[rsrc0]);
-              float rs2 = intregToFloat(fregs[rsrc1]);              
+              float rs1 = intregToFloat(rsdata[0]);
+              float rs2 = intregToFloat(rsdata[1]);              
               if (func3) {
                 // FMAX.S
                 float fmax = std::max(rs1, rs2); 
-                fresult = floatToBin(fmax);
+                rddata = floatToBin(fmax);
               } else {
                 // FMIN.S
                 float fmin = std::min(rs1, rs2);
-                fresult = floatToBin(fmin);
+                rddata = floatToBin(fmin);
               }
             }
           }
@@ -638,18 +624,18 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
         
         // FCVT.W.S FCVT.WU.S
         case 0x60: {          
-          float fpSrc = intregToFloat(fregs[rsrc0]);
+          float fpSrc = intregToFloat(rsdata[0]);
           Word result;
           bool outOfRange = false;          
           if (rsrc1 == 0) { 
             // FCVT.W.S
             // Convert floating point to 32-bit signed integer
-            if (fpSrc > pow(2.0, 31) - 1 || fpBinIsNan(fregs[rsrc0]) || fpBinIsInf(fregs[rsrc0]) == 2) {
+            if (fpSrc > pow(2.0, 31) - 1 || fpBinIsNan(rsdata[0]) || fpBinIsInf(rsdata[0]) == 2) {
               feclearexcept(FE_ALL_EXCEPT);              
               outOfRange = true;
               // result = 2^31 - 1
               result = 0x7FFFFFFF;
-            } else if (fpSrc < -1*pow(2.0, 31) || fpBinIsInf(fregs[rsrc0]) == 1) {
+            } else if (fpSrc < -1*pow(2.0, 31) || fpBinIsInf(rsdata[0]) == 1) {
               feclearexcept(FE_ALL_EXCEPT);              
               outOfRange = true;
               // result = -1*2^31
@@ -661,12 +647,12 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
           } else {
             // FCVT.WU.S
             // Convert floating point to 32-bit unsigned integer
-            if (fpSrc > pow(2.0, 32) - 1 || fpBinIsNan(fregs[rsrc0]) || fpBinIsInf(fregs[rsrc0]) == 2) {
+            if (fpSrc > pow(2.0, 32) - 1 || fpBinIsNan(rsdata[0]) || fpBinIsInf(rsdata[0]) == 2) {
               feclearexcept(FE_ALL_EXCEPT);              
               outOfRange = true;
               // result = 2^32 - 1
               result = 0xFFFFFFFF;
-            } else if (fpSrc <= -1.0 || fpBinIsInf(fregs[rsrc0]) == 1) {
+            } else if (fpSrc <= -1.0 || fpBinIsInf(rsdata[0]) == 1) {
               feclearexcept(FE_ALL_EXCEPT);              
               outOfRange = true;
               // result = 0
@@ -676,33 +662,11 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
               result = (uint32_t) fpSrc;
             }
           }
-          
-          if (fetestexcept(FE_INEXACT)) {
-            core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x1, t, id_); // set NX bit
-            core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x1, t, id_); // set NX bit
-          }
-          
-          if (fetestexcept(FE_UNDERFLOW)) {
-            core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x2, t, id_); // set UF bit
-            core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x2, t, id_); // set UF bit
-          }
 
-          if (fetestexcept(FE_OVERFLOW)) {
-            core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x4, t, id_); // set OF bit
-            core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x4, t, id_); // set OF bit
-          }
+          // update fcsrs
+          update_fcrs(core_, t, id_, outOfRange);
 
-          if (fetestexcept(FE_DIVBYZERO)) {
-            core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x8, t, id_); // set DZ bit
-            core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x8, t, id_); // set DZ bit
-          } 
-
-          if (fetestexcept(FE_INVALID) || outOfRange) {
-            core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit
-            core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit
-          }
-
-          iresult = result;
+          rddata = result;
         } break;
         
         // FMV.X.W FCLASS.S
@@ -711,33 +675,33 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
           if (func3) {
             // Examine the value in fpReg rs1 and write to integer rd
             // a 10-bit mask to indicate the class of the fp number
-            iresult = 0; // clear all bits
+            rddata = 0; // clear all bits
 
-            bool fsign = fregs[rsrc0] & 0x80000000;
-            uint32_t expo = (fregs[rsrc0]>>23) & 0x000000FF;
-            uint32_t fraction = fregs[rsrc0] & 0x007FFFFF;
+            bool fsign = rsdata[0] & 0x80000000;
+            uint32_t expo = (rsdata[0]>>23) & 0x000000FF;
+            uint32_t fraction = rsdata[0] & 0x007FFFFF;
 
             if ((expo==0) && (fraction==0)) {
-             iresult = fsign ? (1<<3) : (1<<4); // +/- 0
+             rddata = fsign ? (1<<3) : (1<<4); // +/- 0
             } else if ((expo==0) && (fraction!=0)) {
-              iresult = fsign ? (1<<2) : (1<<5); // +/- subnormal
+              rddata = fsign ? (1<<2) : (1<<5); // +/- subnormal
             } else if ((expo==0xFF) && (fraction==0)) {
-              iresult = fsign ? (1<<0) : (1<<7); // +/- infinity
+              rddata = fsign ? (1<<0) : (1<<7); // +/- infinity
             } else if ((expo==0xFF) && (fraction!=0)) { 
               if (!fsign && (fraction == 0x00400000)) {
-                iresult = (1<<9);               // quiet NaN
+                rddata = (1<<9);               // quiet NaN
               } else { 
-                iresult = (1<<8);               // signaling NaN
+                rddata = (1<<8);               // signaling NaN
               }
             } else {
-              iresult = fsign ? (1<<1) : (1<<6); // +/- normal
+              rddata = fsign ? (1<<1) : (1<<6); // +/- normal
             }
           } else {          
             // FMV.X.W
             // Move bit values from floating-point register rs1 to integer register rd
             // Since we are using integer register to represent floating point register, 
             // just simply assign here.
-            iresult = fregs[rsrc0];
+            rddata = rsdata[0];
           } 
         } break;
         
@@ -746,7 +710,7 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
         case 0x50: {
           // TODO: FLT.S and FLE.S perform IEEE 754-2009, signaling comparisons, set
           // TODO: the invalid operation exception flag if either input is NaN
-          if (fpBinIsNan(fregs[rsrc0]) || fpBinIsNan(fregs[rsrc1])) {
+          if (fpBinIsNan(rsdata[0]) || fpBinIsNan(rsdata[1])) {
             // FLE.S or FLT.S
             if (func3 == 0 || func3 == 1) {
               // If either input is NaN, set NV bit
@@ -754,27 +718,27 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
               core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit
             } else { // FEQ.S
               // Only set NV bit if it is signaling NaN
-              if (fpBinIsNan(fregs[rsrc0]) == 2 || fpBinIsNan(fregs[rsrc1]) == 2) {
+              if (fpBinIsNan(rsdata[0]) == 2 || fpBinIsNan(rsdata[1]) == 2) {
                 // If either input is NaN, set NV bit
                 core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit
                 core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit
               }
             }
             // The result is 0 if either operand is NaN
-            iresult = 0;
+            rddata = 0;
           } else {
             switch(func3) {              
             case 0: {
               // FLE.S
-              iresult = (intregToFloat(fregs[rsrc0]) <= intregToFloat(fregs[rsrc1]));
+              rddata = (intregToFloat(rsdata[0]) <= intregToFloat(rsdata[1]));
             } break;              
             case 1: {
               // FLT.S
-              iresult = (intregToFloat(fregs[rsrc0]) < intregToFloat(fregs[rsrc1]));
+              rddata = (intregToFloat(rsdata[0]) < intregToFloat(rsdata[1]));
             } break;              
             case 2: {
               // FEQ.S
-              iresult = (intregToFloat(fregs[rsrc0]) == intregToFloat(fregs[rsrc1]));
+              rddata = (intregToFloat(rsdata[0]) == intregToFloat(rsdata[1]));
             } break;
             default:
               std::abort();
@@ -786,13 +750,13 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
           // Cast integer to floating point              
           if (rsrc1) {
             // FCVT.S.WU: convert 32-bit unsigned integer to floating point
-            float data = iregs[rsrc0];      
-            fresult = floatToBin(data);
+            float data = rsdata[0];      
+            rddata = floatToBin(data);
           } else {
             // FCVT.S.W: convert 32-bit signed integer to floating point
-            // iregs[rsrc0] is actually a unsigned number
-            float data = (WordI)iregs[rsrc0];
-            fresult = floatToBin(data);
+            // rsdata[0] is actually a unsigned number
+            float data = (WordI)rsdata[0];
+            rddata = floatToBin(data);
           }
         break;
 
@@ -801,7 +765,7 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
           // Move bit values from integer register rs1 to floating register rd
           // Since we are using integer register to represent floating point register, 
           // just simply assign here.
-          fresult = iregs[rsrc0];
+          rddata = rsdata[0];
         }
         break;
       }
@@ -812,21 +776,21 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
     case FMNMADD:
     case FMNMSUB: {
       // multiplicands are infinity and zero, them set FCSR
-      if (fpBinIsZero(fregs[rsrc0]) || fpBinIsZero(fregs[rsrc1]) || fpBinIsInf(fregs[rsrc0]) || fpBinIsInf(fregs[rsrc1])) {
+      if (fpBinIsZero(rsdata[0]) || fpBinIsZero(rsdata[1]) || fpBinIsInf(rsdata[0]) || fpBinIsInf(rsdata[1])) {
         core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit
         core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit
       }
-      if (fpBinIsNan(fregs[rsrc0]) || fpBinIsNan(fregs[rsrc1]) || fpBinIsNan(fregs[rsrc2])) { 
+      if (fpBinIsNan(rsdata[0]) || fpBinIsNan(rsdata[1]) || fpBinIsNan(rsdata[2])) { 
         // if one of op is NaN, if addend is not quiet NaN, them set FCSR
-        if ((fpBinIsNan(fregs[rsrc0])==2) | (fpBinIsNan(fregs[rsrc1])==2) | (fpBinIsNan(fregs[rsrc1])==2)) {
+        if ((fpBinIsNan(rsdata[0])==2) | (fpBinIsNan(rsdata[1])==2) | (fpBinIsNan(rsdata[1])==2)) {
           core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit
           core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit          
         }
-        fresult = 0x7fc00000;  // canonical(quiet) NaN 
+        rddata = 0x7fc00000;  // canonical(quiet) NaN 
       } else {
-        float rs1 = intregToFloat(fregs[rsrc0]);
-        float rs2 = intregToFloat(fregs[rsrc1]);
-        float rs3 = intregToFloat(fregs[rsrc2]);
+        float rs1 = intregToFloat(rsdata[0]);
+        float rs2 = intregToFloat(rsdata[1]);
+        float rs3 = intregToFloat(rsdata[2]);
         float fpDest(0.0);
         feclearexcept(FE_ALL_EXCEPT);          
         switch (opcode) {
@@ -847,33 +811,10 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
             break;                 
         }  
 
-        // fcsr defined in riscv
-        if (fetestexcept(FE_INEXACT)) {
-          core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x1, t, id_); // set NX bit
-          core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x1, t, id_); // set NX bit
-        }
-        
-        if (fetestexcept(FE_UNDERFLOW)) {
-          core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x2, t, id_); // set UF bit
-          core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x2, t, id_); // set UF bit
-        }
+        // update fcsrs
+        update_fcrs(core_, t, id_);
 
-        if (fetestexcept(FE_OVERFLOW)) {
-          core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x4, t, id_); // set OF bit
-          core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x4, t, id_); // set OF bit
-        }
-
-        if (fetestexcept(FE_DIVBYZERO)) {
-          core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x8, t, id_); // set DZ bit
-          core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x8, t, id_); // set DZ bit
-        } 
-
-        if (fetestexcept(FE_INVALID)) {
-          core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit
-          core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit
-        }
-
-        fresult = floatToBin(fpDest);
+        rddata = floatToBin(fpDest);
       }
     }
     break;
@@ -881,7 +822,7 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
       switch (func3) {
       case 0: {
         // TMC
-        int active_threads = std::min<int>(iregs[rsrc0], num_threads);          
+        int active_threads = std::min<int>(rsdata[0], num_threads);          
         tmask_.reset();
         for (int i = 0; i < active_threads; ++i) {
           tmask_[i] = true;
@@ -892,11 +833,11 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
       } break;
       case 1: {
         // WSPAWN
-        int active_warps = std::min<int>(iregs[rsrc0], core_->arch().num_warps());
-        D(0, "Spawning " << (active_warps-1) << " warps at PC: " << std::hex << iregs[rsrc1]);
+        int active_warps = std::min<int>(rsdata[0], core_->arch().num_warps());
+        D(0, "Spawning " << (active_warps-1) << " warps at PC: " << std::hex << rsdata[1]);
         for (int i = 1; i < active_warps; ++i) {
           Warp &newWarp = core_->warp(i);
-          newWarp.setPC(iregs[rsrc1]);
+          newWarp.setPC(rsdata[1]);
           newWarp.setTmask(0, true);
         }
         pipeline->stall_warp = true;
@@ -905,7 +846,7 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
       case 2: {
         // SPLIT    
         if (checkUnanimous(rsrc0, iRegFile_, tmask_)) {
-          D(3, "Unanimous pred: " << rsrc0 << "  val: " << iregs[rsrc0] << "\n");
+          D(3, "Unanimous pred: " << rsrc0 << "  val: " << rsdata[0] << "\n");
           DomStackEntry e(tmask_);
           e.unanimous = true;
           domStack_.push(e);
@@ -966,7 +907,7 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
       case 4: {
         // BAR
         active_ = false;
-        core_->barrier(iregs[rsrc0], iregs[rsrc1], id_);
+        core_->barrier(rsdata[0], rsdata[1], id_);
         pipeline->stall_warp = true; 
         runOnce = true;       
       } break;
@@ -1745,8 +1686,8 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
           if (vtype_.vsew == 8) {
             for (int i = 0; i < vl_; i++) {
               uint8_t second = *(uint8_t *)(vr2.data() + i);
-              uint8_t result = (iregs[rsrc0] + second);
-              D(4, "Comparing " << iregs[rsrc0] << " + " << second << " = " << result);
+              uint8_t result = (rsdata[0] + second);
+              D(4, "Comparing " << rsdata[0] << " + " << second << " = " << result);
               *(uint8_t *)(vd.data() + i) = result;
             }
             for (int i = vl_; i < VLMAX; i++) {
@@ -1755,8 +1696,8 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
           } else if (vtype_.vsew == 16) {
             for (int i = 0; i < vl_; i++) {
               uint16_t second = *(uint16_t *)(vr2.data() + i);
-              uint16_t result = (iregs[rsrc0] + second);
-              D(4, "Comparing " << iregs[rsrc0] << " + " << second << " = " << result);
+              uint16_t result = (rsdata[0] + second);
+              D(4, "Comparing " << rsdata[0] << " + " << second << " = " << result);
               *(uint16_t *)(vd.data() + i) = result;
             }
             for (int i = vl_; i < VLMAX; i++) {
@@ -1765,8 +1706,8 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
           } else if (vtype_.vsew == 32) {
             for (int i = 0; i < vl_; i++) {
               uint32_t second = *(uint32_t *)(vr2.data() + i);
-              uint32_t result = (iregs[rsrc0] + second);
-              D(4, "Comparing " << iregs[rsrc0] << " + " << second << " = " << result);
+              uint32_t result = (rsdata[0] + second);
+              D(4, "Comparing " << rsdata[0] << " + " << second << " = " << result);
               *(uint32_t *)(vd.data() + i) = result;
             }
             for (int i = vl_; i < VLMAX; i++) {
@@ -1782,8 +1723,8 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
           if (vtype_.vsew == 8) {
             for (int i = 0; i < vl_; i++) {
               uint8_t second = *(uint8_t *)(vr2.data() + i);
-              uint8_t result = (iregs[rsrc0] * second);
-              D(4, "Comparing " << iregs[rsrc0] << " + " << second << " = " << result);
+              uint8_t result = (rsdata[0] * second);
+              D(4, "Comparing " << rsdata[0] << " + " << second << " = " << result);
               *(uint8_t *)(vd.data() + i) = result;
             }
             for (int i = vl_; i < VLMAX; i++) {
@@ -1792,8 +1733,8 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
           } else if (vtype_.vsew == 16) {
             for (int i = 0; i < vl_; i++) {
               uint16_t second = *(uint16_t *)(vr2.data() + i);
-              uint16_t result = (iregs[rsrc0] * second);
-              D(4, "Comparing " << iregs[rsrc0] << " + " << second << " = " << result);
+              uint16_t result = (rsdata[0] * second);
+              D(4, "Comparing " << rsdata[0] << " + " << second << " = " << result);
               *(uint16_t *)(vd.data() + i) = result;
             }
             for (int i = vl_; i < VLMAX; i++) {
@@ -1802,8 +1743,8 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
           } else if (vtype_.vsew == 32) {
             for (int i = 0; i < vl_; i++) {
               uint32_t second = *(uint32_t *)(vr2.data() + i);
-              uint32_t result = (iregs[rsrc0] * second);
-              D(4, "Comparing " << iregs[rsrc0] << " + " << second << " = " << result);
+              uint32_t result = (rsdata[0] * second);
+              D(4, "Comparing " << rsdata[0] << " + " << second << " = " << result);
               *(uint32_t *)(vd.data() + i) = result;
             }
             for (int i = vl_; i < VLMAX; i++) {
@@ -1819,9 +1760,9 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
         vtype_.vsew  = instr.getVsew();
         vtype_.vlmul = instr.getVlmul();
 
-        D(3, "lmul:" << vtype_.vlmul << " sew:" << vtype_.vsew  << " ediv: " << vtype_.vediv << "rsrc_" << iregs[rsrc0] << "VLMAX" << VLMAX);
+        D(3, "lmul:" << vtype_.vlmul << " sew:" << vtype_.vsew  << " ediv: " << vtype_.vediv << "rsrc_" << rsdata[0] << "VLMAX" << VLMAX);
 
-        int s0 = iregs[rsrc0];
+        int s0 = rsdata[0];
         if (s0 <= VLMAX) {
           vl_ = s0;
         } else if (s0 < (2 * VLMAX)) {
@@ -1829,7 +1770,7 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
         } else if (s0 >= (2 * VLMAX)) {
           vl_ = VLMAX;
         }        
-        iresult = vl_;
+        rddata = vl_;
       } break;
       default:
         std::abort();
@@ -1843,13 +1784,13 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
     switch (rdt) {
     case 1:      
       if (rdest) {
-        D(3, "[" << std::dec << t << "] Dest Register: r" << rdest << "=0x" << std::hex << std::hex << iresult);
-        iregs[rdest] = iresult;
+        D(3, "[" << std::dec << t << "] Dest Register: r" << rdest << "=0x" << std::hex << std::hex << rddata);
+        iregs[rdest] = rddata;
       }
       break;
     case 2:
-      D(3, "[" << std::dec << t << "] Dest Register: fr" << rdest << "=0x" << std::hex << std::hex << fresult);
-      fregs[rdest] = fresult;
+      D(3, "[" << std::dec << t << "] Dest Register: fr" << rdest << "=0x" << std::hex << std::hex << rddata);
+      fregs[rdest] = rddata;
       break;
     default:
       break;
diff --git a/simX/test_benchmark.sh b/simX/test_benchmark.sh
deleted file mode 100755
index 72f3b1ba..00000000
--- a/simX/test_benchmark.sh
+++ /dev/null
@@ -1,9 +0,0 @@
-#!/bin/bash
-
-echo start > results.txt
-
-make
-printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n"
-#./simX -a rv32i -i ../benchmarks/vector/vecadd/vx_vec_vecadd.hex  -s 1> emulator.debug
-#./simX -a rv32i -i ../benchmarks/vector/saxpy/vx_vec_saxpy.hex  -s 1> emulator.debug
-./simX -a rv32i -i ../benchmarks/vector/sgemm_nn/vx_vec_sgemm_nn.hex  -s 1> emulator.debug
diff --git a/simX/test_riscv.sh b/simX/test_riscv.sh
deleted file mode 100755
index 58fe3949..00000000
--- a/simX/test_riscv.sh
+++ /dev/null
@@ -1,142 +0,0 @@
-#!/bin/bash
-
-make
-echo start > results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-add.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-add.hex -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-addi.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-addi.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-and.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-and.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-andi.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-andi.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-auipc.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-auipc.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-beq.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-beq.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-bge.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-bge.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-bgeu.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-bgeu.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-blt.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-blt.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-bltu.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-bltu.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-bne.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-bne.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-jal.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-jal.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-jalr.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-jalr.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-lb.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-lb.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-lbu.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-lbu.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-lh.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-lh.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-lhu.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-lhu.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-lui.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-lui.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-lw.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-lw.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-or.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-or.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-ori.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-ori.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-sb.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-sb.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-sh.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-sh.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-simple.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-simple.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-sll.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-sll.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-slli.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-slli.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-slt.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-slt.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-slti.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-slti.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-sltiu.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-sltiu.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-sltu.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-sltu.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-sra.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-sra.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-srai.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-srai.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-srl.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-srl.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-srli.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-srli.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-sub.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-sub.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-sw.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-sw.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-xor.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-xor.hex  -s >> results.txt
-
-echo ./../benchmarks/isa/riscv_tests/rv32ui-p-xori.hex >> results.txt
-./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32ui-p-xori.hex  -s >> results.txt
-
-# echo ./../benchmarks/isa/riscv_tests/rv32um-p-div.hex >> results.txt
-# ./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32um-p-div.hex  -s >> results.txt
-
-# echo ./../benchmarks/isa/riscv_tests/rv32um-p-divu.hex >> results.txt
-# ./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32um-p-divu.hex  -s >> results.txt
-
-# echo ./../benchmarks/isa/riscv_tests/rv32um-p-mul.hex >> results.txt
-# ./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32um-p-mul.hex  -s >> results.txt
-
-# echo ./../benchmarks/isa/riscv_tests/rv32um-p-mulh.hex >> results.txt
-# ./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32um-p-mulh.hex  -s >> results.txt
-
-# echo ./../benchmarks/isa/riscv_tests/rv32um-p-mulhsu.hex >> results.txt
-# ./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32um-p-mulhsu.hex  -s >> results.txt
-
-# echo ./../benchmarks/isa/riscv_tests/rv32um-p-mulhu.hex >> results.txt
-# ./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32um-p-mulhu.hex  -s >> results.txt
-
-# echo ./../benchmarks/isa/riscv_tests/rv32um-p-rem.hex >> results.txt
-# ./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32um-p-rem.hex  -s >> results.txt
-
-# echo ./../benchmarks/isa/riscv_tests/rv32um-p-remu.hex >> results.txt
-# ./simX -a rv32i -i ../benchmarks/isa/riscv_tests/rv32um-p-remu.hex  -s >> results.txt
diff --git a/simX/test_vec.sh b/simX/test_vec.sh
deleted file mode 100755
index 1e3ee457..00000000
--- a/simX/test_vec.sh
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/bash
-
-echo start > results.txt
-
-# echo ../kernel/vortex_test.hex
-make
-printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n"
-./Vcache_simX -a rv32i -i ../rvvector/basic/vx_vector_main.hex -s 1> emulator.debug
diff --git a/simX/trace.h b/simX/trace.h
deleted file mode 100644
index 0bddd70b..00000000
--- a/simX/trace.h
+++ /dev/null
@@ -1,45 +0,0 @@
-
-#pragma once
-
-namespace vortex {
-
-  struct trace_inst_t {
-  	// Warp step
-    bool       valid;
-    unsigned   PC;
-
-    // Core scheduler
-    int        wid;
-
-    // Encoder
-    int        irs1;
-    int        irs2;    
-    int        ird;
-
-    // Floating-point
-    int        frs1;
-    int        frs2;
-    int        frs3;
-    int        frd;
-
-    // Vector extension
-    int        vrs1;
-    int        vrs2;
-    int        vrd;
-
-    // Instruction execute
-    bool       is_lw;
-    bool       is_sw;
-    unsigned * mem_addresses;
-
-    // dmem interface
-    unsigned long mem_stall_cycles;
-    unsigned long fetch_stall_cycles;
-
-    // Instruction execute
-    bool stall_warp;
-    bool wspawn;
-
-    bool stalled;
-  };
-}
\ No newline at end of file