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fixed opencl benchmarks

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This commit is contained in:
Blaise Tine
2020-03-09 09:55:16 -04:00
parent 857bb54f3f
commit 717a75ade8
64 changed files with 235418 additions and 1511751 deletions
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simX/obj_dir/Vcache_simX__verFiles.dat
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@@ -1,43 +1,43 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "--compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -CFLAGS -std=c++11 -fPIC -O3 -Wall -Wextra -pedantic -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1"
S 26 1407374883617647 1583036691 972658000 1583036691 972658000 "../rtl/./VX_define_synth.v"
S 283 1407374883617640 1583036691 969666100 1583036691 969666100 "../rtl/VX_countones.v"
S 7257 1407374883617646 1583036691 972658000 1583036691 972658000 "../rtl/VX_define.v"
S 8325 1407374883617648 1583036691 973655300 1583036691 973655300 "../rtl/VX_dmem_controller.v"
S 517 1407374883617652 1583036691 975649300 1583036691 975649300 "../rtl/VX_generic_priority_encoder.v"
S 683 1407374883617664 1583036691 981634100 1583036691 981634100 "../rtl/VX_priority_encoder_w_mask.v"
S 8590 1407374883617675 1583036691 985623400 1583036691 985623400 "../rtl/cache/VX_Cache_Bank.v"
S 748 1407374883617676 1583036691 986620700 1583036691 986620700 "../rtl/cache/VX_cache_bank_valid.v"
S 7349 1407374883617677 1583036691 986620700 1583036691 986620700 "../rtl/cache/VX_cache_data.v"
S 6476 1407374883617678 1583036691 987617400 1583036691 987617400 "../rtl/cache/VX_cache_data_per_index.v"
S 14645 1407374883617679 1583036691 987617400 1583036691 987617400 "../rtl/cache/VX_d_cache.v"
S 393 1407374883617692 1583036691 993601900 1583036691 993601900 "../rtl/interfaces/VX_dcache_request_inter.v"
S 215 1407374883617693 1583036691 994599200 1583036691 994599200 "../rtl/interfaces/VX_dcache_response_inter.v"
S 870 1407374883617694 1583036691 994599200 1583036691 994599200 "../rtl/interfaces/VX_dram_req_rsp_inter.v"
S 354 1407374883617709 1583036691 999585900 1583036691 999585900 "../rtl/interfaces/VX_icache_request_inter.v"
S 212 1407374883617710 1583036691 999585900 1583036691 999585900 "../rtl/interfaces/VX_icache_response_inter.v"
S 7257 1407374883617646 1583036691 972658000 1583036691 972658000 "../rtl/shared_memory/../VX_define.v"
S 676 1407374883617754 1583036692 20529900 1583036692 20529900 "../rtl/shared_memory/VX_bank_valids.v"
S 3038 1407374883617755 1583036692 21526400 1583036692 21526400 "../rtl/shared_memory/VX_priority_encoder_sm.v"
S 4962 1407374883617756 1583036692 22524600 1583036692 22524600 "../rtl/shared_memory/VX_shared_memory.v"
S 3207 1407374883617757 1583036692 22524600 1583036692 22524600 "../rtl/shared_memory/VX_shared_memory_block.v"
S 26 1407374883678355 1576858113 365285900 1576858113 365285900 "../rtl/./VX_define_synth.v"
S 283 1407374883678346 1576858113 363291200 1576858113 363291200 "../rtl/VX_countones.v"
S 7257 5629499534267235 1583028100 893817800 1583028100 893817800 "../rtl/VX_define.v"
S 8325 1407374883678357 1576858113 366283200 1576858113 366283200 "../rtl/VX_dmem_controller.v"
S 517 1407374883678365 1576858113 368277800 1576858113 368277800 "../rtl/VX_generic_priority_encoder.v"
S 683 1407374883678386 1576858113 374262300 1576858113 374262300 "../rtl/VX_priority_encoder_w_mask.v"
S 8590 1407374883678402 1576858113 378252100 1576858113 378252100 "../rtl/cache/VX_Cache_Bank.v"
S 748 1407374883678406 1576858113 379248400 1576858113 379248400 "../rtl/cache/VX_cache_bank_valid.v"
S 7349 1407374883678408 1576858113 380246000 1576858113 380246000 "../rtl/cache/VX_cache_data.v"
S 6476 1407374883678409 1576858113 380246000 1576858113 380246000 "../rtl/cache/VX_cache_data_per_index.v"
S 14645 1407374883678410 1576858113 381243100 1576858113 381243100 "../rtl/cache/VX_d_cache.v"
S 393 1407374883678432 1576858113 386229700 1576858113 386229700 "../rtl/interfaces/VX_dcache_request_inter.v"
S 215 1407374883678434 1576858113 387227400 1576858113 387227400 "../rtl/interfaces/VX_dcache_response_inter.v"
S 870 1407374883678435 1576858113 387227400 1576858113 387227400 "../rtl/interfaces/VX_dram_req_rsp_inter.v"
S 354 1407374883678447 1576858113 392213800 1576858113 392213800 "../rtl/interfaces/VX_icache_request_inter.v"
S 212 1407374883678448 1576858113 392213800 1576858113 392213800 "../rtl/interfaces/VX_icache_response_inter.v"
S 7257 5629499534267235 1583028100 893817800 1583028100 893817800 "../rtl/shared_memory/../VX_define.v"
S 676 1407374883678497 1576858113 417147000 1576858113 417147000 "../rtl/shared_memory/VX_bank_valids.v"
S 3038 1407374883678498 1576858113 418144200 1576858113 418144200 "../rtl/shared_memory/VX_priority_encoder_sm.v"
S 4962 1407374883678499 1576858113 418144200 1576858113 418144200 "../rtl/shared_memory/VX_shared_memory.v"
S 3207 1407374883678500 1576858113 419141900 1576858113 419141900 "../rtl/shared_memory/VX_shared_memory_block.v"
S 5279832 1125899907857040 1579658333 790142700 1519110675 0 "/usr/bin/verilator_bin"
S 3144 1407374883617983 1583036693 278327800 1583036693 278327800 "cache_simX.v"
T 390173 4222124650721525 1583038884 772480200 1583038884 772480200 "obj_dir/Vcache_simX.cpp"
T 28278 5066549580853492 1583038884 765499600 1583038884 765499600 "obj_dir/Vcache_simX.h"
T 2365 18858823439675736 1583038884 803378700 1583038884 803378700 "obj_dir/Vcache_simX.mk"
T 643931 2533274790457603 1583038884 802128000 1583038884 802128000 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp"
T 23659 2533274790457602 1583038884 788131800 1583038884 788131800 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h"
T 578414 2533274790457601 1583038884 787134700 1583038884 787134700 "obj_dir/Vcache_simX_VX_Cache_Bank__pi9.cpp"
T 23321 4222124650721534 1583038884 776161100 1583038884 776161100 "obj_dir/Vcache_simX_VX_Cache_Bank__pi9.h"
T 1024 2251799813746939 1583038884 775163700 1583038884 775163700 "obj_dir/Vcache_simX_VX_dcache_request_inter.cpp"
T 1561 5348024557564153 1583038884 774165800 1583038884 774165800 "obj_dir/Vcache_simX_VX_dcache_request_inter.h"
T 999 2533274790457592 1583038884 773299100 1583038884 773299100 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
T 1557 2814749767168246 1583038884 773299100 1583038884 773299100 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
T 6004 14073748835594442 1583038884 720643500 1583038884 720643500 "obj_dir/Vcache_simX__Syms.cpp"
T 2455 3096224743878468 1583038884 719619200 1583038884 719619200 "obj_dir/Vcache_simX__Syms.h"
T 1114242 5066549580853489 1583038884 763504200 1583038884 763504200 "obj_dir/Vcache_simX__Trace.cpp"
T 1433229 3377699720589552 1583038884 745891000 1583038884 745891000 "obj_dir/Vcache_simX__Trace__Slow.cpp"
T 1439 1688849860325816 1583038884 804364500 1583038884 804364500 "obj_dir/Vcache_simX__ver.d"
T 0 0 1583038884 836313300 1583038884 836313300 "obj_dir/Vcache_simX__verFiles.dat"
T 1392 2251799813746948 1583038884 802128000 1583038884 802128000 "obj_dir/Vcache_simX_classes.mk"
S 3144 1407374883678789 1576858114 576047000 1576858114 576047000 "cache_simX.v"
T 390173 22236523160217637 1583612769 755410900 1583612769 755410900 "obj_dir/Vcache_simX.cpp"
T 28278 15481123719153127 1583612769 748398500 1583612769 748398500 "obj_dir/Vcache_simX.h"
T 2365 10133099161813405 1583612769 784337500 1583612769 784337500 "obj_dir/Vcache_simX.mk"
T 643931 3940649674155161 1583612769 783340900 1583612769 783340900 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp"
T 23659 5348024557708078 1583612769 771372900 1583612769 771372900 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h"
T 578414 15481123719285399 1583612769 770399200 1583612769 770399200 "obj_dir/Vcache_simX_VX_Cache_Bank__pi9.cpp"
T 23321 11258999068615501 1583612769 760411300 1583612769 760411300 "obj_dir/Vcache_simX_VX_Cache_Bank__pi9.h"
T 1024 8725724278219266 1583612769 757374600 1583612769 757374600 "obj_dir/Vcache_simX_VX_dcache_request_inter.cpp"
T 1561 50102545854682183 1583612769 757374600 1583612769 757374600 "obj_dir/Vcache_simX_VX_dcache_request_inter.h"
T 999 10414574138447661 1583612769 756377900 1583612769 756377900 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
T 1557 6755399441176779 1583612769 756377900 1583612769 756377900 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
T 6004 11821949021903061 1583612769 706686400 1583612769 706686400 "obj_dir/Vcache_simX__Syms.cpp"
T 2455 32088147345022597 1583612769 705722700 1583612769 705722700 "obj_dir/Vcache_simX__Syms.h"
T 1114242 10414574138355386 1583612769 747434700 1583612769 747434700 "obj_dir/Vcache_simX__Trace.cpp"
T 1433229 12103423998619303 1583612769 729412200 1583612769 729412200 "obj_dir/Vcache_simX__Trace__Slow.cpp"
T 1439 6755399441290555 1583612769 784337500 1583612769 784337500 "obj_dir/Vcache_simX__ver.d"
T 0 0 1583612769 844870300 1583612769 844870300 "obj_dir/Vcache_simX__verFiles.dat"
T 1392 4785074604292692 1583612769 784337500 1583612769 784337500 "obj_dir/Vcache_simX_classes.mk"

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